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| revision date: sep. 13, 2007 32 hardware manual renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series h8sx1648 r5f61648 h8sx1644 r5f61644 h8sx1642 r5f61642 rev.1.00 rej09b0365-0100 h8sx/1648 group all information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by renesas technology corp. without notice. please review the latest information published by renesas technology corp. through various means, including the renesas technology corp. website (http://www.renesas.com).
rev. 1.00 sep. 13, 2007 page ii of xxviii rev. 1.00 sep. 13, 2007 page iii of xxviii 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials rev. 1.00 sep. 13, 2007 page iv of xxviii general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. rev. 1.00 sep. 13, 2007 page v of xxviii how to use this manual 1. objective and target users this manual was written to explain the hardware functions and electrical characteristics of this lsi to the target users, i.e. those who will be using this lsi in the design of application systems. target users are expect ed to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. this manual is organized in the following items: an overview of the product, descriptions of the cpu, system control functions, and periphera l functions, electrical characteristics of the device, and usage notes. when designing an application system that includ es this lsi, take all points to note into account. points to note are given in their contex ts and at the final part of each section, and in the section giving usage notes. the list of revisions is a summary of major points of revision or addition for earlier versions. it does not cover all revised items. for details on the revised points, see the actual locations in the manual. the following documents have been prepared for the h8sx/1648 group. before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. document type contents document title document no. data sheet overview of hardware and electrical characteristics ? ? hardware manual hardware specifications (pin assignments, memory maps, peripheral specificat ions, electrical characteristics, and timing charts) and descriptions of operation h8sx/1648 group hardware manual this manual software manual detailed descriptions of the cpu and instruction set h8sx family software manual rej09b0102 application note exampl es of applications and sample programs renesas technical update preliminary report on the specifications of a product, document, etc. the latest versions are available from our web site. rev. 1.00 sep. 13, 2007 page vi of xxviii 2. description of numbers and symbols aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. cmcsr indicates compare match generation, enables or disables interrupts, and selects the counter input clock. generation of a wdtovf signal or interrupt initializes the tcnt value to 0. 14.3 operation the style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [example] cmcsr_0: indicates the cmcsr register for the compare-match timer of channel 0. in descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (1) overall notation (2) register notation rev. 0.50, 10/04, page 416 of 914 14.2.2 compare match control/status register_0, _1 (cmcsr_0, cmcsr_1) 14.3.1 interval count operation (4) (3) (2) binary numbers are given as b'nnnn (b' may be omitted if the number is obviously binary), hexadecimal numbers are given as h'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [examples] binary: b'11 or 11 hexadecimal: h'efa0 or 0xefa0 decimal: 1234 (3) number notation an overbar on the name indicates that a signal or pin is active-low. [example] wdtovf note: the bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. (4) notation for active-low when an internal clock is selected with the cks1 and cks0 bits in cmcsr and the str bit in cmstr is set to 1, cmcnt starts incrementing using the selected clock. when the values in cmcnt and the compare match constant register (cmcor) match, cmcnt is cleared to h'0000 and the cmf flag in cmcsr is set to 1. when the cks1 and cks0 bits are set to b'01 at this time, a f/4 clock is selected. rev. 1.00 sep. 13, 2007 page vii of xxviii 3. description of registers each register description includes a bit chart, illu strating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. the standard format and notation for bit charts and tables are described below. indicates the bit number or numbers. in the case of a 32-bit register, the bits are arranged in order from 31 to 0. in the case of a 16-bit register, the bits are arranged in order from 15 to 0. indicates the name of the bit or bit field. when the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., asid[3:0]). a reserved bit is indicated by " ? ". certain kinds of bits, such as those of timer counters, are not assigned bit names. in such cases, the entry under bit name is blank. (1) bit (2) bit name indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: the initial value is 0 1: the initial value is 1 ? : the initial value is undefined (3) initial value for each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. the notation is as follows: r/w: r/(w): r: w: the bit or field is readable and writable. the bit or field is readable and writable. however, writing is only performed to flag clearing. the bit or field is readable. "r" is indicated for all reserved bits. when writing to the register, write the value under initial value in the bit chart to reserved bits or fields. the bit or field is writable. note: the bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (4) r/w describes the function of the bit or field and specifies the values for writing. (5) description bit 15 13 to 11 10 9 0 all 0 0 0 1 r r/w r r address identifier these bits enable or disable the pin function. reserved this bit is always read as 0. reserved this bit is always read as 1. ? asid2 to asid0 ? ? ? bit name initial value r/w description [bit chart] [table of bits] 14 1514131211109876543210 bit: initial value: r/w: 0000001000000000 r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w ? asid2 ?????? acmp2 q ife ? asid1 asid0 acmp1 acmp0 ? 0 r (1) (2) (3) (4) (5) reserved these bits are always read as 0. rev. 1.00 sep. 13, 2007 page viii of xxviii 4. description of abbreviations the abbreviations used in this manual are listed below. ? abbreviations specific to this product abbreviation description bsc bus controller cpg clock pulse generator dtc data transfer controller intc interrupt controller ppg programmable pulse generator sci serial communication interface tmr 8-bit timer tpu 16-bit timer pulse unit wdt watchdog timer ? abbreviations other than those listed above abbreviation description acia asynchronous communication interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus (iebus is a trademark of nec electronics corporation.) i/o input/output irda infrared data association lsb least significant bit msb most significant bit nc no connection pll phase-locked loop pwm pulse width modulation sfr special function register sim subscriber identity module uart universal asynchronous receiver/transmitter vco voltage-controlled oscillator all trademarks and registered trademarks ar e the property of th eir respective owners. rev. 1.00 sep. 13, 2007 page ix of xxviii contents section 1 overview..................................................................................................1 1.1 features....................................................................................................................... .......... 1 1.1.1 applicat ions .......................................................................................................... 1 1.1.2 overview of functions.......................................................................................... 2 1.2 list of products............................................................................................................... ...... 8 1.3 block diagram.................................................................................................................. .... 9 1.4 pin assign ments ................................................................................................................ .10 1.4.1 pin assignments ................................................................................................. 10 1.4.2 correspondence between pin config uration and operating modes ................... 11 1.4.3 pin functions ...................................................................................................... 17 section 2 cpu........................................................................................................25 2.1 features....................................................................................................................... ........ 25 2.2 cpu operating modes........................................................................................................ 27 2.2.1 normal mode...................................................................................................... 27 2.2.2 middle mode....................................................................................................... 29 2.2.3 advanced mode.................................................................................................. 30 2.2.4 maximum mode ................................................................................................. 31 2.3 instructio n fetch .............................................................................................................. ... 33 2.4 address space.................................................................................................................. ... 33 2.5 registers ...................................................................................................................... ....... 34 2.5.1 general registers................................................................................................ 35 2.5.2 program counter (pc) ........................................................................................ 36 2.5.3 condition-code re gister (ccr)......................................................................... 37 2.5.4 extended control re gister (exr) ...................................................................... 38 2.5.5 vector base re gister (vbr)............................................................................... 39 2.5.6 short address base register (sbr).................................................................... 39 2.5.7 multiply-accumulate re gister (mac) ............................................................... 39 2.5.8 initial values of cpu regist ers .......................................................................... 39 2.6 data formats................................................................................................................... .... 40 2.6.1 general register data formats ........................................................................... 40 2.6.2 memory data formats ........................................................................................ 41 2.7 instruction set ................................................................................................................ ..... 42 2.7.1 instructions and a ddressing modes.................................................................... 44 2.7.2 table of instructions cl assified by function ...................................................... 48 2.7.3 basic instructio n formats ................................................................................... 58 rev. 1.00 sep. 13, 2007 page x of xxviii 2.8 addressing modes and effec tive address ca lculation....................................................... 59 2.8.1 register di rect?rn ........................................................................................... 59 2.8.2 register indi rect?@ern................................................................................... 60 2.8.3 register indirect with displacement ?@(d:2, ern), @(d:16, ern), or @(d:32, ern).................................................................................................. 60 2.8.4 index register indirect with displacement?@(d:16,r nl.b), @(d:32,rnl.b), @(d:16,rn.w), @(d:32,rn.w), @(d:16 ,ern.l), or @(d:32,ern.l) ................. 60 2.8.5 register indirect with post-incremen t, pre-decrement, pre-increment, or post-decrement?@ern + , @ ? ern, @ + ern, or @ern ? ............................. 61 2.8.6 absolute address?@aa:8, @ aa:16, @aa:24, or @aa:32................................... 62 2.8.7 immediate?#xx ................................................................................................. 63 2.8.8 program-counter relative?@(d: 8, pc) or @(d:16, pc) .................................. 63 2.8.9 program-counter relative with index register?@(rnl.b, pc), @(rn.w, pc), or @(ern.l, pc) ........................................................................ 63 2.8.10 memory indirect?@@aa:8 ............................................................................... 64 2.8.11 extended memory in direct?@@vec:7 ............................................................. 65 2.8.12 effective address calculation ............................................................................ 65 2.8.13 mova instruction.............................................................................................. 67 2.9 processing states .............................................................................................................. .. 68 section 3 mcu operating modes ......................................................................... 69 3.1 operating mode selection .................................................................................................. 69 3.2 register de scriptions.......................................................................................................... 70 3.2.1 mode control regi ster (mdcr) ........................................................................ 70 3.2.2 system control re gister (s yscr)..................................................................... 73 3.3 operating mode descriptions ............................................................................................. 75 3.3.1 mode 1................................................................................................................ 75 3.3.2 mode 2................................................................................................................ 75 3.3.3 mode 3................................................................................................................ 75 3.3.4 mode 4................................................................................................................ 75 3.3.5 mode 5................................................................................................................ 75 3.3.6 mode 6................................................................................................................ 76 3.3.7 mode 7................................................................................................................ 76 3.3.8 pin functions ...................................................................................................... 77 3.4 address map.................................................................................................................... ... 77 3.4.1 address map....................................................................................................... 77 section 4 resets..................................................................................................... 85 4.1 types of rese ts................................................................................................................ ... 85 4.2 input/output pin ............................................................................................................... .. 86 rev. 1.00 sep. 13, 2007 page xi of xxviii 4.3 register de scriptions.......................................................................................................... 87 4.3.1 reset status regi ster (rstsr)........................................................................... 87 4.3.2 reset control/status re gister (rstcsr)........................................................... 88 4.4 pin reset ...................................................................................................................... ....... 89 4.5 deep software st andby reset............................................................................................. 89 4.6 watchdog time r reset ....................................................................................................... 89 4.7 determination of rese t generation source......................................................................... 89 section 5 exception handling ...............................................................................91 5.1 exception handling t ypes and priority.............................................................................. 91 5.2 exception sources and exception handling vector table ................................................. 92 5.3 reset .......................................................................................................................... ......... 94 5.3.1 reset exceptio n handling................................................................................... 94 5.3.2 interrupts after reset........................................................................................... 95 5.3.3 on-chip peripheral functions after reset release ............................................. 95 5.4 traces......................................................................................................................... ......... 97 5.5 address error.................................................................................................................. .... 98 5.5.1 address error source.......................................................................................... 98 5.5.2 address error exce ption handling ..................................................................... 99 5.6 interrupts..................................................................................................................... ...... 100 5.6.1 interrupt sources............................................................................................... 100 5.6.2 interrupt exceptio n handling ........................................................................... 101 5.7 instruction excep tion handlin g ........................................................................................ 101 5.7.1 trap instru ction................................................................................................. 101 5.7.2 sleep instruction excep tion hand ling .............................................................. 102 5.7.3 exception handling by i llegal instru ction ........................................................ 103 5.8 stack status after ex ception hand ling.............................................................................. 104 5.9 usage note..................................................................................................................... ... 105 section 6 interrupt controller ..............................................................................107 6.1 features....................................................................................................................... ...... 107 6.2 input/output pins.............................................................................................................. 109 6.3 register desc riptions........................................................................................................ 10 9 6.3.1 interrupt control re gister (i ntcr) ................................................................. 110 6.3.2 cpu priority control re gister (cpu pcr) ....................................................... 111 6.3.3 interrupt priority registers a to i, k to o, q, and r (ipra to ipri, iprk to ipro, iprq, an d iprr).................................................................................... 112 6.3.4 irq enable regi ster (ier) ............................................................................... 114 6.3.5 irq sense control registers h and l (iscrh, iscrl).................................. 116 6.3.6 irq status regi ster (isr)................................................................................. 121 rev. 1.00 sep. 13, 2007 page xii of xxviii 6.3.7 software standby release irq en able register (ssier) ................................ 122 6.4 interrupt sources.............................................................................................................. .123 6.4.1 external interrupts ............................................................................................ 123 6.4.2 internal interrupts ............................................................................................. 124 6.5 interrupt exception hand ling vector table...................................................................... 125 6.6 interrupt control modes and interrupt oper ation............................................................. 131 6.6.1 interrupt control mode 0.................................................................................. 131 6.6.2 interrupt control mode 2.................................................................................. 133 6.6.3 interrupt exception ha ndling sequ ence ........................................................... 135 6.6.4 interrupt respon se times ................................................................................. 136 6.6.5 dtc and dmac activatio n by interr upt ......................................................... 137 6.7 cpu priority control functi on over dtc and dmac.................................................... 140 6.8 usage notes .................................................................................................................... .. 143 6.8.1 conflict between interrupt ge neration and di sabling ...................................... 143 6.8.2 instructions that di sable interrupts................................................................... 144 6.8.3 times when interrupt s are disabled ................................................................. 144 6.8.4 interrupts during execution of eepmov inst ruction ...................................... 144 6.8.5 interrupts during execution of mo vmd and movsd instructions................ 144 6.8.6 interrupts of periph eral modu les ...................................................................... 145 section 7 user break controller (ubc).............................................................. 147 7.1 features....................................................................................................................... ...... 147 7.2 block diagram.................................................................................................................. 148 7.3 register desc riptions........................................................................................................ 14 9 7.3.1 break address register n (bar a, barb, barc, bard) ............................ 150 7.3.2 break address mask register n (b amra, bamrb, bamrc, bamrd) .... 151 7.3.3 break control register n (brcra, brcrb, brcrc, brcrd) ................... 152 7.4 operation ...................................................................................................................... .... 154 7.4.1 setting of break cont rol conditions................................................................. 154 7.4.2 pc break........................................................................................................... 154 7.4.3 condition matc h flag ....................................................................................... 155 7.5 usage notes .................................................................................................................... .. 156 section 8 bus controller (bsc) .......................................................................... 159 8.1 features....................................................................................................................... ...... 159 8.2 register desc riptions........................................................................................................ 16 2 8.2.1 bus width control re gister (a bwcr)............................................................ 163 8.2.2 access state control re gister (a stcr) .......................................................... 164 8.2.3 wait control registers a and b (wtcra , wtcrb) ..................................... 165 8.2.4 read strobe timing cont rol register (rdncr) ............................................. 170 rev. 1.00 sep. 13, 2007 page xiii of xxviii 8.2.5 cs assertion period contro l registers (csacr) ............................................ 171 8.2.6 idle control register (idlcr) ......................................................................... 174 8.2.7 bus control regist er 1 (bcr1) ........................................................................ 176 8.2.8 bus control regist er 2 (bcr2) ........................................................................ 178 8.2.9 endian control regist er (endiancr)............................................................ 179 8.2.10 sram mode control re gister (sra mcr) ..................................................... 180 8.2.11 burst rom interface control register (b romcr)......................................... 181 8.2.12 address/data multiplexed i/o control register (mpxcr) ............................. 183 8.3 bus configur ation............................................................................................................. 1 84 8.4 multi-clock function and numb er of access cycles ...................................................... 185 8.5 external bus................................................................................................................... ... 189 8.5.1 input/output pins.............................................................................................. 189 8.5.2 area division.................................................................................................... 192 8.5.3 chip select signals ........................................................................................... 193 8.5.4 external bus interface....................................................................................... 195 8.5.5 area and external bus interface ....................................................................... 199 8.5.6 endian and data alignment.............................................................................. 204 8.6 basic bus in terface ........................................................................................................... 2 07 8.6.1 data bus............................................................................................................ 207 8.6.2 i/o pins used for ba sic bus inte rface .............................................................. 207 8.6.3 basic timi ng..................................................................................................... 208 8.6.4 wait contro l ..................................................................................................... 214 8.6.5 read strobe ( rd ) timing................................................................................. 216 8.6.6 extension of chip select ( cs ) assertion period............................................... 217 8.6.7 dack signal output timing ........................................................................... 219 8.7 byte control sram interface .......................................................................................... 220 8.7.1 byte control sram space settin g................................................................... 220 8.7.2 data bus............................................................................................................ 220 8.7.3 i/o pins used for byte co ntrol sram in terface ............................................. 221 8.7.4 basic timi ng..................................................................................................... 222 8.7.5 wait contro l ..................................................................................................... 224 8.7.6 read strobe ( rd ).............................................................................................. 226 8.7.7 extension of chip select ( cs ) assertion period............................................... 226 8.7.8 dack signal output timing ........................................................................... 226 8.8 burst rom in terface ........................................................................................................ 228 8.8.1 burst rom space setting................................................................................. 228 8.8.2 data bus............................................................................................................ 228 8.8.3 i/o pins used for bu rst rom interface............................................................ 229 8.8.4 basic timi ng..................................................................................................... 230 8.8.5 wait contro l ..................................................................................................... 232 rev. 1.00 sep. 13, 2007 page xiv of xxviii 8.8.6 read strobe ( rd ) timing................................................................................. 232 8.8.7 extension of chip select ( cs ) assertion period............................................... 232 8.9 address/data multiplexe d i/o inte rface........................................................................... 233 8.9.1 address/data multiplexed i/o space setting ................................................... 233 8.9.2 address/data multiplex .................................................................................... 233 8.9.3 data bus ........................................................................................................... 233 8.9.4 i/o pins used for address/data multiplexed i/o interface.............................. 234 8.9.5 basic timi ng..................................................................................................... 235 8.9.6 address cycle control...................................................................................... 237 8.9.7 wait cont rol ..................................................................................................... 238 8.9.8 read strobe ( rd ) timing................................................................................. 238 8.9.9 extension of chip select ( cs ) assertion period............................................... 240 8.9.10 dack signal output timing ........................................................................... 242 8.10 idle cycle..................................................................................................................... ..... 243 8.10.1 operation .......................................................................................................... 243 8.10.2 pin states in id le cycle..................................................................................... 252 8.11 bus rel ease.................................................................................................................... ... 253 8.11.1 operation .......................................................................................................... 253 8.11.2 pin states in external bus released state ........................................................ 254 8.11.3 transition timing ............................................................................................. 255 8.12 internal bus................................................................................................................... .... 256 8.12.1 access to internal address sp ace ..................................................................... 256 8.13 write data buffe r function .............................................................................................. 258 8.13.1 write data buffer function fo r external data bus .......................................... 258 8.13.2 write data buffer function fo r peripheral modules ........................................ 259 8.14 bus arbitr ation ................................................................................................................ .260 8.14.1 operation .......................................................................................................... 260 8.14.2 bus transfer timing......................................................................................... 261 8.15 bus controller operat ion in reset.................................................................................... 262 8.16 usage notes .................................................................................................................... .. 263 section 9 dma controller (dmac)................................................................... 265 9.1 features....................................................................................................................... ...... 265 9.2 input/output pins.............................................................................................................. 268 9.3 register desc riptions........................................................................................................ 26 9 9.3.1 dma source address re gister (dsar) .......................................................... 270 9.3.2 dma destination address register ( ddar) .................................................. 271 9.3.3 dma offset regist er (dofr).......................................................................... 272 9.3.4 dma transfer count re gister (d tcr) ........................................................... 273 9.3.5 dma block size regi ster (dbsr) .................................................................. 274 rev. 1.00 sep. 13, 2007 page xv of xxviii 9.3.6 dma mode control re gister (d mdr)............................................................ 275 9.3.7 dma address control re gister (dacr) ......................................................... 284 9.3.8 dma module request select register (dmrsr) ........................................... 290 9.4 transfer modes ................................................................................................................. 290 9.5 operations..................................................................................................................... .... 291 9.5.1 address modes ................................................................................................. 291 9.5.2 transfer modes ................................................................................................. 295 9.5.3 activation so urces............................................................................................ 300 9.5.4 bus access modes ............................................................................................ 302 9.5.5 extended repeat ar ea function ....................................................................... 304 9.5.6 address update functio n using offset ............................................................. 307 9.5.7 register during dma transf er ......................................................................... 311 9.5.8 priority of channels .......................................................................................... 316 9.5.9 dma basic bus cycle...................................................................................... 318 9.5.10 bus cycles in dual address mode ................................................................... 319 9.5.11 bus cycles in singl e address mode................................................................. 328 9.6 dma transfer end ........................................................................................................... 333 9.7 relationship among dmac an d other bus ma sters ........................................................ 336 9.7.1 cpu priority control fu nction over dmac ................................................... 336 9.7.2 bus arbitration among dmac and other bus masters ................................... 337 9.8 interrupt sources.............................................................................................................. .338 9.9 usage notes .................................................................................................................... .. 341 section 10 data transfer controller (dtc) ........................................................343 10.1 features....................................................................................................................... ...... 343 10.2 register desc riptions........................................................................................................ 34 5 10.2.1 dtc mode register a (mra) ......................................................................... 346 10.2.2 dtc mode regist er b (m rb).......................................................................... 347 10.2.3 dtc source address re gister (sar)............................................................... 348 10.2.4 dtc destination address register (d ar)....................................................... 349 10.2.5 dtc transfer count re gister a (cra) ........................................................... 349 10.2.6 dtc transfer count re gister b (crb)............................................................ 350 10.2.7 dtc enable registers a to h (dtcera to dtcerh) .................................... 350 10.2.8 dtc control regist er (dtccr) ...................................................................... 351 10.2.9 dtc vector base regi ster (dtcvbr)............................................................ 353 10.3 activation sources............................................................................................................ 3 53 10.4 location of transfer informati on and dtc vector table ................................................ 353 10.5 operation ...................................................................................................................... .... 358 10.5.1 bus cycle di vision ........................................................................................... 360 10.5.2 transfer information re ad skip fu nction ........................................................ 362 rev. 1.00 sep. 13, 2007 page xvi of xxviii 10.5.3 transfer information writ eback skip function................................................ 363 10.5.4 normal transfer mode ..................................................................................... 363 10.5.5 repeat transfer mode ...................................................................................... 364 10.5.6 block transfer mode ........................................................................................ 366 10.5.7 chain transfer .................................................................................................. 367 10.5.8 operation timing.............................................................................................. 368 10.5.9 number of dtc exec ution cycl es ................................................................... 370 10.5.10 dtc bus releas e timing ................................................................................. 371 10.5.11 dtc priority level cont rol to the cpu ........................................................... 371 10.6 dtc activation by interrupt............................................................................................. 372 10.7 examples of use of the dtc............................................................................................ 373 10.7.1 normal transfer mode ..................................................................................... 373 10.7.2 chain transfer .................................................................................................. 373 10.7.3 chain transfer when counter = 0..................................................................... 374 10.8 interrupt sources.............................................................................................................. .376 10.9 usage notes .................................................................................................................... .. 376 10.9.1 module stop st ate settin g ................................................................................ 376 10.9.2 on-chip ram .................................................................................................. 376 10.9.3 dmac transfer en d interr upt.......................................................................... 376 10.9.4 dtce bit se tting.............................................................................................. 376 10.9.5 chain transfer .................................................................................................. 377 10.9.6 transfer information start address, source address, and destination address ................................................................................... 377 10.9.7 transfer informati on modification ................................................................... 377 10.9.8 endian format .................................................................................................. 377 section 11 i/o ports............................................................................................. 379 11.1 register desc riptions........................................................................................................ 38 8 11.1.1 data direction register (pnddr) (n = 1, 2, 3, 6, a, to f, h to k, and n) ....... 389 11.1.2 data register (pndr) (n = 1, 2, 3, 6, a, to f, h to k, and n).......................... 390 11.1.3 port register (portn) (n = 1 to 6, a to f, h to k, and n) .............................. 390 11.1.4 input buffer control register (pnicr) (n = 1 to 6, a to f, h to k, and n) ..... 391 11.1.5 pull-up mos control register (pnpcr) (n = d to f and h to k)................... 392 11.1.6 open-drain control register (pnodr) (n = 2 and f)...................................... 393 11.2 output buffer control....................................................................................................... 393 11.2.1 port 1................................................................................................................. 394 11.2.2 port 2................................................................................................................. 398 11.2.3 port 3................................................................................................................. 402 11.2.4 port 5................................................................................................................. 405 11.2.5 port 6................................................................................................................. 406 rev. 1.00 sep. 13, 2007 page xvii of xxviii 11.2.6 port a................................................................................................................ 409 11.2.7 port b ................................................................................................................ 414 11.2.8 port c ................................................................................................................ 418 11.2.9 port d................................................................................................................ 420 11.2.10 port e ................................................................................................................ 421 11.2.11 port f ................................................................................................................ 422 11.2.12 port h................................................................................................................ 426 11.2.13 port i ................................................................................................................. 427 11.2.14 port j ................................................................................................................. 428 11.2.15 port k................................................................................................................ 432 11.2.16 port n................................................................................................................ 436 11.3 port function c ontroller ................................................................................................... 447 11.3.1 port function control re gister 0 (pfcr0)....................................................... 448 11.3.2 port function control re gister 1 (pfcr1)....................................................... 448 11.3.3 port function control re gister 2 (pfcr2)....................................................... 450 11.3.4 port function control re gister 4 (pfcr4)....................................................... 451 11.3.5 port function control re gister 6 (pfcr6)....................................................... 453 11.3.6 port function control re gister 7 (pfcr7)....................................................... 454 11.3.7 port function control re gister 9 (pfcr9)....................................................... 456 11.3.8 port function control re gister a ( pfcra) ..................................................... 458 11.3.9 port function control re gister b ( pfcrb)...................................................... 460 11.3.10 port function control re gister c ( pfcrc)...................................................... 461 11.3.11 port function control re gister d ( pfcrd) ..................................................... 463 11.4 usage notes .................................................................................................................... .. 464 11.4.1 notes on input buffer contro l register (icr ) setting ..................................... 464 11.4.2 notes on port function control register (pfcr) settings............................... 464 section 12 16-bit timer pulse unit (tpu) .........................................................465 12.1 features....................................................................................................................... ...... 465 12.2 input/output pins.............................................................................................................. 472 12.3 register desc riptions........................................................................................................ 47 4 12.3.1 timer control regi ster (t cr).......................................................................... 479 12.3.2 timer mode regist er (tmdr) ......................................................................... 484 12.3.3 timer i/o control re gister (tior) .................................................................. 486 12.3.4 timer interrupt enable register (tier) ........................................................... 504 12.3.5 timer status regi ster (tsr)............................................................................. 505 12.3.6 timer counter (tcnt)..................................................................................... 509 12.3.7 timer general regi ster (tgr) ......................................................................... 509 12.3.8 timer start regist er (tstr) ............................................................................ 510 12.3.9 timer synchronous re gister (tsyr)............................................................... 511 rev. 1.00 sep. 13, 2007 page xviii of xxviii 12.4 operation ...................................................................................................................... .... 512 12.4.1 basic func tions................................................................................................. 512 12.4.2 synchronous op eration..................................................................................... 518 12.4.3 buffer operation............................................................................................... 520 12.4.4 cascaded oper ation .......................................................................................... 524 12.4.5 pwm modes..................................................................................................... 526 12.4.6 phase counting mode....................................................................................... 531 12.5 interrupt sources.............................................................................................................. .538 12.6 dtc activa tion ................................................................................................................ 5 40 12.7 dmac activa tion ............................................................................................................ 540 12.8 a/d converter ac tivation................................................................................................. 540 12.9 operation timing.............................................................................................................. 5 41 12.9.1 input/output timing ......................................................................................... 541 12.9.2 interrupt signal timing .................................................................................... 545 12.10 usage notes .................................................................................................................... .. 549 12.10.1 module stop func tion settin g .......................................................................... 549 12.10.2 input clock rest rictions ................................................................................... 549 12.10.3 caution on cycl e setting .................................................................................. 550 12.10.4 conflict between tcnt write and clear oper ations....................................... 550 12.10.5 conflict between tcnt write an d increment operations ............................... 551 12.10.6 conflict between tgr write and compare match........................................... 551 12.10.7 conflict between buffer register write and comp are match .......................... 552 12.10.8 conflict between tgr read and input capture ............................................... 552 12.10.9 conflict between tgr write and input capture .............................................. 553 12.10.10 conflict between buffer register write and inpu t capture.............................. 554 12.10.11 conflict between overflow/underfl ow and counter clearing ......................... 555 12.10.12 conflict between tcnt write and overflow/underflow ................................ 555 12.10.13 multiplexing of i/o pins ................................................................................... 556 12.10.14 ppg1 setting when tpu1 pin is used.............................................................. 556 12.10.15 interrupts and module stop mode .................................................................... 556 section 13 programmable pulse generator (ppg).............................................. 557 13.1 features....................................................................................................................... ...... 557 13.2 input/output pins.............................................................................................................. 560 13.3 register desc riptions........................................................................................................ 56 2 13.3.1 next data enable register s h, l (nderh, nderl) ..................................... 563 13.3.2 output data registers h, l (podrh, podrl)............................................... 566 13.3.3 next data registers h, l (ndrh, ndrl) ...................................................... 568 13.3.4 ppg output control register (pcr) ................................................................ 573 13.3.5 ppg output mode re gister (pmr) .................................................................. 575 rev. 1.00 sep. 13, 2007 page xix of xxviii 13.4 operation ...................................................................................................................... .... 579 13.4.1 output timing................................................................................................... 579 13.4.2 sample setup procedure for normal pulse output........................................... 580 13.4.3 example of normal pulse output (exa mple of 5-phase pulse output)............ 582 13.4.4 non-overlapping pu lse output......................................................................... 583 13.4.5 sample setup procedure for non- overlapping pulse output ........................... 585 13.4.6 example of non-overlapping pulse output (example of 4-phase complementary non-overlapp ing pulse output) ............................................. 587 13.4.7 inverted pulse output ....................................................................................... 589 13.4.8 pulse output triggered by input capture ......................................................... 590 13.5 usage notes .................................................................................................................... .. 591 13.5.1 module stop stat e setting ................................................................................ 591 13.5.2 operation of pulse output pins......................................................................... 591 13.5.3 tpu setting when ppg1 is in use.................................................................... 591 section 14 8-bit timers (tmr)...........................................................................593 14.1 features....................................................................................................................... ...... 593 14.2 input/output pins.............................................................................................................. 598 14.3 register desc riptions........................................................................................................ 59 9 14.3.1 timer counter (tcnt)..................................................................................... 601 14.3.2 time constant regist er a (tcora)................................................................ 601 14.3.3 time constant regi ster b (t corb) ................................................................ 602 14.3.4 timer control regi ster (t cr).......................................................................... 602 14.3.5 timer counter control register (tccr) ......................................................... 604 14.3.6 timer control/status register (t csr)............................................................. 609 14.4 operation ...................................................................................................................... .... 613 14.4.1 pulse outp ut...................................................................................................... 613 14.4.2 reset inpu t ........................................................................................................ 614 14.5 operation timing.............................................................................................................. 6 15 14.5.1 tcnt count timing ........................................................................................ 615 14.5.2 timing of cmfa and cmfb se tting at compar e match................................. 616 14.5.3 timing of timer output at compare match ..................................................... 616 14.5.4 timing of counter clear by compare match ................................................... 617 14.5.5 timing of tcnt ex ternal reset....................................................................... 617 14.5.6 timing of overflow fl ag (ovf) setting .......................................................... 618 14.6 operation with cascad ed connection............................................................................... 618 14.6.1 16-bit counter mode ........................................................................................ 618 14.6.2 compare match co unt mode............................................................................ 619 14.7 interrupt sources.............................................................................................................. .619 14.7.1 interrupt sources and dtc activa tion ............................................................. 619 rev. 1.00 sep. 13, 2007 page xx of xxviii 14.7.2 a/d converter ac tivation ................................................................................. 620 14.8 usage notes .................................................................................................................... .. 621 14.8.1 notes on settin g cycle ..................................................................................... 621 14.8.2 conflict between tcnt writ e and counte r clear ........................................... 621 14.8.3 conflict between tcnt wr ite and increment.................................................. 622 14.8.4 conflict between tcor write and compare match........................................ 622 14.8.5 conflict between compare matches a and b................................................... 623 14.8.6 switching of internal clocks and tcnt op eration ......................................... 623 14.8.7 mode setting with casc aded connect ion ......................................................... 625 14.8.8 module stop st ate settin g ................................................................................ 625 14.8.9 interrupts in module stop state ........................................................................ 625 section 15 watchdog timer (wdt) ................................................................... 627 15.1 features....................................................................................................................... ...... 627 15.2 input/output pin ............................................................................................................... 628 15.3 register desc riptions........................................................................................................ 62 9 15.3.1 timer counter (tcnt)..................................................................................... 629 15.3.2 timer control/status re gister (tcsr)............................................................. 629 15.3.3 reset control/status re gister (rst csr)......................................................... 631 15.4 operation ...................................................................................................................... .... 632 15.4.1 watchdog time r mode..................................................................................... 632 15.4.2 interval timer mode......................................................................................... 634 15.5 interrupt source ............................................................................................................... .634 15.6 usage notes .................................................................................................................... .. 635 15.6.1 notes on regist er access ................................................................................. 635 15.6.2 conflict between timer counter (t cnt) write and increment....................... 636 15.6.3 changing values of bi ts cks2 to cks0.......................................................... 636 15.6.4 switching between watchdog timer m ode and interval timer mode............. 636 15.6.5 internal reset in watc hdog timer mode.......................................................... 637 15.6.6 system reset by wdtovf signal................................................................... 637 15.6.7 transition to watchdog timer mode or software st andby mode.................... 637 section 16 serial communications interface (sci, irda, crc)........................ 639 16.1 features....................................................................................................................... ...... 639 16.2 input/output pins.............................................................................................................. 644 16.3 register desc riptions........................................................................................................ 64 5 16.3.1 receive shift regi ster (rsr) ........................................................................... 647 16.3.2 receive data regi ster (rdr)........................................................................... 647 16.3.3 transmit data regi ster (tdr).......................................................................... 648 16.3.4 transmit shift regi ster (tsr) .......................................................................... 648 rev. 1.00 sep. 13, 2007 page xxi of xxviii 16.3.5 serial mode regi ster (smr) ............................................................................ 648 16.3.6 serial control re gister (s cr)........................................................................... 652 16.3.7 serial status regi ster (ssr) ............................................................................. 658 16.3.8 smart card mode re gister (s cmr)................................................................. 667 16.3.9 bit rate regist er (brr) ................................................................................... 668 16.3.10 serial extended mode re gister (semr_2) ...................................................... 676 16.3.11 serial extended mode register 5 and 6 (semr_5 and semr_6) ................... 678 16.3.12 irda control regi ster (ircr) ........................................................................... 685 16.4 operation in asynch ronous mode .................................................................................... 686 16.4.1 data transfer format........................................................................................ 687 16.4.2 receive data sampling timing and reception margin in asynchronous mode ..................................................................................... 688 16.4.3 clock................................................................................................................. 689 16.4.4 sci initialization (async hronous mo de) .......................................................... 690 16.4.5 serial data transmission (asynchronous mode) ............................................. 691 16.4.6 serial data reception (a synchronous mode)................................................... 693 16.5 multiprocessor co mmunication f unction......................................................................... 697 16.5.1 multiprocessor serial da ta transmission ......................................................... 699 16.5.2 multiprocessor serial data recep tion .............................................................. 700 16.6 operation in clock sy nchronous mode............................................................................ 703 16.6.1 clock................................................................................................................. 703 16.6.2 sci initialization (clock synchronous mode).................................................. 704 16.6.3 serial data transmission (c lock synchronous mode) ..................................... 705 16.6.4 serial data reception (clock synchronous mode) .......................................... 707 16.6.5 simultaneous serial data tr ansmission and reception (clock synchronous mode) .............................................................................. 708 16.7 operation in smart ca rd interface mode.......................................................................... 710 16.7.1 sample connection ........................................................................................... 710 16.7.2 data format (except in bl ock transfer mode) ................................................ 711 16.7.3 block transfer mode ........................................................................................ 712 16.7.4 receive data sampling timing and receptio n margin .................................... 713 16.7.5 initializatio n ...................................................................................................... 714 16.7.6 data transmission (except in block transfer mode) ...................................... 715 16.7.7 serial data reception (except in block transfer mode).................................. 718 16.7.8 clock output control........................................................................................ 719 16.8 irda oper ation ................................................................................................................. 721 16.9 interrupt sources.............................................................................................................. .724 16.9.1 interrupts in normal serial co mmunication interface mode ........................... 724 16.9.2 interrupts in smart ca rd interface mode .......................................................... 725 rev. 1.00 sep. 13, 2007 page xxii of xxviii 16.10 usage notes .................................................................................................................... .. 727 16.10.1 module stop st ate settin g ................................................................................ 727 16.10.2 break detection an d processing ....................................................................... 727 16.10.3 mark state and break detection ....................................................................... 727 16.10.4 receive error flags and transmit operations (clock synchronous mode only) ..................................................................... 727 16.10.5 relation between writing to tdr and tdre flag .......................................... 728 16.10.6 restrictions on usin g dtc or dmac.............................................................. 728 16.10.7 sci operations during power-down state ....................................................... 729 16.11 crc operation ci rcuit ..................................................................................................... 732 16.11.1 features............................................................................................................. 732 16.11.2 register desc riptions........................................................................................ 733 16.11.3 crc operation circu it operatio n .................................................................... 735 16.11.4 note on crc opera tion circui t........................................................................ 738 section 17 i 2 c bus interface 2 (iic2).................................................................. 739 17.1 features....................................................................................................................... ...... 739 17.2 input/output pins.............................................................................................................. 741 17.3 register desc riptions........................................................................................................ 74 2 17.3.1 i 2 c bus control regist er a (iccra ) ............................................................... 744 17.3.2 i 2 c bus control regi ster b (i ccrb) ............................................................... 745 17.3.3 i 2 c bus mode regist er (icmr)........................................................................ 747 17.3.4 i 2 c bus interrupt enable register (i cier)....................................................... 748 17.3.5 i 2 c bus status regi ster (icsr)......................................................................... 751 17.3.6 slave address regi ster (sar).......................................................................... 754 17.3.7 i 2 c bus transmit data re gister (icdrt) ........................................................ 755 17.3.8 i 2 c bus receive data re gister (icd rr).......................................................... 755 17.3.9 i 2 c bus shift regist er (icdrs)........................................................................ 755 17.4 operation ...................................................................................................................... .... 756 17.4.1 i 2 c bus format.................................................................................................. 756 17.4.2 master transmit operation............................................................................... 757 17.4.3 master receive operatio n ................................................................................ 759 17.4.4 slave transmit op eration ................................................................................. 761 17.4.5 slave receive op eration................................................................................... 764 17.4.6 noise canceller................................................................................................. 765 17.4.7 example of use................................................................................................. 766 17.5 interrupt request .............................................................................................................. 770 17.6 bit synchronous circuit.................................................................................................... 770 17.7 usage notes .................................................................................................................... .. 771 rev. 1.00 sep. 13, 2007 page xxiii of xxviii section 18 a/d converter....................................................................................773 18.1 features....................................................................................................................... ...... 773 18.2 input/output pins.............................................................................................................. 777 18.3 register desc riptions........................................................................................................ 77 9 18.3.1 a/d data registers a to h (addra to addrh) .......................................... 781 18.3.2 a/d control/status register for unit 0 (adc sr_0)........................................ 782 18.3.3 a/d control/status register for unit 1 (adc sr_1)........................................ 784 18.3.4 a/d control/status register for unit 2 (adc sr_2)........................................ 786 18.3.5 a/d control register (adcr_0) un it 0 .......................................................... 788 18.3.6 a/d control register (adcr_1) un it 1 .......................................................... 790 18.3.7 a/d control register (adcr_2) un it 2 .......................................................... 792 18.4 operation ...................................................................................................................... .... 794 18.4.1 single mode...................................................................................................... 794 18.4.2 scan mode ........................................................................................................ 795 18.4.3 input sampling and a/d conversion time ...................................................... 798 18.4.4 external trigger input timi ng.......................................................................... 800 18.5 interrupt source ............................................................................................................... .801 18.6 a/d conversion accura cy definitions ............................................................................. 803 18.7 usage notes .................................................................................................................... .. 805 18.7.1 module stop func tion settin g .......................................................................... 805 18.7.2 a/d input hold function in software stan dby mode ...................................... 805 18.7.3 permissible signal s ource impedance .............................................................. 805 18.7.4 influences on abso lute accuracy ..................................................................... 806 18.7.5 setting range of analog powe r supply and other pins ................................... 806 18.7.6 notes on boar d design ..................................................................................... 807 18.7.7 notes on noise co untermeasures ..................................................................... 807 section 19 d/a converter....................................................................................809 19.1 features....................................................................................................................... ...... 809 19.2 input/output pins.............................................................................................................. 810 19.3 register desc riptions........................................................................................................ 81 0 19.3.1 d/a data registers 0 and 1 (dadr0 and dadr1)......................................... 810 19.3.2 d/a control register 01 (da cr01) ................................................................ 811 19.4 operation ...................................................................................................................... .... 813 19.5 usage notes .................................................................................................................... .. 814 19.5.1 module stop st ate settin g ................................................................................ 814 19.5.2 d/a output hold function in software stan dby mode.................................... 814 section 20 ram ..................................................................................................815 rev. 1.00 sep. 13, 2007 page xxiv of xxviii section 21 flash memory.................................................................................... 817 21.1 features....................................................................................................................... ...... 817 21.2 mode transition diagram................................................................................................. 820 21.3 memory mat conf iguration ........................................................................................... 822 21.4 block structure ................................................................................................................ .823 21.4.1 block diagram of h8sx/1 642k....................................................................... 823 21.4.2 block diagram of h8sx/1644.......................................................................... 824 21.4.3 block diagram of h8sx/1648.......................................................................... 825 21.5 programming/erasing interface ........................................................................................ 826 21.6 input/output pins.............................................................................................................. 828 21.7 register desc riptions........................................................................................................ 82 8 21.7.1 programming/erasing inte rface registers ........................................................ 829 21.7.2 programming/erasing inte rface parameters ..................................................... 836 21.7.3 ram emulation regist er (ramer)................................................................ 848 21.8 on-board progra mming m ode ......................................................................................... 849 21.8.1 boot mode ........................................................................................................ 849 21.8.2 user program mode.......................................................................................... 853 21.8.3 user boot mode................................................................................................ 863 21.8.4 on-chip program and storable area for program data ................................... 867 21.9 protection..................................................................................................................... ..... 873 21.9.1 hardware protection ......................................................................................... 873 21.9.2 software prot ection........................................................................................... 874 21.9.3 error protection ................................................................................................ 874 21.10 flash memory emula tion using ram............................................................................. 876 21.11 switching between user mat and user boot mat........................................................ 879 21.12 programmer mode ............................................................................................................ 880 21.13 standard serial communications inte rface specifications fo r boot mode ...................... 880 21.14 usage notes .................................................................................................................... .. 909 section 22 boundary scan................................................................................... 911 22.1 features....................................................................................................................... ...... 911 22.2 block diagram of bounda ry scan function ..................................................................... 912 22.3 input/output pins.............................................................................................................. 912 22.4 register desc riptions........................................................................................................ 91 3 22.4.1 instruction regist er (jtir) ............................................................................... 914 22.4.2 bypass register (jtbpr) ................................................................................. 915 22.4.3 boundary scan regist er (jtbsr) .................................................................... 916 22.4.4 idcode register (jtid) ................................................................................. 925 22.5 operations..................................................................................................................... .... 926 22.5.1 tap contro ller ................................................................................................. 926 rev. 1.00 sep. 13, 2007 page xxv of xxviii 22.5.2 commands ........................................................................................................ 927 22.6 usage notes .................................................................................................................... .. 928 22.7 supplementary in formation .............................................................................................. 929 22.7.1 notes on serial transfer ................................................................................... 929 section 23 clock pulse generator .......................................................................931 23.1 register desc ription ......................................................................................................... 93 3 23.1.1 system clock control register (s ckcr) ........................................................ 933 23.2 oscillator..................................................................................................................... ...... 936 23.2.1 connecting crystal resonato r .......................................................................... 936 23.2.2 external cloc k input ......................................................................................... 937 23.3 pll circuit .................................................................................................................... ... 938 23.4 frequency divider ............................................................................................................ 93 8 23.5 usage notes .................................................................................................................... .. 938 23.5.1 notes on clock pulse generator ....................................................................... 938 23.5.2 notes on resonator ........................................................................................... 939 23.5.3 notes on boar d design ..................................................................................... 939 section 24 power-down modes ..........................................................................941 24.1 features....................................................................................................................... ...... 941 24.2 register desc riptions........................................................................................................ 94 4 24.2.1 standby control regi ster (sbycr) ................................................................. 944 24.2.2 module stop control registers a and b (mstpcra and mstpcrb) .......... 947 24.2.3 module stop control re gister c (m stpcrc)................................................. 950 24.2.4 deep standby control re gister (dps bycr)................................................... 951 24.2.5 deep standby wait contro l register (dpswcr)............................................ 954 24.2.6 deep standby interrupt enab le register (dpsier) ......................................... 956 24.2.7 deep standby interrupt flag register (dpsifr).............................................. 958 24.2.8 deep standby interrupt edge register (dpsiegr) ......................................... 960 24.2.9 reset status regist er (rstsr)......................................................................... 961 24.2.10 deep standby backup re gister (dpsbkrn) ................................................... 962 24.3 multi-clock f unction ....................................................................................................... 963 24.4 module stop state............................................................................................................. 9 63 24.5 sleep mode ..................................................................................................................... .. 964 24.5.1 entry to sleep mode ......................................................................................... 964 24.5.2 exit from sleep mode....................................................................................... 964 24.6 all-module-clock- stop mode.......................................................................................... 965 24.7 software sta ndby mode.................................................................................................... 966 24.7.1 entry to software standby mode...................................................................... 966 24.7.2 exit from software standby m ode ................................................................... 966 rev. 1.00 sep. 13, 2007 page xxvi of xxviii 24.7.3 setting oscillation settling time after ex it from software standby mode...... 967 24.7.4 software standby mode a pplication example................................................. 969 24.8 deep software st andby mode .......................................................................................... 970 24.8.1 entry to deep softwa re standby mode ............................................................ 970 24.8.2 exit from deep softwa re standby mode.......................................................... 971 24.8.3 pin state on exit from deep software sta ndby mode...................................... 972 24.8.4 b operation after exit from deep software standby mode ........................... 973 24.8.5 setting oscillation settling time after exit from deep software standby mode ................................................................................................... 974 24.8.6 deep software standby mode application example ....................................... 976 24.8.7 flowchart of deep software standby mode op eration .................................... 980 24.9 hardware stan dby mode .................................................................................................. 982 24.9.1 transition to hardware standby mode............................................................. 982 24.9.2 clearing hardware standby m ode.................................................................... 982 24.9.3 hardware standby mode timing...................................................................... 982 24.9.4 timing sequence at power-on ......................................................................... 983 24.10 sleep instruction ex ception hand ling .............................................................................. 984 24.11 | clock output control.................................................................................................. 987 24.12 usage notes .................................................................................................................... .. 988 24.12.1 i/o port st atus................................................................................................... 988 24.12.2 current consumption during oscilla tion settling sta ndby peri od ................... 988 24.12.3 module stop state of dmac or dtc .............................................................. 988 24.12.4 on-chip peripheral mo dule interr upts ............................................................. 988 24.12.5 writing to mstpcra, mstp crb, and ms tpcrc....................................... 988 24.12.6 control of input buffers by dirqne (n = 3 to 0)............................................. 989 24.12.7 input buffer control by di rqne (n = 3 to 0) .................................................. 989 24.12.8 b output st ate ................................................................................................ 989 section 25 list of registers................................................................................. 991 25.1 register addresses (a ddress order)................................................................................. 992 25.2 register bits .................................................................................................................. . 1008 25.3 register states in ea ch operating mode ........................................................................ 1030 section 26 electrical characteristics ................................................................. 1047 26.1 absolute maximu m ratings ........................................................................................... 1047 26.2 dc character istics .......................................................................................................... 104 8 26.3 ac character istics .......................................................................................................... 105 1 26.3.1 clock timing .................................................................................................. 1051 26.3.2 control signal timing .................................................................................... 1054 26.3.3 bus timi ng ..................................................................................................... 1055 rev. 1.00 sep. 13, 2007 page xxvii of xxviii 26.3.4 dmac timi ng................................................................................................ 1070 26.3.5 timing of on-chip peri pheral modu les ......................................................... 1073 26.4 a/d conversion char acteristic s ..................................................................................... 1081 26.5 d/a conversion char acteristic s ..................................................................................... 1081 26.6 flash memory char acteristic s ........................................................................................ 1082 appendix............................................................................................................1085 a. port states in e ach pin st ate........................................................................................... 1085 b. product li neup................................................................................................................ 1 091 c. package dime nsions ....................................................................................................... 1092 d. treatment of un used pins............................................................................................... 1093 index ..................................................................................................................1095 rev. 1.00 sep. 13, 2007 page xxviii of xxviii section 1 overview rev. 1.00 sep. 13, 2007 page 1 of 1102 rej09b0365-0100 section 1 overview 1.1 features the core of each product in the h8sx/1648 group of cisc (complex instruction set computer) microcontrollers is an h8sx cpu, which has an internal 32-bit arch itecture. the h8sx cpu provides upward-compatibility with the cpus of other renesas technology-original microcontrollers; h8/300, h8/300h, and h8s. as peripheral functions, each lsi of the group includes a dma controller, which enables high- speed data transfer, and a bus-state controller, which enables direct connection to different kinds of memory. the lsi of the group also include s serial communications interfaces, a/d and d/a converters, and a multi-function timer that make s motor control easy. together, the modules realize low-cost configur ations for end systems. the power consumption of these modules is kept down dynamically by an on-chip power-management function. the on-chip rom is a flash memory (f-ztat tm *) with a capacity of 1024 kbytes (h8sx/1648), 512 kbytes (h8sx/1644), or 256 kbytes (h8sx/1642). note: * f-ztat tm is a trademark of renesas technology corp. 1.1.1 applications examples of the applicati ons of this lsi include pc peripheral equipment, optical storage devices, office automation equipment, and industrial equipment. section 1 overview rev. 1.00 sep. 13, 2007 page 2 of 1102 rej09b0365-0100 1.1.2 overview of functions table 1.1 lists the functions of h8sx/1648 group products in outline. table 1.1 overview of functions classification module/ function description rom ? rom capacity: 1024 kbytes, 512 kbytes, or 256 kbytes memory ram ? ram capacity: 56 kbytes, 40 kbytes, or 24 kbytes cpu ? 32-bit high-speed h8sx cpu (cisc type) upwardly compatible for h8/300, h8/300h, and h8s cpus at object level ? general-register architecture (six teen 16-bit general registers) ? eleven addressing modes ? 4-gbyte address space program: 4 gbytes available data: 4 gbytes available ? 87 basic instructions, classifiable as bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, multiply-and-accumulate instructions, and others ? minimum instruction execution time: 20.0 ns (for an add instruction while system clock i = 50 mhz and v cc = 3.0 to 3.6 v) ? on-chip multiplier (16 16 32 bits) ? supports multiply-and-accumulate instructions (16 16 + 32 32 bits) cpu operating mode ? advanced mode normal, middle, or maximum mode is not supported. section 1 overview rev. 1.00 sep. 13, 2007 page 3 of 1102 rej09b0365-0100 classification module/ function description cpu mcu operating mode mode 1: user boot mode (selected by driving the md2 and md1 pins low and driving the md0 pin high) mode 2: boot mode (selected by driving the md2 and md0 pins low and driving the md1 pin high) mode 3: boundary scan enabled single-chip mode (selected by driving the md2 pin low and driving the md1 and md0 pins high) mode 4: on-chip rom disabled external extended mode, 16-bit bus (selected by driving the md1 and md0 pins low and driving the md2 pin high) mode 5: on-chip rom disabled external extended mode, 8-bit bus (selected by driving the md1 pin low and driving the md2 and md0 pins high) mode 6: on-chip rom enabled external extended mode (selected by driving the md0 pin low and driving the md2 and md1 pins high) mode 7: single-chip mode (can be externally extended) (selected by driving the md2, md1, and md0 pins high) ? low power consumption state (t ransition driven by the sleep instruction) interrupt controller (intc) ? seventeen external interrupt pins (nmi, and irq15 to irq0 ) ? 112 internal interrupt sources ? two interrupt control modes (specified by the interrupt control register) ? eight priority orders specifiable (by setting the interrupt priority register) ? independent vector addresses interrupt (source) break interrupt (ubc) ? break point can be set for four channels ? address break can be set for cpu instruction fetch cycles section 1 overview rev. 1.00 sep. 13, 2007 page 4 of 1102 rej09b0365-0100 classification module/ function description dma controller (dmac) ? four-channel dma transfer available ? three activation methods (auto-request, on-chip module interrupt, external request) ? three transfer modes (normal transfer, repeat transfer, block transfer) ? dual or single address mode selectable ? extended repeat-area function dma data transfer controller (dtc) ? allows dma transfer over 76 channels (number of dtc activation sources) ? activated by interrupt sources (chain transfer enabled) ? three transfer modes (normal transfer, repeat transfer, block transfer) ? short-address mode or full-address mode selectable ? 16-mbyte external address space ? the external address space can be divided into eight areas, each of which is independently controllable ? chip-select signals ( cs0 to ca7 ) can be output ? access in two or three states can be selected for each area ? program wait cycles can be inserted ? the period of cs assertion can be extended ? idle cycles can be inserted ? bus arbitration function (arbitrates bus mastership among the internal cpu and dtc, and external bus masters) bus formats ? external memory interfaces (for the connection of rom, burst rom, sram, and byte control sram) ? address/data bus format: support for both separate and multiplexed buses (8-bit access or 16-bit access) external bus extension bus controller (bsc) ? endian conversion function for connecting devices in little- endian format section 1 overview rev. 1.00 sep. 13, 2007 page 5 of 1102 rej09b0365-0100 classification module/ function description clock clock pulse generator (cpg) ? one clock generation circuit available ? separate clock signals are provided for each of functional modules (detailed below) and eac h is independently specifiable (multi-clock function) ? system-intended data transfer modules, i.e. the cpu, runs in synchronization with the system clock (i ): 8 to 50 mhz ? internal peripheral functions run in synchronization with the peripheral module clock (p ): 8 to 35 mhz ? modules in the external space are supplied with the external bus clock (b ): 8 to 50 mhz ? includes a pll frequency multiplication circuit and frequency divider, so the operating frequency is selectable ? five low-power-consumption modes: sleep mode, all-module- clock-stop mode, software standby mode, deep software standby mode, and hardware standby mode a/d converter a/d converter (adc) ? 10-bit resolution three units ? selectable input channel and unit configuration four channels three units (units 0, 1, and 2) eight channels one unit (unit 0) + four channels one unit (unit 2) ? sample and hold function included ? conversion time: 2.7 s per channel (with peripheral module clock (p ) at 25-mhz operation) ? two operating modes: single mode and scan mode ? three ways to start a/d conversion: unit 0: software, timer (tpu/tmr (units 0 and 1)) trigger, and external trigger unit 1: software, tmr (units 2 and 3) trigger, and external trigger unit 2: software, tmr (units 2 and 3) trigger, and external trigger ? activation of dtc and dmac by adi interrupt: unit 0: dtc and dmac can be activated by an adi0 interrupt. unit 1: dmac can be activated by an adi1 interrupt. unit 2: dmac can be activated by an adi2 interrupt. section 1 overview rev. 1.00 sep. 13, 2007 page 6 of 1102 rej09b0365-0100 classification module/ function description d/a converter d/a converter (dac) ? 8-bit resolution two output channels ? output voltage: 0 v to vref, maximum conversion time: 10 s (with 20-pf load) 8-bit timer (tmr) ? 8 bits eight channels (can be used as 16 bits four channels) ? select from among seven clock sources (six internal clocks and one external clock) ? allows the output of pulse tr ains with a desired duty cycle or pwm signals 16-bit timer pulse unit (tpu) ? 16 bits 12 * channels (general pulse timer unit) ? select from among eight counter-input clocks for each channel ? up to 16 pulse inputs and outputs ? counter clear operation, simultaneous writing to multiple timer counters (tcnt), simultaneous clearing by compare match and input capture possible, simultaneous input/output for registers possible by counter synchronous operation, and up to 15-phase pwm output possible by combination with synchronous operation ? buffered operation, cascaded operation (32 bits two channels), and phase counting mode (two-phase encoder input) settable for each channel ? input capture function supported ? output compare function (by the output of compare match waveform) supported note: * the pin function of unit 1 cannot be used in external bus extended mode. timer program- mable pulse generator (ppg) ? 32-bit * 1 * 2 pulse output ? four output groups, non-overlapp ing mode, and inverted output can be set ? selectable output trigger sign als; the ppg can operate in conjunction with the data transfer controller (dtc) and the dma controller (dmac) notes: 1. pulse output pins po 31 to po16 cannot be activated by input capture. 2. pulse of unit 1 cannot be output in external bus extended mode. watchdog timer watchdog timer (wdt) ? 8 bits one channels (selectable from eight counter input clocks) ? switchable between watchdog timer mode and interval timer mode section 1 overview rev. 1.00 sep. 13, 2007 page 7 of 1102 rej09b0365-0100 classification module/ function description serial interface ? seven channels (select asynchro nous or clock synchronous serial communications mode) ? full-duplex communications capability ? select the desired bit rate and lsb-first or msb-first transfer ? transfer rate clock input from tmr (sci_5, sci_6) ? irda transmission and recepti on conformant with the irda specifications version 1.0 ? on-chip cyclic redundancy check (crc) calculator for improved reliability in data transfer smart card/sim serial communi- cations interface (sci) ? the sci module supports a smart card (sim) interface. i 2 c bus interface i 2 c bus interface 2 (iic2) ? four channels ? bus can be directly driven (the scl and sda pins are nmos open drains). ? iic2 (unit 1) is open drain pins supporting 5 v input. i/o ports ? 13 cmos input-only pins ? 97 cmos input/output pins ? eight large-current drive pins (port 3) ? 40 pull-up resistors ? 16 open drains ? four open-drain i/o pins supporting 5 v input package ? lqfp-144 package operating frequency/ power supply voltage ? operating frequency: 8 to 50 mhz ? power supply voltage: vcc = pllvcc = 3.0 to 3.6 v, avcc = 3.0 to 3.6 v ? flash programming/erasure voltage: 3.0 to 3.6 v ? supply current: ? 50 ma (typ.) (vcc = pllvcc = 3.0 v, avcc = 3.0 v, i = b = 50 mhz, p = 25 mhz) operating peripheral temperature ( c) ? ? 20 to +75 c (regular specifications) ? ? 40 to +85 c (wide-range specifications) section 1 overview rev. 1.00 sep. 13, 2007 page 8 of 1102 rej09b0365-0100 1.2 list of products table 1.2 is the list of products, and figure 1.1 shows how to read the product name code. table 1.2 list of products part no. rom capacity ram capacity package remarks r5f61648n50fpv 1024 kbytes 56 kbytes lqfp-144 ? R5F61644N50FPV 512 kbytes 40 kbytes lqfp-144 ? r5f61642n50fpv 256 kbytes 24 kbytes lqfp-144 ? part no. indicates the pb-free version. indicates a renesas semiconductor product. indicates the package. fp: lqfp indicates the product-specific number. h8sx/1648 group indicates the type of rom device. f: on-chip flash memory product classification microcontroller r 5 f 61648n50 fp v figure 1.1 how to read the product name code ? small package package package code body size pin pitch lqfp-144 plqp0144ka-a (fp-144lv) * 20.0 20.0 mm 0.50 mm note: * pb-free version section 1 overview rev. 1.00 sep. 13, 2007 page 9 of 1102 rej09b0365-0100 1.3 block diagram internal system bus internal peripheral bus [legend] note: * in single-chip mode, the port d and port e functions can be used in the initial state. pin functions are selectable by setting the pcjke bit in pfcrd. ports d and e are enabled when pcjke = 0 (initial value) and ports j and k are enabled when pcjke = 1. in external extended mode, only ports d and e can be used. cpu: dtc: bsc: dmac: wdt: central processing unit data transfer controller bus controller dma controller watchdog timer 8-bit timer 16-bit timer pulse unit programmable pulse generator serial communications interface iic bus interface 2 tmr: tpu: ppg: sci: iic2: interrupt controller h8sx cpu ram rom dtc clock pulse generator bsc dmac 4 channels iic2 4 channels sci 7 channels tpu 6 channels (unit 0) tmr 2 channels (unit 1) tmr 2 channels (unit 0) tmr 2 channels (unit 3) tmr 2 channels (unit 2) wdt tpu 6 channels (unit 1) ppg 16 channels (unit 0) ppg 16 channels (unit 1) 10-bit ad 4 channels (unit 0) 10-bit ad 4 channels (unit 1) port f port 5 port h port 2 port 3 port 6 port a port i port 4 port b port n 8-bit da 2 channels port c 10-bit ad 4 channels (unit 2) port d/ port j * port e/ port k * port 1 external bus figure 1.2 block diagram section 1 overview rev. 1.00 sep. 13, 2007 page 10 of 1102 rej09b0365-0100 1.4 pin assignments 1.4.1 pin assignments notes: 1. in single-chip mode prots d and e can be used (initial state). pin functions are selectable by setting the pcjke bit in pfcrd. pin functions are selectable by setting the pcjke bit in pfcrd. ports d and e are enabled when pcjke = 0 (initial value) and ports j and k are enabled when pcjke = 1. in external extended mode, only ports d and e can be used. 2. this pin is an on-chip emulator enable pin. drive this pin low for the connection in normal operating mode. the on-chip emulator function is enabled by driving this pin high. when the on-chip emulator is in use, the p62, p63, p64, p65, and wdtovf pins are dedicated pins for the on-chip emulator. for details on a connection example with the e10a, see e10a emulator user's manual. lqfp-144 (top vew) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b pb2/ cs2 -a/ cs6 -a pb3/ cs3 -a/ cs7 -a vss pb7/ cs7 -d vcc md2 pn0/sda2 pn1/scl2 pc5 pf7/a23/sck5 pf6/a22/rxd5/irrxd pf5/a21/txd5/irtxd pf4/a20 pf3/a19 vss pf2/a18 pf1/a17 pf0/a16 pe7/a15 pe6/a14 pe5/a13 vss pe4/a12 vcc pe3/a11 pe2/a10 pe1/a9 pe0/a8 pd7/a7 pd6/a6 vss pd5/a5 pd4/a4 pd3/a3 pd2/a2 pk7/po31/tioca11/tiocb11 pk6/po30/tioca11 pk5/po29/tioca10/tiocb10 pj5/po21/tioca7/tiocb7/tclkg pj4/po20/tioca7 pj3/po19/tiocc6/tiocd6/tclkf pj2/po18/tiocc6/tclke pk3/po27/tiocc9/tiocd9 pk2/po26/tiocc9 pk1/po25/tioca9/tiocb9 pk0/po24/tioca9 pj7/po23/tioca8/tiocb8/tclkh pj6/po22/tioca8 pk4/po28/tioca10 p61/tmci2/rxd4/ tend2 / irq9 -b p60/tmri2/txd4/ dreq2 / irq8 -b p37/po15/tioca2/tiocb2/tclkd-a p36/po14/tioca2 p35/po13/tioca1/tiocb1/tclkc-a/ dack1 -b vss stby p17/tclkd-b/scl0/ adtrg1 -a/ irq7 -a p16/tclkc-b/sck3/sda0/ dack1 -a/ irq6 -a vcc extal xtal vss wdtovf /tdo p15/tclkb-b/rxd3/scl1/ tend1 -a/ irq5 -a p14/tclka-b/txd3/sda1/ dreq1 -a/ irq4 -a vcl res p67/ irq15 -b p66 vss p13/ adtrg0 -a/ irq3 -a p12/sck2/ dack0 -a/ irq2 -a p11/rxd2/ tend0 -a/ irq1 -a p10/txd2/ dreq0 -a/ irq0 -a pi7/d15 pi6/d14 pi5/d13 pi4/d12 vss pi3/d11 pi2/d10 pi1/d9 pi0/d8 vcc ph7/d7 ph6/d6 ph5/d5 ph4/d4 vss ph3/d3 ph2/d2 ph1/d1 ph0/d0 vcc p34/po12/tioca1/ tend1 -b p33/po11/tiocc0/tiocd0/tclkb-a/ dreq1 -b nmi p27/po7/tioca5/tiocb5/ irq15 -a p26/po6/tioca5/tmo1/txd1/ irq14 p32/po10/tiocc0/tclka-a/ dack0 -b p31/po9/tioca0/tiocb0/ tend0 -b p30/po8/tioca0/ dreq0 -b p25/po5/tioca4/tmci1/rxd1/ irq13 -a p24/po4/tioca4/tiocb4/tmri1/sck1/ irq12 -a p23/po3/tiocc3/tiocd3/ irq11 -a p22/po2/tiocc3/tmo0/txd0/ irq10 -a p21/po1/tioca3/tmci0/rxd0/ irq9 -a vcc p20/po0/tioca3/tiocb3/tmri0/sck0/ irq8 -a vss pc4/ adtrg2 pc1/ cs4 -c/ cs5 -c/ cs6 -c/ cs7 -c pc0/ cs3 -b/ wait -b/ adtrg1 -b pb6/ cs6 -d/(rd/ wr -b)/ adtrg0 -b pb5/ cs5 -d pb4/ cs4 -b pn3/scl3 pn2/sda3 emle pd0/a0 pd1/a1 pj0/po16/tioca6 pj1/po17/tioca6/tiocb6 p62/tmo2/sck4/ dack2 / irq10 -b/ trst pllvcc p63/tmri3/txd6/ dreq3 / irq11 -b/tms pllvss p64/tmci3/rxd6/ tend3 / irq12 -b/tdi p65/tmo3/sck6/ dack3 / irq13 -b/tck md0 pc2 pc3 p50/an0/ irq0 -b p51/an1/ irq1 -b p52/an2/ irq2 -b avcc p53/an3/ irq3 -b avss p54/an4/ irq4 -b vref p55/an5/ irq5 -b p56/an6/da0/ irq6 -b p57/an7/da1/ irq7 -b p44/an8 p45/an9 p46/an10 p47/an11 md1 pa0/ breqo / bs -a pa1/ back /(rd/ wr -a) pa2/ breq / wait -a pa3/ llwr / llb pa4/ lhwr / lub pa5/ rd pa6/ as / ah / bs -b vss pa7/b vcc pb0/ cs0 / cs4 -a/ cs5 -b 88 87 86 85 84 12345678910111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 * 1 * 1 * 2 figure 1.3 pin assignments section 1 overview rev. 1.00 sep. 13, 2007 page 11 of 1102 rej09b0365-0100 1.4.2 correspondence between pin configuration and operating modes table 1.3 pin configuration in each operating mode (h8sx/1648 group) pin name pin no. modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 1 pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b 2 pb2/ cs2 -a/ cs6 -a pb2/ cs2 -a/ cs6 -a pb2/ cs2 -a/ cs6 -a 3 pb3/ cs3 -a/ cs7 -a pb3/ cs3 -a/ cs7 -a pb3/ cs3 -a/ cs7 -a 4 vss vss vss 5 pb7/ cs7 -d pb7/ cs7 -d pb7/ cs7 -d 6 vcc vcc vcc 7 md2 md2 md2 8 pn0/sda2 pn0/sda2 pn0/sda2 9 pn1/scl2 pn1/scl2 pn1/scl2 10 pc5 pc5 pc5 11 pf7/a23/sck5 pf7/a23/sck5 pf7/a23/sck5 12 pf6/a22/rxd5/irrxd pf6/a22/rxd5/irrxd pf6/a22/rxd5/irrxd 13 pf5/a21/txd5/irtxd pf5/a21/txd5/irtxd pf5/a21/txd5/irtxd 14 pf4/a20 pf4/a20 a20 15 pf3/a19 pf3/a19 a19 16 vss vss vss 17 pf2/a18 pf2/a18 a18 18 pf1/a17 pf1/a17 a17 19 pf0/a16 pf0/a16 a16 20 pe7/a15 pe7/a15 pk7/po31/tioca11/ tiocb11 * 1 a15 21 pe6/a14 pe6/a14 pk6/po30/tioca11 * 1 a14 22 pe5/a13 pe5/a13 pk5/po29/tioca10/ tiocb10 * 1 a13 23 vss vss vss 24 pe4/a12 pe4/a12 pk4/po28/tioca10 * 1 a12 25 vcc vcc vcc section 1 overview rev. 1.00 sep. 13, 2007 page 12 of 1102 rej09b0365-0100 pin name pin no. modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 26 pe3/a11 pe3/a11 pk3/po27/tiocc9/ tiocd9 * 1 a11 27 pe2/a10 pe2/a10 pk2/po26/tiocc9 * 1 a10 28 pe1/a9 pe1/a9 pk1/po25/tioca9/ tiocb9 * 1 a9 29 pe0/a8 pe0/a8 pk0/po24/tioca9 * 1 a8 30 pd7/a7 pd7/a7 pj7/po23/tioca8/ tiocb8/tclkh * 1 a7 31 pd6/a6 pd6/a6 pj6/po22/tioca8 * 1 a6 32 vss vss vss 33 pd5/a5 pd5/a5 pj5/po21/tioca7/ tiocb7/tclkg * 1 a5 34 pd4/a4 pd4/a4 pj4/po20/tioca7 * 1 a4 35 pd3/a3 pd3/a3 pj3/po19/tiocc6/ tiocd6/tclkf * 1 a3 36 pd2/a2 pd2/a2 pj2/po18/tiocc6/ tclke * 1 a2 37 pd1/a1 pd1/a1 pj1/po17/tioca6/ tiocb6 * 1 a1 38 pd0/a0 pd0/a0 pj0/po16/tioca6 * 1 a0 39 emle emle emle 40 pn2/sda3 pn2/sda3 pn2/sda3 41 pn3/scl3 pn3/scl3 pn3/scl3 42 pb4/ cs4 -b pb4/ cs4 -b pb4/ cs4 -b 43 pb5/ cs5 -d pb5/ cs5 -d pb5/ cs5 -d 44 pb6/ cs6 -d/ (rd/ wr -b)/ adtrg0 -b pb6/ cs6 -d/(rd/ wr -b)/ adtrg0 -b pb6/ cs6 -d/ (rd/ wr -b)/ adtrg0 -b 45 pc0/ cs3 -b/ wait -b/ adtrg1 -b pc0/ cs3 -b/ wait -b/ adtrg1 -b pc0/ cs3 -b/ wait -b/ adtrg1 -b 46 pc1/ cs4 -c/ cs5 -c/ cs6 -c/ cs7 -c pc1/ cs4 -c/ cs5 -c/ cs6 -c/ cs7 -c pc1/ cs4 -c/ cs5 -c/ cs6 -c/ cs7 -c 47 pc4/ adtrg2 pc4/ adtrg2 pc4/ adtrg2 48 vss vss vss section 1 overview rev. 1.00 sep. 13, 2007 page 13 of 1102 rej09b0365-0100 pin name pin no. modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 49 p20/po0/tioca3/tiocb3/ tmri0/sck0/ irq8 -a p20/po0/tioca3/tiocb3/tmri0/ sck0/ irq8 -a p20/po0/tioca3/tiocb3/ tmri0/sck0/ irq8 -a 50 vcc vcc vcc 51 p21/po1/tioca3/tmci0/ rxd0/i rq9 -a p21/po1/tioca3/tmci0/rxd0/ irq9 -a p21/po1/tioca3/tmci0/ rxd0/ irq9 -a 52 p22/po2/tiocc3/tmo0/ txd0/ irq10 -a p22/po2/tiocc3/tmo0/txd0/ irq10 -a p22/po2/tiocc3/tmo0/ txd0/ irq10 -a 53 p23/po3/tiocc3/tiocd3/ irq11 -a p23/po3/tiocc3/tiocd3/ irq11 -a p23/po3/tiocc3/tiocd3/ irq11 -a 54 p24/po4/tioca4/tiocb4/ tmri1/sck1/ irq12 -a p24/po4/tioca4/tiocb4/tmri1/ sck1/ irq12 -a p24/po4/tioca4/tiocb4/ tmri1/sck1/ irq12 -a 55 p25/po5/tioca4/tmci1/ rxd1/ irq13 -a p25/po5/tioca4/tmci1/rxd1/ irq13 -a p25/po5/tioca4/tmci1/ rxd1/ irq13 -a 56 p30/po8/tioca0/ dreq0 -b p30/po8/tioca0/ dreq0 -b p30/po8/tioca0/ dreq0 -b 57 p31/po9/tioca0/tiocb0/ tend0 -b p31/po9/tioca0/tiocb0/ tend0 -b p31/po9/tioca0/tiocb0/ tend0 -b 58 p32/po10/tiocc0/ tclka-a/ dack0 -b p32/po10/tiocc0/ tclka-a/ dack0 -b p32/po10/tiocc0/ tclka-a/ dack0 -b 59 p26/po6/tioca5/tmo1/ txd1/ irq14 p26/po6/tioca5/tmo1/txd1/ irq14 p26/po6/tioca5/tmo1/ txd1/ irq14 60 p27/po7/tioca5/tiocb5/ irq15 -a p27/po7/tioca5/tiocb5/ irq15 -a p27/po7/tioca5/tiocb5/ irq15 -a 61 nmi nmi nmi 62 p33/po11/tiocc0/tiocd0/ tclkb-a/ dreq1 -b p33/po11/tiocc0/tiocd0/ tclkb-a/ dreq1 -b p33/po11/tiocc0/tiocd0/ tclkb-a/ dreq1 -b 63 p34/po12/tioca1/ tend1 -b p34/po12/tioca1/ tend1 -b p34/po12/tioca1/ tend1 -b 64 vcc vcc vcc 65 ph0/d0 ph0/d0 d0 66 ph1/d1 ph1/d1 d1 67 ph2/d2 ph2/d2 d2 68 ph3/d3 ph3/d3 d3 69 vss vss vss 70 ph4/d4 ph4/d4 d4 71 ph5/d5 ph5/d5 d5 section 1 overview rev. 1.00 sep. 13, 2007 page 14 of 1102 rej09b0365-0100 pin name pin no. modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 72 ph6/d6 ph6/d6 d6 73 ph7/d7 ph7/d7 d7 74 vcc vcc vcc 75 pi0/d8 pi0/d8 pi0/d8 76 pi1/d9 pi1/d9 pi1/d9 77 pi2/d10 pi2/d10 pi2/d10 78 pi3/d11 pi3/d11 pi3/d11 79 vss vss vss 80 pi4/d12 pi4/d12 pi4/d12 81 pi5/d13 pi5/d13 pi5/d13 82 pi6/d14 pi6/d14 pi6/d14 83 pi7/d15 pi7/d15 pi7/d15 84 p10/txd2/ dreq0 -a/ irq0 -a p10/txd2/ dreq0 -a/ irq0 -a p10/txd2/ dreq0 -a/ irq0 -a 85 p11/rxd2/ tend0 -a/ irq1 -a p11/rxd2/ tend0 -a/ irq1 -a p11/rxd2/ tend0 -a/ irq1 -a 86 p12/sck2/ dack0 -a/ irq2 -a p12/sck2/ dack0 -a/ irq2 -a p12/sck2/ dack0 -a/ irq2 -a 87 p13/ adtrg0 -a/ irq3 -a p13/ adtrg0 -a/ irq3 -a p13/ adtrg0 -a/ irq3 -a 88 vss vss vss 89 p66 p66 p66 90 p67/ irq15 -b p67/ irq15 -b p67/ irq15 -b 91 res res res 92 vcl vcl vcl 93 p14/tclka-b/txd3/sda1/ dreq1 -a/ irq4 -a p14/tclka-b/txd3/sda1/ dreq1 -a/ irq4 -a p14/tclka-b/txd3/sda1/ dreq1 -a/ irq4 -a 94 p15/tclkb-b/rxd3/scl1/ tend1 -a/ irq5 -a p15/tclkb-b/rxd3/scl1/ tend1 -a/ irq5 -a p15/tclkb-b/rxd3/scl1/ tend1 -a/ irq5 -a 95 wdtovf wdtovf /tdo * 2 wdtovf 96 vss vss vss 97 xtal xtal xtal 98 extal extal extal 99 vcc vcc vcc section 1 overview rev. 1.00 sep. 13, 2007 page 15 of 1102 rej09b0365-0100 pin name pin no. modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 100 p16/tclkc-b/sck3/sda0/ dack1 -a/ irq6 -a p16/tclkc-b/ sck3/sda0/ dack1 -a/ irq6 -a p16/tclkc-b/sck3/sda0/ dack1 -a/ irq6 -a 101 p17/tclkd-b/scl0/ adtrg1 -a/ irq7 -a p17/tclkd-b/scl0/ adtrg1 -a/ irq7 -a p17/tclkd-b/scl0/ adtrg1 -a/ irq7 -a 102 stby stby stby 103 vss vss vss 104 p35/po13/tioca1/tiocb1/ tclkc-a/ dack1 -b p35/po13/tioca1/tiocb1/ tclkc-a/ dack1 -b p35/po13/tioca1/tiocb1/ tclkc-a/ dack1 -b 105 p36/po14/tioca2 p36/po14/tioca2 p36/po14/tioca2 106 p37/po15/tioca2/tiocb2/ tclkd-a p37/po15/tioca2/tiocb2/ tclkd-a p37/po15/tioca2/tiocb2/ tclkd-a 107 p60/tmri2/txd4/ dreq2 / irq8 -b p60/tmri2/txd4/ dreq2 / irq8 -b p60/tmri2/txd4/ dreq2 / irq8 -b 108 p61/tmci2/rxd4/ tend2 / irq9 -b p61/tmci2/rxd4/ tend2 / irq9 -b p61/tmci2/rxd4/ tend2 / irq9 -b 109 p62/tmo2/sck4/ dack2 / irq10 -b p62/tmo2/sck4/ dack2 / irq10 -b/ trst * 2 p62/tmo2/sck4/ dack2 / irq10 -b 110 pllvcc pllvcc pllvcc 111 p63/tmri3/txd6/ dreq3 / irq11 -b p63/tmri3/txd6/ dreq3 / irq11 -b/tms * 2 p63/tmri3/txd6/ dreq3 / irq11 -b 112 pllvss pllvss pllvss 113 p64/tmci3/rxd6/ tend3 / irq12 -b p64/tmci3/rxd6/ tend3 / irq12 -b/tdi * 2 p64/tmci3/rxd6/ tend3 / irq12 -b 114 p65/tmo3/sck6/ dack3 / irq13 -b p65/tmo3/sck6/ dack3 / irq13 -b/tck * 2 p65/tmo3/sck6/ dack3 / irq13 -b 115 md0 md0 md0 116 pc2 pc2 pc2 117 pc3 pc3 pc3 118 p50/an0/ irq0 -b p50/an0/ irq0 -b p50/an0/ irq0 -b 119 p51/an1/ irq1 -b p51/an1/ irq1 -b p51/an1/ irq1 -b 120 p52/an2/ irq2 -b p52/an2/ irq2 -b p52/an2/ irq2 -b 121 avcc av cc avcc 122 p53/an3/ irq3 -b p53/an3/ irq3 -b p53/an3/ irq3 -b section 1 overview rev. 1.00 sep. 13, 2007 page 16 of 1102 rej09b0365-0100 pin name pin no. modes 1, 2, and 6 modes 3 and 7 modes 4 and 5 123 avss av ss avss 124 p54/an4/ irq4 -b p54/an4/ irq4 -b p54/an4/ irq4 -b 125 vref vref vref 126 p55/an5/ irq5 -b p55/an5/ irq5 -b p55/an5/ irq5 -b 127 p56/an6/da0/ irq6 -b p56/an6/da0/ irq6 -b p56/an6/da0/ irq6 -b 128 p57/an7/da1/ irq7 -b p57/an7/da1/ irq7 -b p57/an7/da1/ irq7 -b 129 p44/an8 p44/an8 p44/an8 130 p45/an9 p45/an9 p45/an9 131 p46/an10 p46/an10 p46/an10 132 p47/an11 p47/an11 p47/an11 133 md1 md1 md1 134 pa0/ breqo / bs -a pa0/ breqo / bs -a pa0/ breqo / bs -a 135 pa1/ back /(rd/ wr -a) pa1/ back /(rd/ wr -a) pa1/ back /(rd/ wr -a) 136 pa2/ breq / wait -a pa2/ breq / wait -a pa2/ breq / wait -a 137 pa3/ llwr / llb pa3/ llwr / llb llwr / llb 138 pa4/ lhwr / lub pa4/ lhwr / lub pa4/ lhwr / lub 139 pa5/ rd pa5/ rd rd 140 pa6/ as / ah / bs -b pa6/ as / ah / bs -b pa6/ as / ah / bs -b 141 vss vss vss 142 pa7/b pa7/b pa7/b 143 vcc vcc vcc 144 pb0/ cs0 / cs4 -a/ cs5 -b pb0/ cs0 / cs4 -a/ cs5 -b pb0/ cs0 / cs4 -a/ cs5 -b notes: 1. these pins can be used when the pcjke bit in pfcrd is set to 1 in single-chip mode. 2. pins tdo, trst, tms, tdi, and tck are enabled in mode 3. section 1 overview rev. 1.00 sep. 13, 2007 page 17 of 1102 rej09b0365-0100 1.4.3 pin functions table 1.4 pin functions classification pin name i/o description power supply v cc input power supply pins. connect them to the system power supply. v cl input connect this pin to v ss via a 0.1- f capacitor (the capacitor should be placed close to the pin). v ss input ground pins. connect them to the system power supply (0 v). pllv cc input power supply pin for the pll circuit. pllv ss input ground pin for the pll circuit. clock xtal input extal input pins for a crystal resonator. an external clock signal can be input through the extal pin. for an example of this connection, see section 23, clock pulse generator. b output outputs the system clock for external devices. operating mode control md2 to md0 input pins for setting the operat ing mode. the signal levels on these pins must not be changed during operation. system control res input reset signal input pin. this lsi enters the reset state when this signal goes low. stby input this lsi enters hardware standby mode when this signal goes low. emle input input pin for the on-chip emulator enable si gnal. if the on-chip emulator is used, the signal level should be fixed high. if the on-chip emulator is not used, the signal level should be fixed low. trst input tms input tdi input tck input on-chip emulator tdo output on-chip emulator pins or boundary scan pins. when the emle pin is driven high, these pins are dedicat ed for the on-chip emulator. when the emle pin is driven low and set to mode 3, these pins are dedicated for the boundary scan mode. address bus a23 to a0 output output pins for the address bits. data bus d15 to d0 input/ output input and output for the bidirectional data bus. these pins also output addresses when accessing an address?data multiplexed i/o interface space. bus control breq input external bus-master modules a ssert this signal to request the bus. breqo output internal bus-master modules as sert this signal to request access to the external space via the bus in the external bus released state. section 1 overview rev. 1.00 sep. 13, 2007 page 18 of 1102 rej09b0365-0100 classification pin name i/o description bus control back output bus acknowledge signal, wh ich indicates that the bus has been released. bs -a/ bs -b output indicates the start of a bus cycle. as output strobe signal which indicates that the output address on the address bus is valid in access to the basic bus interface or byte control sram interface space. ah output this signal is used to hold the address when accessing the address-data multiplexed i/o interface space. rd output strobe signal which indicate s that reading from the basic bus interface space is in progress. rd/ wr output indicates the direction (input or output) of the data bus. lhwr output strobe signal which indicate s that the higher-order byte (d15 to d8) is valid in access to the basic bus interface space. llwr output strobe signal which indicates that the lower-order byte (d7 to d0) is valid in access to the basic bus interface space. lub output strobe signal which indicate s that the higher-order byte (d15 to d8) is valid in access to the byte control sram interface space. llb output strobe signal which indicates that the lower-order byte (d7 to d0) is valid in access to the byte control sram interface space. cs0 cs1 cs2 -a/ cs2 -b cs3 -a/ cs3 -b cs4 -a/ cs4 -b/ cs4 -c cs5 -a/ cs5 -b/ cs5 -c/ cs5 -d cs6 -a/ cs6 -b/ cs6 -c/ cs6 -d cs7 -a/ cs7 -b/ cs7 -c/ cs7 -d output select signals for areas 0 to 7. wait -a/ wait -b input requests wait cycles in access to the external space. section 1 overview rev. 1.00 sep. 13, 2007 page 19 of 1102 rej09b0365-0100 classification pin name i/o description interrupt nmi input non-maskable interrupt request signal. when this pin is not in use, this signal must be fixed high. irq15 -a/ irq15 -b irq14 irq13 -a/ irq13 -b irq12 -a/ irq12 -b irq11 -a/ irq11 -b irq10 -a/ irq10 -b irq9 -a/ irq9 -b irq8 -a/ irq8 -b irq7 -a/ irq7 -b irq6 -a/ irq6 -b irq5 -a/ irq5 -b irq4 -a/ irq4 -b irq3 -a/ irq3 -b irq2 -a/ irq2 -b irq1 -a/ irq1 -b irq0 -a/ irq0 -b input maskable interrupt request signal. dreq0 -a/ dreq0 -b dreq1 -a/ dreq1 -b dreq2 dreq3 input requests dmac activation. dack0 -a/ dack0 -b dack1 -a/ dack1 -b dack2 dack3 output dmac single address- transfer acknowledge signal. dma controller (dmac) tend0 -a/ tend0 -b tend1 -a/ tend1 -b tend2 tend3 output indicates end of data transfer by the dmac. 16-bit timer pulse unit (tpu) tclka-a/tclka-b tclkb-a/tclkb-b tclkc-a/tclkc-b tclkd-a/tclkd-b input input pins for the external cl ock signals. tioca0 tiocb0 tiocc0 tiocd0 input/ output signals for tgra_0 to tgrd_0. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca1 tiocb1 input/ output signals for tgra_1 and tgrb_1. these pins are used as input capture inputs, output compare outputs, or pwm outputs. section 1 overview rev. 1.00 sep. 13, 2007 page 20 of 1102 rej09b0365-0100 classification pin name i/o description 16-bit timer pulse unit (tpu) tioca2 tiocb2 input/ output signals for tgra_2 and tgrb_2. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca3 tiocb3 tiocc3 tiocd3 input/ output signals for tgra_3 to tgrd_3. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca4 tiocb4 input/ output signals for tgra_4 and tgrb_4. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca5 tiocb5 input/ output signals for tgra_5 and tgrb_5. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tclke tclkf tclkg tclkh input input pins for ex ternal clock signals. tioca6 tiocb6 tiocc6 tiocd6 input/ output signals for tgra_6 to tgrd_6. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca7 tiocb7 input/ output signals for tgra_7 and tgrb_7. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca8 tiocb8 input/ output signals for tgra_8 and tgrb_8. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca9 tiocb9 tiocc9 tiocd9 input/ output signals for tgra_9 to tgrd_9. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca10 tiocb10 input/ output signals for tgra_10 and tgrb_10. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca11 tiocb11 input/ output signals for tgra_11 and tgrb_11. these pins are used as input capture inputs, output compare outputs, or pwm outputs. programmable pulse generator (ppg) po31 to po0 output output pins for the pulse signals. section 1 overview rev. 1.00 sep. 13, 2007 page 21 of 1102 rej09b0365-0100 classification pin name i/o description tmo0 to tmo3 output output pins for the compare match signals. tmci0 to tmci3 input input pins for the external cloc k signals that drive for the counters. 8-bit timer (tmr) tmri0 to tmri3 input input pins for the counter-reset signals. watchdog timer (wdt) wdtovf output output pin for the counter-overflow signal in watchdog-timer mode. serial communications interface (sci) txd0 txd1 txd2 txd3 txd4 txd5 txd6 output output pins for data transmission. rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 input input pins for data reception. sck0 sck1 sck2 sck3 sck4 sck5 sck6 input/ output input/output pins for clock signals. irtxd output output pin that outputs encoded data for irda. sci with irda (sci) irrxd input input pin that inputs encoded data for irda. scl0 scl1 scl2 scl3 input/ output input/output pin for iic clock. bus can be directly driven by the nmos open drain output. scl2 and scl3 support 5-v input. i 2 c bus interface 2 (iic2) sda0 sda1 sda2 sda3 input/ output input/output pin for iic data. bus can be directly driven by the nmos open drain output. sda2 and sda3 support 5-v input. section 1 overview rev. 1.00 sep. 13, 2007 page 22 of 1102 rej09b0365-0100 classification pin name i/o description an11 to an0 input input pins for the analog signals to be processed by the a/d converter. a/d converter adtrg0 -a/ adtrg0 -b adtrg1 -a/ adtrg1 -b adtrg2 input input pins for the external tri gger signal that starts a/d conversion. d/a converter da1, da0 output output pins for the analog signals from the d/a converter. a/d converter, d/a converter av cc input analog power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. av ss input ground pin for the a/d and d/a converters. connect this pin to the system power supply (0 v). vref input reference power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. i/o ports p17 to p10 input/ output 8-bit input/output pins. p27 to p20 input/ output 8-bit input/output pins. p37 to p30 input/ output 8-bit input/output pins. p47 to p44 input 4-bit input-only pins. p57 to p50 input 8-bit input-only pins. p67 to p60 input/ output 8-bit input/output pins. pa7 input input-only pin. pa6 to pa0 input/ output 7-bit input/output pins. pb7 to pb0 input/ output 8-bit input/output pins. pc5 to pc0 input/ output 6-bit input/output pins. pd7 to pd0 input/ output 8-bit input/output pins. pe7 to pe0 input/ output 8-bit input/output pins. section 1 overview rev. 1.00 sep. 13, 2007 page 23 of 1102 rej09b0365-0100 classification pin name i/o description pf7 to pf0 input/ output 8-bit input/output pins. ph7 to ph0 input/ output 8-bit input/output pins. pi7 to pi0 input/ output 8-bit input/output pins. pn3 to pn0 input/ output 4-bit input/output (open drain) pins. pj7 to pj0 * input/ output 8-bit input/output pins. pk7 to pk0 * input/ output 8-bit input/output pins. note: * these pins can be used when the pcjke bit in pfcrd is set to 1 in single-chip mode. section 1 overview rev. 1.00 sep. 13, 2007 page 24 of 1102 rej09b0365-0100 section 2 cpu rev. 1.00 sep. 13, 2007 page 25 of 1102 rej09b0365-0100 section 2 cpu the h8sx cpu is a high-speed cpu with an in ternal 32-bit architect ure that is upward compatible with the h8/300, h8/300h, and h8s cpus. the h8sx cpu has sixteen 16-bit general register s, can handle a 4-gbyte linear address space, and is ideal for a r ealtime control system. 2.1 features ? upward-compatible with h8/300, h8/300h, and h8s cpus ? can execute object programs of these cpus ? sixteen 16-bit general registers ? also usable as sixteen 8-bit registers or eight 32-bit registers ? 87 basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? bit field transfer instructions ? powerful bit-manipulation instructions ? bit condition branch instructions ? multiply-and-accumulate instruction ? eleven addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:2,ern), @(d:16,ern), or @(d:32,ern)] ? index register indirect with displacement [@(d:16,rnl.b), @(d:32,rnl.b), @(d:16,rn.w), @(d:32,rn.w), @(d: 16,ern.l), or @(d:32,ern.l)] ? register indirect with pre-/post- increment or pre-/post-decrement [@ + ern, @ ? ern, @ern + , or @ern ? ] ? absolute address [@aa:8, @a a:16, @aa:24, or @aa:32] ? immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? program-counter relative with index re gister [@(rnl.b,pc), @(rn.w,pc), or @(ern.l,pc)] ? memory indirect [@@aa:8] ? extended memory i ndirect [@@vec:7] section 2 cpu rev. 1.00 sep. 13, 2007 page 26 of 1102 rej09b0365-0100 ? two base registers ? vector base register ? short address base register ? 4-gbyte address space ? program: 4 gbytes ? data: 4 gbytes ? high-speed operation ? all frequently-used instructions executed in one or two states ? 8/16/32-bit register-regist er add/subtract: 1 state ? 8 8-bit register-register multiply: 1 state ? 16 8-bit register-register divide: 10 states ? 16 16-bit register-register multiply: 1 state ? 32 16-bit register-register divide: 18 states ? 32 32-bit register-register multiply: 5 states ? 32 32-bit register-register divide: 18 states ? four cpu operating modes ? normal mode ? middle mode ? advanced mode ? maximum mode ? power-down modes ? transition is made by exec ution of sleep instruction ? choice of cpu operating clocks notes: 1. advanced mode is only supported as the cpu operating mode of the h8sx/1648 group. normal, middle, and maximum modes are not supported. 2. the multiplier and divider are supported by the h8sx/1648 group. section 2 cpu rev. 1.00 sep. 13, 2007 page 27 of 1102 rej09b0365-0100 2.2 cpu operating modes the h8sx cpu has four operating modes: normal, middle, advanced and maximum modes. these modes can be selected by the mode pins of this lsi. cpu operating modes normal mode maximum mode maximum 64 kbytes for program and data areas combined maximum 4 gbytes for program and data areas combined maximum 16-mbyte program area and 64-kbyte data area, maximum 16 mbytes for program and data areas combined maximum 16-mbyte program area and 4-gbyte data area, maximum 4 gbytes for program and data areas combined advanced mode middle mode figure 2.1 cpu operating modes 2.2.1 normal mode the exception vector table and stack have th e same structure as in the h8/300 cpu. ? address space the maximum address space of 64 kbytes can be accessed. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when the extended register en is used as a 16-bit register it can contain any value, even when the corresponding general register rn is used as an address register. (if the general register rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post- decrement and a carry or borrow occurs, however, the value in the corresponding extended register en will be affected.) ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. section 2 cpu rev. 1.00 sep. 13, 2007 page 28 of 1102 rej09b0365-0100 ? exception vector table and memo ry indirect branch addresses in normal mode, the top area starting at h'0000 is allocated to the exce ption vector table. one branch address is stored per 16 bits. the struct ure of the exception vect or table is shown in figure 2.2. h'0000 h'0001 h'0002 h'0003 reset exception vector reset exception vector exception vector table figure 2.2 exception vector table (normal mode) the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute address included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.3. the pc contents are saved or restored in 16-bit units. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1, * 3 ccr ccr*3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored on return. (sp ) * 2 figure 2.3 stack structure (normal mode) section 2 cpu rev. 1.00 sep. 13, 2007 page 29 of 1102 rej09b0365-0100 2.2.2 middle mode the program area in middle mode is extended to 16 mbytes as compared with that in normal mode. ? address space the maximum address space of 16 mbytes can be accessed as a total of the program and data areas. for individual areas, up to 16 mbytes of the program area or up to 64 kbytes of the data area can be allocated. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when the extended register en is used as a 16-bit register (in other than the jmp and jsr instructions), it can contain any value even when the corresponding general register rn is used as an address register. (if the general register rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post- decrement and a carry or borrow occurs, howev er, the value in the corresponding extended register en will be affected.) ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid and the up per eight bits are sign-extended. ? exception vector table and memo ry indirect branch addresses in middle mode, the top area starting at h'000000 is allocated to the exception vector table. one branch address is stored per 32 bits. the upper eight bits are ignored and the lower 24 bits are stored. the structure of the exception vector table is shown in figure 2.4. the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute addr ess included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. in middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. the upper eight bits are reserved and assumed to be h'00. ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.5. the pc contents are saved or restored in 24-bit units. section 2 cpu rev. 1.00 sep. 13, 2007 page 30 of 1102 rej09b0365-0100 2.2.3 advanced mode the data area is extended to 4 gbytes as compared with that in middle mode. ? address space the maximum address space of 4 gbytes can be linearly accessed. for individual areas, up to 16 mbytes of the program area and up to 4 gbytes of the data area can be allocated. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. ? instruction set all instructions and addressing modes can be used. ? exception vector table and memo ry indirect branch addresses in advanced mode, the top area starting at h'00000000 is allocat ed to the excep tion vector table. one branch address is stored per 32 bits. the upper eight bits are ignored and the lower 24 bits are stored. the structure of the exception vector table is shown in figure 2.4. h'00000000 h'00000003 h'00000004 exception vector table reserved reset exception vector reserved h'00000007 h'00000001 h'00000002 h'00000005 h'00000006 figure 2.4 exception vector table (middle and advanced modes) the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute address included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. in advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. the upper eight bits are reserved and assumed to be h'00. section 2 cpu rev. 1.00 sep. 13, 2007 page 31 of 1102 rej09b0365-0100 ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.5. the pc contents are saved or restored in 24-bit units. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1 , * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored on return. (sp ) * 2 reserved figure 2.5 stack structure (middle and advanced modes) 2.2.4 maximum mode the program area is extended to 4 gbytes as compared with that in advanced mode. ? address space the maximum address space of 4 gbytes can be linearly accessed. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. ? instruction set all instructions and addressing modes can be used. ? exception vector table and memo ry indirect branch addresses in maximum mode, the top area st arting at h'00000000 is allocat ed to the exception vector table. one branch address is stor ed per 32 bits. the structure of the exception vector table is shown in figure 2.6. section 2 cpu rev. 1.00 sep. 13, 2007 page 32 of 1102 rej09b0365-0100 h'00000000 h'00000003 h'00000004 exception vector table reset exception vector h'00000007 h'00000001 h'00000002 h'00000005 h'00000006 figure 2.6 exception vector table (maximum modes) the memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the jmp and jsr instructions. an 8- bit absolute address included in the instruction code specifies a memory location. execution branches to the cont ents of the memory location. in maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. ? stack structure the stack structure of pc at a subroutine branch and that of pc and ccr at an exception handling are shown in figure 2.7. the pc contents are saved or restored in 32-bit units. the exr contents are saved or restored regardless of whether or not exr is in use. (a) subroutine branch (b) exception handling pc (32 bits) exr ccr pc (32 bits) sp sp figure 2.7 stack structure (maximum mode) section 2 cpu rev. 1.00 sep. 13, 2007 page 33 of 1102 rej09b0365-0100 2.3 instruction fetch the h8sx cpu has two modes for instruction fetch: 16-bit and 32-bit modes. it is recommended that the mode be set according to the bus width of the memory in which a program is stored. the instruction-fetch mode setting does not affect opera tion other than instruction fetch such as data accesses. whether an instruction is fetched in 16- or 32-bit mode is selected by the fetchmd bit in syscr. for details, see section 3.2.2, system control register (syscr). 2.4 address space figure 2.8 shows a memory map of the h8sx cpu. the address space differs depending on the cpu operating mode. h'0000 h'000000 h'007fff h'ff8000 h'ffffff h'00000000 h'00ffffff h'ffffffff h'00000000 h'ffffffff h'ffff normal mode program area data area (64 kbytes) program area data area (4 gbytes) program area (16 mbytes) program area (16 mbytes) data area (64 kbytes) data area (4 gbytes) middle mode advanced mode maximum mode figure 2.8 memory map section 2 cpu rev. 1.00 sep. 13, 2007 page 34 of 1102 rej09b0365-0100 2.5 registers the h8sx cpu has the internal registers shown in figure 2.9. there are two types of registers: general registers and control registers. the control registers are the 32-bit program counter (pc), 8-bit extended control register (exr), 8-bit co ndition-code register ( ccr), 32-bit vector base register (vbr), 32-bit short address base register (sbr), and 64-bit multiply-accumulate register (mac). t ???? i2 i1 i0 exr 76543210 31 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers and extended registers control registers [legend] stack pointer program counter condition-code register interrupt mask bit user bit or interrupt mask bit half-carry flag sp: pc: ccr: i: ui: h: user bit negative flag zero flag overflow flag carry flag extended control register u: n: z: v: c: exr: er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 7654321 0 sign extension 63 32 41 0 31 mac pc (reserved) 31 0 12 vbr (reserved) 31 0 8 sbr macl trace bit interrupt mask bits vector base register short address base register multiply-accumulate register t: i2 to i0: vbr: sbr: mac: mach figure 2.9 cpu registers section 2 cpu rev. 1.00 sep. 13, 2007 page 35 of 1102 rej09b0365-0100 2.5.1 general registers the h8sx cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figure 2.10 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). when the general registers are used as 16-bit registers, the er registers are divided into 16-bit general registers designated by the letters e (e 0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. when the general registers are used as 8-bit registers, the r registers are divided into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. the general registers er (er0 to er7), r (r0 to r7 ), and rl (r0l to r7l) are also used as index registers. the size in the operand field determines which register is selected. the usage of each register can be selected independently. address registers 32-bit registers 32-bit index registers 16-bit registers general registers e (e0 to e7) 8-bit registers general registers rh (r0h to r7h) 16-bit registers 16-bit index registers general registers r (r0 to r7) 8-bit registers 8-bit index registers general registers rl (r0l to r7l) general registers er (er0 to er7) ? ? ? ? ? ? ? ? ? figure 2.10 usage of general registers section 2 cpu rev. 1.00 sep. 13, 2007 page 36 of 1102 rej09b0365-0100 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. figure 2.11 shows the stack. free area stack area sp (er7) figure 2.11 stack 2.5.2 program counter (pc) pc is a 32-bit counter that indicat es the address of the next instru ction the cpu will execute. the length of all cpu instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (when the instruction code is fetched, the least significant bit is regarded as 0. section 2 cpu rev. 1.00 sep. 13, 2007 page 37 of 1102 rej09b0365-0100 2.5.3 condition-code register (ccr) ccr is an 8-bit register that contains internal cp u status information, including an interrupt mask (i) and user (ui, u) bits and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branch conditio ns for conditional branch (bcc) instructions. bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts when set to 1. th is bit is set to 1 at the start of an exception handling. 6 ui undefined r/w user bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written to and read from by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit (regarded as sign bit) of data. section 2 cpu rev. 1.00 sep. 13, 2007 page 38 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. a carry has the following types: ? carry from the result of addition borrow from the result of subtraction carry from the result of shift or rotation the carry flag is also used as a bit accumulator by bit manipulation instructions. 2.5.4 extended control register (exr) exr is an 8-bit register that contains the trace bit (t) and three interrupt mask bits (i2 to i0). operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. for details, see section 5, exception handling. bit bit name initial value r/w description 7 t 0 r/w trace bit when this bit is set to 1, a trace exception is generated each time an instruction is executed. when this bit is cleared to 0, instructions are executed in sequence. 6 to 3 ? all 1 r/w reserved these bits are always read as 1. 2 1 0 i2 i1 i0 1 1 1 r/w r/w r/w interrupt mask bits these bits designate the interrupt mask level (0 to 7). section 2 cpu rev. 1.00 sep. 13, 2007 page 39 of 1102 rej09b0365-0100 2.5.5 vector base register (vbr) vbr is a 32-bit register in which the upper 20 bits are valid. the lower 12 bi ts of this register are read as 0s. this register is a base address of the vector area for exceptio n handlings other than a reset and a cpu address error (extended memory indi rect is also out of th e target). the initial value is h'00000000. the vbr contents are changed with the ldc and stc instructions. 2.5.6 short address base register (sbr) sbr is a 32-bit register in which the upper 24 bits are valid. the lower eight bits are read as 0s. in 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. the initial value is h'ffffff00. the sbr contents are changed with the ldc and stc instructions. 2.5.7 multiply-accumulate register (mac) mac is a 64-bit register that stores the results of multiply-and-accumulate operations. it consists of two 32-bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are sign extended. the mac contents are changed with the mac, clrmac, ldmac, and stmac instructions. 2.5.8 initial values of cpu registers reset exception handling loads the start address from the vector table into the pc, clears the t bit in exr to 0, and sets the i bits in ccr and exr to 1. the general registers, mac, and the other bits in ccr are not initialized. in particular, the initial value of the stack pointer (er7) is undefined. the sp should therefore be initialized using an mov.l instruction executed immediately after a reset. section 2 cpu rev. 1.00 sep. 13, 2007 page 40 of 1102 rej09b0365-0100 2.6 data formats the h8sx cpu can process 1-bit, 4-bit bcd, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions oper ate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.6.1 general register data formats figure 2.12 shows the data formats in general registers. 7 6 5 4 3 2 1 0 don't care 7 0 don't care 7 6 5 4 3 2 1 0 43 70 70 don?t care upper lower lsb msb lsb 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data word data word data longword data rnh rnl rnh rnl rnh rnl rn en ern msb don't care upper lower 43 7 0 don't care 7 0 don't care 70 general register er general register e general register r general register rh [legend] ern: en: rn: rnh: 0 15 msb lsb 0 lsb 15 16 msb 31 en rn 0 msb lsb 15 rnl: msb: lsb: general register rl most significant bit least significant bit figure 2.12 general register data formats section 2 cpu rev. 1.00 sep. 13, 2007 page 41 of 1102 rej09b0365-0100 2.6.2 memory data formats figure 2.13 shows the data formats in memory. the h8sx cpu can access word data and longword data which are stored at any addresses in memory. when word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesse s. for example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. in this case, these accesses are assumed to be individual bus cycles. however, instructions to be fetc hed, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and mac instruction should be locat ed to even addresses. when sp (er7) is used as an address register to access the stack, the operand size should be word size or longword size. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.13 memory data formats section 2 cpu rev. 1.00 sep. 13, 2007 page 42 of 1102 rej09b0365-0100 2.7 instruction set the h8sx cpu has 87 types of instructions. the instructions are classified by function as shown in table 2.1. the arithmetic operation, logic oper ation, shift, and bit mani pulation instructions are called operation instruction in this manual. table 2.1 instruction classification function instructions size types data transfer mov b/w/l 6 movfpe * 6 , movtpe * 6 b pop, push * 1 w/l ldm, stm l mova b/w * 2 block transfer eepmov b 3 movmd b/w/l movsd b arithmetic operations add, addx, sub, subx, cmp, neg, inc, dec b/w/l 27 daa, das b adds, subs l mulxu, divxu, mulxs, divxs b/w mulu, divu, muls, divs w/l mulu/u, muls/u l extu, exts w/l tas b mac ? ldmac, stmac ? clrmac ? logic operations and, or, xor, not b/w/l 4 shift shll, shlr, shal, shar, ro tl, rotr, rotxl, rotxr b/w/l 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist b 20 bset/eq, bset/ne, bclr/eq, bclr/ne, bstz, bistz b bfld, bfst b section 2 cpu rev. 1.00 sep. 13, 2007 page 43 of 1102 rej09b0365-0100 function instructions size types branch bra/bs, bra/bc, bsr/bs, bsr/bc b * 3 9 bcc * 5 , jmp, bsr, jsr, rts ? rts/l l * 5 bra/s ? system control trapa, rte, sleep, nop ? 10 rte/l l * 5 ldc, stc, andc, orc, xorc b/w/l total 87 [legend] b: byte size w: word size l: longword size notes: 1. pop.w rn and push.w rn are identical to mov.w @sp + , rn and mov.w rn, @ ? sp. pop.l ern and push.l ern are identical to mov.l @sp + , ern and mov.l ern, @ ? sp. 2. size of data to be added with a displacement 3. size of data to specify a branch condition 4. bcc is the generic designation of a conditional branch instruction. 5. size of general register to be restored 6. only when the multiplier is available. section 2 cpu rev. 1.00 sep. 13, 2007 page 44 of 1102 rej09b0365-0100 2.7.1 instructions and addressing modes table 2.2 indicates the combinations of instructions and addressing modes that the h8sx cpu can use. table 2.2 combinations of instru ctions and addressing modes (1) addressing mode classifi- cation instruction size #xx rn @ern @(d,ern) @(d, rnl.b/ rn.w/ ern.l) @ ? ern/ @ern + / @ern ? / @ + ern @aa:8 @aa:16/ @aa:32 ? data transfer mov b/w/l s sd sd sd sd sd sd b s/d s/d movfpe, movtpe * 12 b s/d s/d * 1 pop, push w/l s/d s/d * 2 ldm, stm l s/d s/d * 2 mova * 4 b/w s s s s s s eepmov b sd * 3 block transfer movmd b/w/l sd * 3 movsd b sd * 3 add, cmp b s d d d d d d d b s d d d d d d b d s s s s s s b sd sd sd sd sd w/l s sd sd sd sd sd sd arithmetic operations sub b s d d d d d d b s d d d d d d b d s s s s s s b sd sd sd sd sd w/l s sd sd sd sd sd sd addx, subx b/w/l s sd b/w/l s sd b/w/l s sd * 5 inc, dec b/w/l d adds, subs l d daa, das b d mulxu, divxu b/w s:4 sd mulu, divu w/l s:4 sd section 2 cpu rev. 1.00 sep. 13, 2007 page 45 of 1102 rej09b0365-0100 addressing mode classifi- cation instruction size #xx rn @ern @(d,ern) @(d, rnl.b/ rn.w/ ern.l) @ ? ern/ @ern + / @ern ? / @ + ern @aa:8 @aa:16/ @aa:32 ? arithmetic operations mulxs, divxs b/w s:4 sd muls, divs w/l s:4 sd neg b d d d d d d d w/l d d d d d d extu, exts w/l d d d d d d tas b d mac ? clrmac ? o ldmac ? s stmac ? d and, or, xor b s d d d d d d b d s s s s s s b sd sd sd sd sd w/l s sd sd sd sd sd sd logic operations not b d d d d d d d w/l d d d d d d shift shll, shlr b d d d d d d d b/w/l * 6 d d d d d d b/w/l * 7 d b d d d d d d d shal, shar rotl, rotr rotxl, rotxr w/l d d d d d d bit manipu- lation bset, bclr, bnot, btst, bset/cc, bclr/cc b d d d d band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist, bstz, bistz b d d d d section 2 cpu rev. 1.00 sep. 13, 2007 page 46 of 1102 rej09b0365-0100 addressing mode classifi- cation instruction size #xx rn @ern @(d,ern) @(d, rnl.b/ rn.w/ ern.l) @ ? ern/ @ern + / @ern ? / @ + ern @aa:8 @aa:16/ @aa:32 ? bfld b d s s s bit manipu- lation bfst b s d d d branch bra/bs, bra/bc * 8 b s s s bsr/bs, bsr/bc * 8 b s s s ldc (ccr, exr) b/w * 9 s s s s s * 10 s ldc (vbr, sbr) l s stc (ccr, exr) b/w * 9 d d d d * 11 d system control stc (vbr, sbr) l d andc, orc, xorc b s sleep ? o nop ? o [legend] d: d:16 or d:32 s: can be specified as a source operand. d: can be specified as a destination operand. sd: can be specified as either a s ource or destination operand or both. s/d: can be specified as either a source or destination operand. s:4: 4-bit immediate data can be specified as a source operand. notes: 1. only @aa:16 is available. 2. @ern + as a source operand and @ ? ern as a destination operand 3. specified by er5 as a source addre ss and er6 as a destination address for data transfer. 4. size of data to be added with a displacement 5. only @ern ? is available 6. when the number of bits to be shifted is 1, 2, 4, 8, or 16 7. when the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. size of data to specify a branch condition 9. byte when immediate or r egister direct, otherwise, word 10. only @ern + is available 11. only @ ? ern is available 12. not available in this lsi. section 2 cpu rev. 1.00 sep. 13, 2007 page 47 of 1102 rej09b0365-0100 table 2.2 combinations of instru ctions and addressing modes (2) addressing mode classifi- cation instruction size @ern @(d,pc) @(rnl. b/rn.w/ ern.l, pc) @aa:24 @ aa:32 @@ aa:8 @@vec: 7 ? branch bra/bs, bra/bc ? o bsr/bs, bsr/bc ? o bcc ? o bra ? o o bra/s ? o * jmp ? o o o o o bsr ? o jsr ? o o o o o rts, rts/l ? o trapa ? o system control rte, rte/l ? o [legend] d: d:8 or d:16 note: * only @(d:8, pc) is available. section 2 cpu rev. 1.00 sep. 13, 2007 page 48 of 1102 rej09b0365-0100 2.7.2 table of instructions classified by function tables 2.4 to 2.11 summarize th e instructions in each functional category. the notation used in these tables is defined in table 2.3. table 2.3 operation notation operation notation description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register vbr vector base register sbr short address base register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical exclusive or move logical not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). section 2 cpu rev. 1.00 sep. 13, 2007 page 49 of 1102 rej09b0365-0100 table 2.4 data transfer instructions instruction size function mov b/w/l #imm (ead), (eas) (ead) transfers data between immediate data , general registers, and memory. movfpe * b (eas) rd movtpe * b rs (eas) pop w/l @sp + rn restores the data from the stack to a general register. push w/l rn @ ? sp saves general register contents on the stack. ldm l @sp + rn (register list) restores the data from the stack to mu ltiple general registers. two, three, or four general registers which have serial register numbers can be specified. stm l rn (register list) @ ? sp saves the contents of multiple general registers on the stack. two, three, or four general registers which have serial register numbers can be specified. mova b/w ea rd zero-extends and shifts the contents of a specified general register or memory data and adds them with a disp lacement. the result is stored in a general register. note: * not available in this lsi. section 2 cpu rev. 1.00 sep. 13, 2007 page 50 of 1102 rej09b0365-0100 table 2.5 block transfer instructions instruction size function eepmov.b eepmov.w b transfers a data block. transfers byte data which begins at a memory location specified by er5 to a memory location specified by er6. the number of byte data to be transferred is specified by r4 or r4l. movmd.b b transfers a data block. transfers byte data which begins at a memory location specified by er5 to a memory location specified by er6. the number of byte data to be transferred is specified by r4. movmd.w w transfers a data block. transfers word data which begins at a memory location specified by er5 to a memory location specified by er6. the number of word data to be transferred is specified by r4. movmd.l l transfers a data block. transfers longword data which begins at a memory location specified by er5 to a memory location specified by er6. the number of longword data to be transferred is specified by r4. movsd.b b transfers a data block with zero data detection. transfers byte data which begins at a memory location specified by er5 to a memory location specified by er6. the number of byte data to be transferred is specified by r4. when ze ro data is detected during transfer, the transfer stops and execution bran ches to a specified address. section 2 cpu rev. 1.00 sep. 13, 2007 page 51 of 1102 rej09b0365-0100 table 2.6 arithmetic operation instructions instruction size function add sub b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs addition or subtracti on on data between immediate data, general registers, and memory. immediate byte data cannot be subtracted from byte data in a general register. addx subx b/w/l (ead) #imm c (ead), (ead) (eas) c (ead) performs addition or subtraction wit h carry on data between immediate data, general registers, and me mory. the addressing mode which specifies a memory location can be sp ecified as register indirect with post-decrement or register indirect. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a general register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 2-digit 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits, or 16 bits 16 bits 32 bits. mulu w/l rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits, or 16 bits 16 bits 32 bits. mulu/u l rd rs rd performs unsigned multiplication on data in two general registers (32 bits 32 bits upper 32 bits). mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits, or 16 bits 16 bits 32 bits. muls w/l rd rs rd performs signed multiplication on data in two general registers: either 16 bits 16 bits 16 bits, or 32 bits 32 bits 32 bits. muls/u l rd rs rd performs signed multiplication on data in two general registers (32 bits 32 bits upper 32 bits). divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder, or 32 bits 16 bits 16-bit quotient and 16-bit remainder. section 2 cpu rev. 1.00 sep. 13, 2007 page 52 of 1102 rej09b0365-0100 instruction size function divu w/l rd rs rd performs unsigned division on data in two general registers: either 16 bits 16 bits 16-bit quotient, or 32 bits 32 bits 32-bit quotient. divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder, or 32 bits 16 bits 16-bit quotient and 16-bit remainder. divs w/l rd rs rd performs signed division on data in two general registers: either 16 bits 16 bits 16-bit quotient, or 32 bits 32 bits 32-bit quotient. cmp b/w/l (ead) ? #imm, (ead) ? (eas) compares data between immediate data, general registers, and memory and stores the result in ccr. neg b/w/l 0 ? (ead) (ead) takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. extu w/l (ead) (zero extension) (ead) performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. the lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. exts w/l (ead) (sign extension) (ead) performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. the lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. tas b @erd ? 0, 1 ( section 2 cpu rev. 1.00 sep. 13, 2007 page 53 of 1102 rej09b0365-0100 table 2.7 logic operation instructions instruction size function and b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs a logical and operati on on data between immediate data, general registers, and memory. or b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs a logical or operation on data between immediate data, general registers, and memory. xor b/w/l (ead) #imm (ead), (ead) (eas) (ead) performs a logical exclusive or operation on data between immediate data, general registers, and memory. not b/w/l (ead) (ead) takes the one's complement of the c ontents of a general register or a memory location. table 2.8 shift operation instructions instruction size function shll shlr b/w/l (ead) (shift) (ead) performs a logical shift on the contents of a general register or a memory location. the contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. the contents of a general register can be shifted by any bits. in this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. shal shar b/w/l (ead) (shift) (ead) performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. rotl rotr b/w/l (ead) (rotate) (ead) rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l (ead) (rotate) (ead) rotates the contents of a general regi ster or a memory location with the carry bit. 1-bit or 2-bit rotation is possible. section 2 cpu rev. 1.00 sep. 13, 2007 page 54 of 1102 rej09b0365-0100 table 2.9 bit manipulation instructions instruction size function bset b 1 ( section 2 cpu rev. 1.00 sep. 13, 2007 page 55 of 1102 rej09b0365-0100 instruction size function bior b c [~ ( section 2 cpu rev. 1.00 sep. 13, 2007 page 56 of 1102 rej09b0365-0100 instruction size function bistz b z ( section 2 cpu rev. 1.00 sep. 13, 2007 page 57 of 1102 rej09b0365-0100 table 2.11 system control instructions instruction size function trapa ? starts trap-instruct ion excepti on handling. rte ? returns from an exception-handling routine. rte/l ? returns from an exception-handli ng routine, restoring data from the stack to multiple general registers. sleep ? causes a transition to a power-down state. b/w #imm ccr, (eas) ccr, #imm exr, (eas) exr loads immediate data or the contents of a general register or a memory location to ccr or exr. although ccr and exr are 8-bit regi sters, word-size transfers are performed between them and memory. the upper 8 bits are valid. ldc l rs vbr, rs sbr transfers the general register contents to vbr or sbr. b/w ccr (ead), exr (ead) transfers the contents of ccr or exr to a general register or memory. although ccr and exr are 8-bit regi sters, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc l vbr rd, sbr rd transfers the contents of vbr or sbr to a general register. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter. section 2 cpu rev. 1.00 sep. 13, 2007 page 58 of 1102 rej09b0365-0100 2.7.3 basic instruction formats the h8sx cpu instructions consist of 2-byte (1 -word) units. an instruction consists of an operation field (op field), a register field (r field) , an effective address extension (ea field), and a condition field (cc). figure 2.14 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2.14 instruction formats ? operation field indicates the function of the inst ruction, and specifies the addre ssing mode and operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers are sp ecified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data , an absolute address, or a displacement. ? condition field specifies the branch condition of bcc instructions. section 2 cpu rev. 1.00 sep. 13, 2007 page 59 of 1102 rej09b0365-0100 2.8 addressing modes and effective address calculation the h8sx cpu supports the 11 addressing modes listed in table 2.12. each instruction uses a subset of these addressing modes. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.12 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:2,ern)/@(d:16,ern)/@(d:32,ern) 4 index register indirect with displacement @(d:16, rnl.b)/@(d: 16,rn.w)/@(d:16,ern.l) @(d:32, rnl.b)/@(d: 32,rn.w)/@(d:32,ern.l) 5 register indirect with post-increment @ern + register indirect with pre-decrement @ ? ern register indirect with pre-increment @ + ern register indirect with post-decrement @ern ? 6 absolute address @aa:8/@aa:16/@aa:24/@aa:32 7 immediate #xx:3/#xx: 4/#xx:8/#xx:16/#xx:32 8 program-counter relati ve @(d:8,pc)/@(d:16,pc) 9 program-counter relative with index regi ster @(rnl.b,pc)/@(rn.w,pc)/@(ern.l,pc) 10 memory indirect @@aa:8 11 extended memory indirect @@vec:7 2.8.1 register direct?rn the operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in th e instruction code. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. section 2 cpu rev. 1.00 sep. 13, 2007 page 60 of 1102 rej09b0365-0100 2.8.2 register indirect?@ern the operand value is the co ntents of the memory location which is pointed to by the contents of an address register (ern). ern is specified by the register field of the instruction code. in advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). 2.8.3 register indirect with displa cement ?@(d:2, ern), @(d:16, ern), or @(d:32, ern) the operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ern) and a 16- or 32-bit displacement. er n is specified by the register field of the in struction code. the displacement is incl uded in the instruction code and the 16-bit displacement is sign-extended when added to ern. this addressing mode has a short format (@(d:2, ern)). the short format can be used when the displacement is 1, 2, or 3 and the operand is byte da ta, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. 2.8.4 index register indirect with disp lacement?@(d:16,rnl.b), @(d:32,rnl.b), @(d:16,rn.w), @(d:32,rn.w), @(d:16,ern.l), or @(d:32,ern.l) the operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (rnl, rn, ern) specified by the register field in the instruction code are zero- extended to 32-bit data an d multiplied by 1, 2, or 4. the displacement is in cluded in the instruction code and the 16-bit displacement is sign-extended wh en added to ern. if the operand is byte data, ern is multiplied by 1. if the operand is word or longword data, ern is multiplied by 2 or 4, respectively. section 2 cpu rev. 1.00 sep. 13, 2007 page 61 of 1102 rej09b0365-0100 2.8.5 register indirect with post-in crement, pre-decrement, pre-increment, or post-decrement?@ern + , @ ? ern, @ + ern, or @ern ? ? register indirect with post-increment?@ern + the operand value is the contents of a memory location which is pointed to by the contents of an address register (ern). ern is specified by the register field of th e instruction code. after the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address regi ster. the value added is 1 for by te access, 2 for word access, or 4 for longword access. ? register indirect with pre-decrement?@ ? ern the operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ern). ern is specified by the register field of the instructio n code. after that, the operand value is stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. ? register indirect with pre-increment?@ + ern the operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ern). ern is specified by the register fiel d of the instruction code. after that, the operand value is stored in the address register. the value added is 1 for byte access, 2 for wo rd access, or 4 for longword access. ? register indirect with post-decrement?@ern ? the operand value is the contents of a memory location which is pointed to by the contents of an address register (ern). ern is specified by the register field of th e instruction code. after the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register . the value subtracted is 1 for byte access, 2 for word access, or 4 fo r longword access. using this addressing mode, data to be written is the contents of the general register after calculating an effective address. if the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the seco nd calculation of an effective address. example 1: mov.w r0, @er0 + when er0 before execution is h'12345678, h'567a is written at h'12345678. section 2 cpu rev. 1.00 sep. 13, 2007 page 62 of 1102 rej09b0365-0100 example 2: mov.b @er0 + , @er0 + when er0 before execution is h'00001000, h'000010 00 is read and the contents is written at h'00001001. after execution, er0 is h'00001002. 2.8.6 absolute address?@aa:8, @aa:16, @aa:24, or @aa:32 the operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. there are 8-bit (@aa:8), 16-bit (@aa:16), 24-b it (@aa:24), and 32-bit (@aa:32) absolute addresses. to access the data area, the absolu te address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. for an 8-bit absolute address, the upper 24 bits are specified by sbr. for a 16- bit absolute address, the upper 16 bits are sign -extended. a 32-bit absolu te address can access the entire address space. to access the program area, the abso lute address of 24 bits (@aa:24 ) or 32 bits (@aa:32) is used. for a 24-bit absolute addres s, the upper 8 bits are a ll assumed to be 0 (h'00). table 2.13 shows the accessibl e absolute address ranges. table 2.13 absolute address access ranges absolute address normal mode middle mode advanced mode maximum mode data area 8 bits (@aa:8) a consecutive 256-byte area (the upper address is set in sbr) 16 bits (@aa:16) h'0000 to h'ffff h'00000000 to h'00007fff, h'ffff8000 to h'ffffffff 32 bits (@aa:32) h'000000 to h'007fff, h'ff8000 to h'ffffff h'00000000 to h'ffffffff program area 24 bits (@aa:24) h'000000 to h'ffffff h'00000000 to h'00ffffff 32 bits (@aa:32) h'00000000 to h'00ffffff h'00000000 to h'ffffffff section 2 cpu rev. 1.00 sep. 13, 2007 page 63 of 1102 rej09b0365-0100 2.8.7 immediate?#xx the operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. this addressing mode has short formats in which 3- or 4-bit immediate data can be used. when the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. the bfld and bfst instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. the tr apa instruction contains 2-bit immediate data in the instruction code, for specifying a vector address. 2.8.8 program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instructions. the operand value is a 32-bit branch address, which is the sum of an 8- or 16 -bit displacement in the instruction code and th e 32-bit address of the pc contents. the 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the pc contents. the pc contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ? 126 to + 128 bytes ( ? 63 to + 64 words) or ? 32766 to + 32768 bytes ( ? 16383 to + 16384 words) from the branch instruction. the resulting value should be an even number. in advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). 2.8.9 program-counter relative with index register?@(rnl.b, pc), @(rn.w, pc), or @(ern.l, pc) this mode is used in the bcc an d bsr instructions. the operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the pc contents: the contents of an address register specified by the register field in the instruction code (rnl, rn, or ern) is zero-extended and multiplie d by 2. the pc contents to wh ich the displacement is added is the address of the first byte of the next instruction. in advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). section 2 cpu rev. 1.00 sep. 13, 2007 page 64 of 1102 rej09b0365-0100 2.8.10 memory indirect?@@aa:8 this mode can be used by the jmp and jsr instru ctions. the operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. the upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in other modes). in normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. in other modes, the memory location is pointed to by longword-size data. in middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (h'00). note that the top part of the address range is al so used as the exception handling vector area. a vector address of an exception handling other than a reset or a cpu address error can be changed by vbr. figure 2.15 shows an example of specification of a branch address using this addressing mode. (a) normal mode (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address figure 2.15 branch address speci fication in memory indirect mode section 2 cpu rev. 1.00 sep. 13, 2007 page 65 of 1102 rej09b0365-0100 2.8.11 extended memo ry indirect?@@vec:7 this mode can be used by the jmp and jsr instru ctions. the operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of h'80 is multiplied by 2 or 4. the address range to store a branch address is h'0100 to h'01ff in normal mode and h'000200 to h'0003ff in other modes. in assembler notation, an address to store a branch address is specified. in normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. in other modes, the memory location is pointed to by longword-size data. in middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (h'00). 2.8.12 effective ad dress calculation tables 2.14 and 2.15 show how effective addresses are calculate d in each addressing mode. the lower bits of the effective addre ss are valid and the upper bits are ignored (zero extended or sign extended) according to the cpu operating mode. the valid bits in middle mode are as follows: ? the lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. ? the lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions. section 2 cpu rev. 1.00 sep. 13, 2007 page 66 of 1102 rej09b0365-0100 table 2.14 effective address calculation for transfer and operation instructions 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 15 31 15 0 31 0 31 0 0 31 15 0 31 0 1, 2, or 4 31 31 0 0 31 0 31 1, 2, or 4 1, 2, or 4 31 0 7 no. op op rm rn imm 1 2 3 4 5 6 7 op r op disp disp disp disp aa aa aa disp r op disp r op aa op disp r op disp r op aa op r op r op aa 31 0 0 1, 2, or 4 addressing mode and instruction format effective address calculation effective address (ea) immediate register direct register indirect register indirect with 16-bit displacement register indirect with 32-bit displacement index register indirect with 16-bit displacement index register indirect with 32-bit displacement register indirect with post-increment or post-decrement register indirect with pre-increment or pre-decrement 8-bit absolute address 16-bit absolute address 32-bit absolute address sign extension sbr general register contents general register contents zero extension contents of general register (rl, r, or er) zero extension contents of general register (rl, r, or er) sign extension general register contents general register contents general register contents sign extension + + + + section 2 cpu rev. 1.00 sep. 13, 2007 page 67 of 1102 rej09b0365-0100 table 2.15 effective address calc ulation for branch instructions 31 0 31 0 31 0 31 0 31 31 23 0 0 31 31 0 0 31 0 2 or 4 7 1 7 vec op disp 1 2 3 4 5 6 op disp op r op aa op r op aa aa aa op aa aa 31 0 31 0 op vec 31 0 31 0 31 0 31 0 31 7 0 disp 31 0 31 0 31 15 0 disp 31 0 31 31 0 2 0 no. register indirect program-counter relative with 8-bit displacement 24-bit absolute address 32-bit absolute address zero extension contents of general register (rl, r, or er) general register contents sign extension addressing mode and instruction format effective address calculation effective address (ea) pc contents sign extension pc contents zero extension zero extension memory contents memory contents zero extension pc contents program-counter relative with 16-bit displacement program-counter relative with index register memory indirect extended memory indirect + + + 2.8.13 mova instruction the mova instruction stores the eff ective address in a general register. 1. firstly, data is obtained by the addressing mode shown in item 2 of table 2.14. 2. next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. the obtained data is used instead of the general register. the result is stored in a general register. for details, see h8sx family software manual. section 2 cpu rev. 1.00 sep. 13, 2007 page 68 of 1102 rej09b0365-0100 2.9 processing states the h8sx cpu has five main processing states: th e reset state, exception-ha ndling state, program execution state, bus-released stat e, and program stop state. fi gure 2.16 indicates the state transitions. ? reset state in this state the cpu and internal peripheral mo dules are all initialized and stopped. when the res input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset state. reset exception handlin g starts when the res signal changes from low to high. for details, see section 5, exception handling. the reset state can also be entered by a watchdog timer overflow when available. ? exception-handling state the exception-handling state is a transient state that occurs wh en the cpu alters the normal processing flow due to activati on of an exception sour ce, such as, a reset, trace, interrupt, or trap instruction. the cpu fetches a start addre ss (vector) from the exception handling vector table and branches to that address. for further details, see section 5, exception handling. ? program execution state in this state the cpu executes pr ogram instructions in sequence. ? bus-released state the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. ? program stop state this is a power-down state in which the cpu stops operating. the program stop state occurs when a sleep instruction is executed or the cpu enters hardware standby mode. for details, see section 24, power-down modes. note: * a transition to the reset state occurs whenever the res signal goes low. a transition can also be made to the reset state when the watchdog timer overflows. reset state * exception-handling state request for exception handling end of exception handling program execution state bus-released state bus request end of bus request program stop state sleep instruction interrupt request bus request end of bus request res = high res = low figure 2.16 state transitions section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 69 of 1102 rej09b0365-0100 section 3 mcu operating modes 3.1 operating mode selection this lsi has seven operating modes (modes 1, 2, 3, 4, 5, 6, and 7). the operating mode is selected by the setting of mode pins md2 to md0. table 3.1 lists mcu operating mode settings. table 3.1 mcu operating mode settings external data bus width mcu operating mode md2 md1 md0 cpu operating mode address space lsi initiation mode on-chip rom default max. 1 0 0 1 advanced mode 16 mbytes user boot mode enabled ? 16 bits 2 0 1 0 boot mode enabled ? 16 bits 3 0 1 1 boundary scan enabled single-chip mode enabled ? 16 bits 4 1 0 0 disabled 16 bits 16 bits 5 1 0 1 on-chip rom disabled extended mode disabled 8 bits 16 bits 6 1 1 0 on-chip rom enabled extended mode enabled 8 bits 16 bits 7 1 1 1 single-chip mode enabled ? 16 bits in this lsi, an advanced mode as the cpu op erating mode and a 16-mbyte address space are available. the initial external bus widths are eight or 16 bits. as the lsi initiation mode, the external extended mode, on-chip rom initiation mode, or single-chip initiation mode can be selected. modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory can be programmed and erased. for details on the user boot mode and boot mode, see section 21, flash memory. section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 70 of 1102 rej09b0365-0100 mode 3 is the boundary scan function enabled single-chip mode. for details on the boundary scan function, see section 22, boundary scan. mode 7 is a single-chip initiation mode. all i/o po rts can be used as general input/output ports. the external address space cannot be accessed in th e initial state, but setti ng the expe bit in the system control register (syscr) to 1 enables to use the external address space. after the external address space is enabled, ports d, e, and f can be used as an address output bus and ports h and i as a data bus by specifying the data direction register (ddr) for each por t. when the external address space is not in use, ports j and k can be used by setting the pcjke bit in the port function control register d (pfcrd) to 1. modes 4 to 6 are external extended modes, in which the external memory and devices can be accessed. in the external extended modes, the exte rnal address space can be designated as 8-bit or 16-bit address space for each ar ea by the bus controller after starting program execution. if 16-bit address space is designated for any one area , it is called the 16-bit bus widths mode. if 8- bit address space is designated for all areas, it is called the 8-bit bus width mode. 3.2 register descriptions the following registers are related to the operating mode setting. ? mode control register (mdcr) ? system control register (syscr) 3.2.1 mode control register (mdcr) mdcr indicates the current opera ting mode. when mdcr is read from, the states of signals md2 to md0 are latched. latching is released by a reset. section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 71 of 1102 rej09b0365-0100 bit bit name initial value r/w note: * determined by pins md2 to md0. 15 ? 0 r 14 ? 1 r 13 ? 0 r 12 ? 1 r 11 mds3 undefined * r 10 mds2 undefined * r 9 mds1 undefined * r 8 mds0 undefined * r bit bit name initial value r/w 7 ? 0 r 6 ? 1 r 5 ? 0 r 4 ? 1 r 3 ? undefined * r 2 ? undefined * r 1 ? undefined * r 0 ? undefined * r bit bit name initial value r/w descriptions 15 14 13 12 ? ? ? ? 0 1 0 1 r r r r reserved these are read-only bits and cannot be modified. 11 10 9 8 mds3 mds2 mds1 mds0 undefined * undefined * undefined * undefined * r r r r mode select 3 to 0 these bits indicate the operating mode selected by the mode pins (md2 to md0) (see table 3.2). when mdcr is read, the signal levels input on pins md2 to md0 are latched into these bits. these latches are released by a reset. 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? 0 1 0 1 undefined * undefined * undefined * undefined * r r r r r r r r reserved these are read-only bits and cannot be modified. note: * determined by pins md2 to md0. section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 72 of 1102 rej09b0365-0100 table 3.2 settings of bits mds3 to mds0 mode pins mdcr mcu operating mode md2 md1 md0 mds3 mds2 mds1 mds0 1 0 0 1 1 1 0 1 2 0 1 0 1 1 0 0 3 0 1 1 0 1 0 0 4 1 0 0 0 0 1 0 5 1 0 1 0 0 0 1 6 1 1 0 0 1 0 1 7 1 1 1 0 1 0 0 section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 73 of 1102 rej09b0365-0100 3.2.2 system control register (syscr) syscr controls mac saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-ch ip ram, and selects the dtc address mode. bit bit name initial value r/w note: * the initial value depends on the startup mode. 15 ? 1 r/w 14 ? 1 r/w 13 macs 0 r/w 12 ? 1 r/w 11 fetchmd 0 r/w 10 ? undefined * r 9 expe undefined * r/w 8 rame 1 r/w bit bit name initial value r/w 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 dtcmd 1 r/w 0 ? 1 r/w bit bit name initial value r/w descriptions 15 14 ? ? 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 13 macs 0 r/w mac saturation operation control selects either saturation operation or non-saturation operation for the mac instruction. 0: mac instruction is non-saturation operation 1: mac instruction is saturation operation 12 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 11 fetchmd 0 r/w instruction fetch mode select this lsi can prefetch an instruction in units of 16 bits or 32 bits. select the bus width for instruction fetch depending on the used memory for the storage of programs. 0: 32-bit mode 1: 16-bit mode section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 74 of 1102 rej09b0365-0100 bit bit name initial value r/w descriptions 10 ? undefined * 1 r reserved this bit is fixed at 1 in on-chip rom enabled mode, and 0 in on-chip rom disabled mode. this bit cannot be changed. 9 expe undefined * 1 r/w external bus mode enable selects external bus mode. in external extended mode, this bit is fixed 1 and cannot be changed. in single-chip mode, the initial value of th is bit is 0, and can be read from or written to when pckje = 0. do not write to this bit when pckje = 1 * 2 . when writing 0 to this bit after reading expe = 1, an external bus cycle should not be executed. the external bus cycle may be carried out in parallel with the internal bus cycle depending on the setting of the write data buffer function. 0: external bus disabled 1: external bus enabled 8 rame 1 r/w ram enable enables or disables the on-chip ram. this bit is initialized when the reset stat e is released. do not write 0 during access to the on-chip ram. 0: on-chip ram disabled 1: on-chip ram enabled 7 to 2 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 1 dtcmd 1 r/w dtc mode select selects dtc operating mode. 0: dtc is in full-address mode 1: dtc is in short address mode 0 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. notes: 1. the initial value varies according to the lsi initiation mode. 2. for details on the settings of the expe and pcjke bits when the external address space is in use, see section 11.3.11, port function control register d (pfcrd). section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 75 of 1102 rej09b0365-0100 3.3 operating mode descriptions 3.3.1 mode 1 this is the user boot mode for the flash memory. the lsi operates in the same way as in mode 7 except for programming and erasing of the flas h memory. for details, see section 21, flash memory. 3.3.2 mode 2 this is the boot mode for the flash memory. th e lsi operates in the same way as in mode 7 except for programming and erasing of the flas h memory. for details, see section 21, flash memory. 3.3.3 mode 3 this is the boundary scan function enabled single-chip activation mode. the operation is the same as mode 7 except for the boundary scan function. for details on the boundary scan function, see section 22, boundary scan. 3.3.4 mode 4 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is disabled. the initial bus width mode immediately after a rese t is 16 bits, with 16-bit access to all areas. ports d, e, and f function as an address bus, ports h and i function as a data bus, and parts of ports a and b function as bus control signals. however, if all areas are designated as an 8-bit access space by the bus contro ller, the bus mode switches to ei ght bits, and only port h functions as a data bus. 3.3.5 mode 5 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is disabled. the initial bus width mode immediately after a rese t is eight bits, with 8-bit access to all areas. ports d, e, and f function as an address bus, port h functions as a data bus, and parts of ports a and b function as bus control signals. however, if any area is designated as a 16-bit access space section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 76 of 1102 rej09b0365-0100 by the bus controller, the bus width mode switches to 16 bits, and ports h and i function as a data bus. 3.3.6 mode 6 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is enabled. the initial bus width mode immediately after a rese t is eight bits, with 8-bit access to all areas. ports d, e, and f function as input ports, but they can be used as an address bus by specifying the data direction register (ddr) for each port. for de tails, see section 11, i/o ports. port h functions as a data bus, and parts of ports a and b function as bus control signals. however, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports h and i function as a data bus. 3.3.7 mode 7 the cpu operating mode is adva nced mode in which the addres s space is 16 mbytes, and the on- chip rom is enabled. all i/o ports can be used as general input/output ports. the external address space cannot be accessed in the initial state, but se tting the expe bit in the system control register (syscr) to 1 enables the external addr ess space. after the external address space is en abled, ports d, e, and f can be used as an address output bus and ports h and i as a data bus by specifying the data direction register (ddr) for each port. when the external address space is not in use, ports j and k can be used by setting the pcjke bit in the port function control register d (pfcrd) to 1. for details, see section 11, i/o ports. section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 77 of 1102 rej09b0365-0100 3.3.8 pin functions table 3.3 lists the pin functions in each operating mode. table 3.3 pin functions in each operating mode (advanced mode) port a port b port c port d port e port f port h port i mcu operating mode pa 7 pa 6 to pa 3 pa 2 to pa 0 pb 7 to pb 1 pb 0 pc 1 to pc 0 pf 4 to pf 0 pf 7 to pf 5 1 p * /c p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /a p * /d p * /d 2 p * /c p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /a p * /d p * /d 3 p * /c p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /a p * /d p * /d 4 p/c * p/c * p * /c p * /c p/c * p * /c a a a p * /a d p/d * 5 p/c * p/c * p * /c p * /c p/c * p * /c a a a p * /a d p * /d 6 p/c * p/c * p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /a d p * /d 7 p * /c p * /c p * /c p * /c p * /c p * /c p * /a p * /a p * /a p * /a p * /d p * /d [legend] p: i/o port a: address bus output d: data bus input/output c: control signals, clock input/output * : immediately after a reset 3.4 address map 3.4.1 address map figures 3.1 to 3.3 sh ow the address map in each operating mode. section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 78 of 1102 rej09b0365-0100 modes 1 and 2 user boot mode, boot mode (advanced mode) e xternal address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area on-chip rom on-chip ram * 2 on-chip i/o registers on-chip i/o registers h'000000 h'100000 h'fee000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 modes 3 and 7 boundary scan enabled single-chip mode, single-chip mode (advanced mode) external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area on-chip rom on-chip ram/ external address space * 4 on-chip i/o registers on-chip i/o registers h'000000 h'100000 h'fee000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 h'fee000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff h'fec000 external address space external address space external address space external address space access prohibited area on-chip ram/ external address space * 4 on-chip i/o registers on-chip i/o registers access prohibited area modes 4 and 5 on-chip rom disabled extended mode (advanced mode) h'000000 this area is specified as the external address space when expe = 1 and the reserved area when expe = 0. the on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. do not access the reserved areas. this area is specified as the external address space by clearing the rame bit in syscr to 0. 1. 2. 3. 4. notes: figure 3.1 address map in each operating mode of h8sx/1648 (1) section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 79 of 1102 rej09b0365-0100 external address space on-chip rom mode 6 on-chip rom enabled extended mode (advanced mode) external address space external address space access prohibited area on-chip ram/ external address space * on-chip i/o registers on-chip i/o registers access prohibited area h'000000 h'100000 h'fee000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff h'fec000 external address space h'ffc000 this area is specified as the external address space by clearing the rame bit in syscr to 0. * note: figure 3.1 address map in each operating mode of h8sx/1648 (2) section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 80 of 1102 rej09b0365-0100 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area on-chip rom on-chip ram * 2 on-chip i/o registers on-chip i/o registers h'000000 h'080000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area access prohibited area access prohibited area on-chip rom on-chip i/o registers on-chip i/o registers h'100000 h'000000 h'080000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff h'fec000 h'100000 external address space external address space external address space external address space access prohibited area access prohibited area access prohibited area on-chip ram/ external address space * 4 on-chip ram/ external address space * 4 on-chip i/o registers on-chip i/o registers h'000000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'fec000 h'ffea00 h'ffff00 h'ffff20 h'ffffff this area is specified as the external address space when expe = 1 and the reserved area when expe = 0. the on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. do not access the reserved areas. this area is specified as the external address space by clearing the rame bit in syscr to 0. 1. 2. 3. 4. notes: modes 1 and 2 user boot mode, boot mode (advanced mode) modes 3 and 7 boundary scan enabled single-chip mode, single-chip mode (advanced mode) modes 4 and 5 on-chip rom disabled extended mode (advanced mode) figure 3.2 address map in each operating mode of h8sx/1644 (1) section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 81 of 1102 rej09b0365-0100 mode 6 on-chip rom enabled extended mode (advanced mode) external address space external address space external address space external address space access prohibited area on-chip rom on-chip ram/ external address space * on-chip i/o registers on-chip i/o registers h'000000 h'080000 h'ff2000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 access prohibited area h'100000 this area is specified as the external address space by clearing the rame bit in syscr to 0. * note: figure 3.2 address map in each operating mode of h8sx/1644 (2) section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 82 of 1102 rej09b0365-0100 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area on-chip rom on-chip ram * 2 on-chip i/o registers on-chip i/o registers h'000000 h'040000 h'ff6000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 external address space/ reserved area * 1 * 3 access prohibited area access prohibited area access prohibited area on-chip rom on-chip i/o registers on-chip i/o registers h'100000 h'000000 h'040000 h'ff6000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff h'fec000 h'100000 external address space external address space external address space external address space access prohibited area access prohibited area access prohibited area on-chip ram/ external address space * 4 on-chip ram/ external address space * 4 on-chip i/o registers on-chip i/o registers h'000000 h'ff6000 h'ffc000 h'fd9000 h'fdc000 h'fec000 h'ffea00 h'ffff00 h'ffff20 h'ffffff this area is specified as the external address space when expe = 1 and the reserved area when expe = 0. the on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. do not access the reserved areas. this area is specified as the external address space by clearing the rame bit in syscr to 0. 1. 2. 3. 4. notes: modes 1 and 2 user boot mode, boot mode (advanced mode) modes 3 and 7 boundary scan enabled single-chip mode, single-chip mode (advanced mode) modes 4 and 5 on-chip rom disabled extended mode (advanced mode) figure 3.3 address map in each operating mode of h8sx/1642 (1) section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 83 of 1102 rej09b0365-0100 mode 6 on-chip rom enabled extended mode (advanced mode) external address space external address space external address space external address space access prohibited area on-chip rom on-chip ram/ external address space * on-chip i/o registers on-chip i/o registers h'000000 h'040000 h'ff6000 h'ffc000 h'fd9000 h'fdc000 h'ffea00 h'ffff00 h'ffff20 h'ffffff access prohibited area h'fec000 access prohibited area h'100000 this area is specified as the external address space by clearing the rame bit in syscr to 0. * note: figure 3.3 address map in each operating mode of h8sx/1642 (2) section 3 mcu operating modes rev. 1.00 sep. 13, 2007 page 84 of 1102 rej09b0365-0100 section 4 resets rev. 1.00 sep. 13, 2007 page 85 of 1102 rej09b0365-0100 section 4 resets 4.1 types of resets there are three types of resets: a pin reset, deep software standby reset, and watchdog timer reset. table 4.1 shows the reset names and sources. the internal state and pins are initialized by a reset. figure 4.1 shows the reset targets to be initialized. table 4.1 reset names and sources reset name source pin reset voltage input to the res pin is driven low. deep software standby reset deep software standby mode is canceled by an interrupt. watchdog timer reset the watchdog timer overflows. registers related to power-down mode rstsr.dpsrstf dpsbycr, dpswcr, dpsier, dpsifr dpsiegr, dpsbkr rstcsr for wdt deep software standby reset watchdog timer reset pin reset res deep software standby reset generation circuit watchdog timer internal state other than above, and pin state figure 4.1 block diagram of reset circuit section 4 resets rev. 1.00 sep. 13, 2007 page 86 of 1102 rej09b0365-0100 note that some registers are not initialized by an y of the resets. the following describes the cpu internal registers. the pc, one of the cpu internal re gisters, is initialized by loadin g the start address from vector addresses with the reset exception handling. at this time, the t bit in exr is cleared to 0 and the i bits in exr and ccr are set to 1. the general registers, mac, and other bits in ccr are not initialized. the initial value of the sp (er7) is undefined. the sp should be initialized using the mov.l instruction immediately after a reset. for details, see section 2, cpu. for other registers that are not initialized by a reset, see regist er descriptions in each section. when a reset is canceled, the reset exception handling is started. for the reset exception handling, see section 5.3, reset. 4.2 input/output pin table 4.2 shows the pin related to resets. table 4.2 pin configuration pin name symbol i/o function reset res input reset input section 4 resets rev. 1.00 sep. 13, 2007 page 87 of 1102 rej09b0365-0100 4.3 register descriptions this lsi has the following registers for resets. ? reset status register (rstsr) ? reset control/status register (rstcsr) 4.3.1 reset status register (rstsr) rstsr indicates a source for generating an internal reset. bit bit name initial value: r/w: 7 dpsrstf 0 r/(w) * 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w note: * only 0 can be written to clear the flag. bit bit name initial value r/w description 7 dpsrstf 0 r/(w) * deep software standby reset flag indicates that deep software standby mode is canceled by an external interrupt source specified with dpsier or dpsiegr and an internal reset is generated. [setting condition] when deep software standby mode is canceled by an external interrupt source. [clearing conditions] ? when this bit is read as 1 and then written by 0. ? when a pin reset is generated. 6 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. note: * only 0 can be written to clear the flag. section 4 resets rev. 1.00 sep. 13, 2007 page 88 of 1102 rej09b0365-0100 4.3.2 reset control/status register (rstcsr) rstcsr controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. rstcsr is initialized to h?1f by a pin reset or a deep software standby reset, but not by the internal reset signal generated by a wdt overflow. bit bit name initial value: r/w: 7 wovf 0 r/(w) * 6 rste 0 r/w 5 ? 0 r/w 4 ? 1 r 3 ? 1 r 2 ? 1 r 1 ? 1 r 0 ? 1 r note: * only 0 can be written to clear the flag. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog timer overflow flag this bit is set when tcnt overflows in watchdog timer mode, but not set in interval timer mode. only 0 can be written to. [setting condition] when tcnt overflows (h?ff h?00) in watchdog timer mode. [clearing condition] when this bit is read as 1 and then written by 0. (the flag must be read after writing of 0, when this bit is cleared by the cpu using an interrupt.) 6 rste 0 r/w reset enable selects whether or not the lsi inte rnal state is reset by a tcnt overflow in watchdog timer mode. 0: internal state is not rese t when tcnt overflows. (although this lsi internal state is not reset, tcnt and tcsr of the wdt are reset.) 1: internal state is reset when tcnt overflows. 5 ? 0 r/w reserved although this bit is readable/writ able, operation is not affected by this bit. 4 to 0 ? 1 r reserved these are read-only bits but cannot be modified. note: * only 0 can be written to clear the flag. section 4 resets rev. 1.00 sep. 13, 2007 page 89 of 1102 rej09b0365-0100 4.4 pin reset this is a reset generated by the res pin. when the res pin is driven low, all the processing in progress is aborted and the lsi enters a reset state. in order to firmly reset the lsi, the stby pin should be set to high and the res pin should be held low at least for 20 ms at a power-on. during operation, the res pin should be held low at least for 20 states. 4.5 deep software standby reset this is an internal reset generated when deep software standby mode is canceled by an interrupt. when deep software standby mode is canceled, a deep software standby reset is generated, and simultaneously, clock oscillation starts. after th e time specified with dpswcr has elapsed, the deep software standby reset is canceled. for details of the deep software standby reset, see section 24, power-down modes. 4.6 watchdog timer reset this is an internal reset generated by the watchdog timer. when the rste bit in rstcsr is set to 1, a watchdog timer reset is generated by a tcnt overflow. after a certain time, the watchdog timer reset is canceled. for details of the watchdog timer reset, see section 15, watchdog timer (wdt). 4.7 determination of reset generation source reading rstcsr and rstsr determines which reset was used to execute the reset exception handling. figure 4.2 shows an example the flow to identify a reset generation source. section 4 resets rev. 1.00 sep. 13, 2007 page 90 of 1102 rej09b0365-0100 reset exception handling rstcsr.rste = 1 & rstcsr.wovf = 1 no yes no yes rstsr. dpsrstf=1 deep software standby reset pin reset watchdog timer reset figure 4.2 example of reset generation source determination flow section 5 exception handling rev. 1.00 sep. 13, 2007 page 91 of 1102 rej09b0365-0100 section 5 exception handling 5.1 exception handling types and priority as table 5.1 indicates, exception handling is cause d by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal instruction or slot illegal instruction). exception handling is prioritized as shown in table 5.1. if two or more exceptions occur simu ltaneously, they are accepted and processed in order of priority. exception sources, the stack structure, and operation of the cpu vary depending on the interrupt control mode. for details on the interrupt control mode, see section 6, interrupt controller. table 5.1 exception types and priority priority exception type e xception handling start timing high reset exception handling starts at the timing of level change from low to high on the res pin, or when the watchdog timer overflows. the cpu enters the reset state when the res pin is low. illegal instruction exception hand ling starts when an undefined code is executed. trace * 1 exception handling starts a fter execution of the current instruction or exception handling, if the trace (t) bit in exr is set to 1. address error after an address error has occurred, exception handling starts on completion of instruction execution. interrupt exception handling starts after execution of the current instruction or exception handli ng, if an interrupt request has occurred. * 2 sleep instruction exception handling star ts by execution of a sleep instruction (sleep), if the ssby bit in sbycr is set to 0 and the slpie bit in sbycr is set to 1. low trap instruction * 3 exception handling starts by execution of a trap instruction (trapa). notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on comple tion of reset exception handling. 3. trap instruction exception handling reques ts and sleep instruction exception handling requests are accepted at all time s in program execution state. section 5 exception handling rev. 1.00 sep. 13, 2007 page 92 of 1102 rej09b0365-0100 5.2 exception sources and exception handling vector table different vector table address offsets are assigned to different exception sources. the vector table addresses are calculated from th e contents of the vector base register (vbr) and vector table address offset of the v ector number. the start address of the exception service routine is fetched from the exception handling vector table in dicated by this vector table address. table 5.2 shows the corresponden ce between the exception sour ces and vector table address offsets. table 5.3 shows the calculation method of exception handling vector table addresses. table 5.2 exception handling vector table vector table address offset * 1 exception source vector number normal mode * 2 advanced, middle * 2 , maximum * 2 modes reset 0 h'0000 to h'0001 h'0000 to h'0003 reserved for system use 1 h'000 2 to h'0003 h' 0004 to h'0007 2 h'0004 to h'0005 h'0008 to h'000b 3 h'0006 to h'0007 h'000c to h'000f illegal instruction 4 h'0008 to h'0009 h'0010 to h'0013 trace 5 h'000a to h'000b h'0014 to h'0017 reserved for system use 6 h'000c to h'000d h'0018 to h'001b interrupt (nmi) 7 h'000e to h'000f h'001c to h'001f trap instruction (#0) 8 h'001 0 to h'0011 h'0020 to h'0023 (#1) 9 h'0012 to h'0013 h'0024 to h'0027 (#2) 10 h'0014 to h'0015 h'0028 to h'002b (#3) 11 h'0016 to h'0017 h'002c to h'002f cpu address error 12 h'0018 to h'0019 h'0030 to h'0033 dma address error * 3 13 h'001a to h'001b h'0034 to h'0037 ubc break interrupt 14 h?001c to h?001d h?0038 to h?003b reserved for system use 15 ? 17 h'001e to h'001f ? h'0022 to h'0023 h'003c to h'003f ? h'0044 to h'0047 sleep interrupt 18 h'0024 to h'0025 h'0048 to h'004b section 5 exception handling rev. 1.00 sep. 13, 2007 page 93 of 1102 rej09b0365-0100 vector table address offset * 1 exception source vector number normal mode * 2 advanced, middle * 2 , maximum * 2 modes reserved for system use 19 ? 23 h'0026 to h'0027 ? h'002e to h'002f h'004c to h'004f ? h'005c to h'005f user area (not used) 24 ? 63 h'0030 to h'0031 ? h'007e to h'007f h'0060 to h'0063 ? h'00fc to h'00ff external interrupt irq0 64 h'0080 to h'0081 h'0100 to h'0103 irq1 65 h'0082 to h'0083 h'0104 to h'0107 irq2 66 h'0084 to h'0085 h'0108 to h'010b irq3 67 h'0086 to h'0087 h'010c to h'010f irq4 68 h'0088 to h'0089 h'0110 to h'0113 irq5 69 h'008a to h'008b h'0114 to h'0117 irq6 70 h'008c to h'008d h'0118 to h'011b irq7 71 h'008e to h'008f h'011c to h'011f irq8 72 h'0090 to h'0091 h'0120 to h'0123 irq9 73 h'0092 to h'0093 h'0124 to h'0127 irq10 74 h'0094 to h'0095 h'0128 to h'012b irq11 75 h'0096 to h'0097 h'012c to h'012f irq12 76 h'0098 to h'0099 h'0130 to h'0133 irq13 77 h'009a to h'009b h'0134 to h'0137 irq14 78 h'009c to h'009d h'0138 to h'013b irq15 79 h'009e to h'009f h'013c to h'013f internal interrupt * 4 80 ? 255 h'00a0 to h'00a1 ? h'01fe to h'01ff h'0140 to h'0143 ? h'03fc to h'03ff notes: 1. lower 16 bits of the address. 2. not available in this lsi. 3. a dma address error is generated by the dtc and dmac. 4. for details of internal interrupt vectors, see section 6.5, interrupt exception handling vector table. section 5 exception handling rev. 1.00 sep. 13, 2007 page 94 of 1102 rej09b0365-0100 table 5.3 calculation method of exception handling vector table address exception source calculation method of vector table address reset, cpu address error vector table address = (vector table address offset) other than above vector table address = vbr + (vector table address offset) [legend] vbr: vector base register vector table address offset: see table 5.2. 5.3 reset a reset has priority over any other exception. when the res pin goes low, all processing halts and this lsi enters the reset state. to ensu re that this lsi is reset, hold the res pin low for at least 20 ms with the stby pin driven high when the power is turned on. when operation is in progress, hold the res pin low for at least 20 cycles. the chip can also be reset by overflow of th e watchdog timer. for details, see section 15, watchdog timer (wdt). a reset initializes the internal state of the cpu an d the registers of the on -chip peripheral modules. the interrupt control mode is 0 immediately after a reset. 5.3.1 reset exception handling when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized, vbr is cleared to h'00000000, the t bit is cleared to 0 in exr, and the i bits are set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the ad dress indicated by the pc. figures 5.1 and 5.2 show examples of the reset sequence. section 5 exception handling rev. 1.00 sep. 13, 2007 page 95 of 1102 rej09b0365-0100 5.3.2 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 5.3.3 on-chip peripheral functions after reset release after the reset state is released, mstpcra and mstpcrb are initialized to h'0fff and h'ffff, respectively, and all modules except the dtc and dmac ente r the module stop state. consequently, on-chip peripheral module registers cannot be read or written to. register reading and writing is enabled when the module stop state is canceled. res high vector fetch internal operation first instruction prefetch (1): reset exception handling vector address (when reset, (1) = h'000000) (2): start address (contents of reset exception handling vector address) (3) start address ((3) = (2)) (4) first instruction in the exception handling routine i internal address bus internal read signal internal write signal internal data bus (1) (2) (4) (3) figure 5.1 reset sequence (on-chip rom enabled advanced mode) section 5 exception handling rev. 1.00 sep. 13, 2007 page 96 of 1102 rej09b0365-0100 res rd hwr , lwr d15 to d0 high * * * b address bus vector fetch internal operation first instruction prefetch (1) (2) (4) (6) (3) (5) (1)(3) reset exception handling vector address (when reset, (1) = h'000000, (3) = h'000002) (2)(4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2)(4)) (6) first instruction in the exception handling routine note: * seven program wait cycles are inserted. figure 5.2 reset sequence (16-bit external access in on-chi p rom disabled advanced mode) section 5 exception handling rev. 1.00 sep. 13, 2007 page 97 of 1102 rej09b0365-0100 5.4 traces traces are enabled in interrupt control mode 2. tr ace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. before changing interrupt control modes, the t bit must be cleared. for details on interrupt contro l modes, see section 6, interrupt controller. if the t bit in exr is set to 1, trace mode is ac tivated. in trace mode, a tr ace exception occurs on completion of each instruction. trace mode is not affected by interrupt masking by ccr. table 5.4 shows the state of ccr and exr after execution of trace exception handling. trace mode is canceled by clearing the t bit in exr to 0 during the trace excepti on handling. however, the t bit saved on the stack retains its value of 1, and wh en control is returned from the trace exception handling routine by the rte inst ruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. interrupts are accepted even within th e trace exception handling routine. table 5.4 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui t i2 to i0 0 trace exception handling cannot be used. 2 1 ? 0 ? [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 5 exception handling rev. 1.00 sep. 13, 2007 page 98 of 1102 rej09b0365-0100 5.5 address error 5.5.1 address error source instruction fetch, stack operation, or data read/write shown in table 5.5 may cause an address error. table 5.5 bus cycle and address error bus cycle type bus master description address error instruction fetch cpu fetches instructi ons from even addresses no (normal) fetches instructions from odd addresses occurs fetches instructions from areas other than on-chip peripheral module space * 1 no (normal) fetches instructions from on-chip peripheral module space * 1 occurs fetches instructions from external memory space in single-chip mode occurs fetches instructions fr om access prohibited area .* 2 occurs stack operation cpu accesses stack w hen the stack pointer value is even address no (normal) accesses stack when the stack pointer value is odd occurs data read/write cpu accesses word data from even addresses no (normal) accesses word data from odd addresses no (normal) accesses external memory sp ace in single-chip mode occurs accesses to access prohibited area * 2 occurs data read/write dtc or dmac accesses word data from even addresses no (normal) accesses word data from odd addresses no (normal) accesses external memory sp ace in single-chip mode occurs accesses to access prohibited area * 2 occurs single address transfer dmac address access space is the external memory space for single address transfer no (normal) address access space is not the external memory space for single address transfer occurs notes: 1. for on-chip peripheral module spac e, see section 8, bus controller (bsc). 2. for the access prohibited area, refer to figure 3.1 in section 3.4, address map. section 5 exception handling rev. 1.00 sep. 13, 2007 page 99 of 1102 rej09b0365-0100 5.5.2 address error exception handling when an address error occurs, address error excep tion handling starts after the bus cycle causing the address error ends and curren t instruction execution complete s. the address error exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. an exception handling vector table address corresponding to the address error is generated, the start address of the exception se rvice routine is loaded from the vector table to pc, and program execution starts from that address. even though an address error occurs during a tran sition to an address error exception handling, the address error is not accepte d. this prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. if the sp contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (pc, ccr, and exr) are undefined. when an address error occurs, the following is performed to halt the dtc and dmac. ? the err bit of dtccr in the dtc is set to 1. ? the errf bit of dmdr_0 in the dmac is set to 1. ? the dte bits of dmdrs for all channels in the dmac are cleared to 0 to forcibly terminate transfer. table 5.6 shows the state of ccr and exr after execution of the address error exception handling. table 5.6 status of ccr and exr af ter address error exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 7 [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. section 5 exception handling rev. 1.00 sep. 13, 2007 page 100 of 1102 rej09b0365-0100 5.6 interrupts 5.6.1 interrupt sources interrupt sources are nmi, ubc break interrupt, irq0 to irq15, and on-chip peripheral modules, as shown in table 5.7. table 5.7 interrupt sources type source number of sources nmi nmi pin (external input) 1 ubc break interrupt user break controller (ubc) 1 dma controller (dmac) 8 watchdog timer (wdt) 1 on-chip peripheral module a/d converter 3 16-bit timer pulse unit (tpu) 52 8-bit timer (tmr) 16 serial communications interface (sci) 28 i 2 c bus interface 2 (iic2) 4 different vector numbers and vector table offsets are assigned to different interrupt sources. for vector number and vector table offset, refer to table 6.2, interrupt sources, vect or address offsets, and interrupt priority in section 6, interrupt controller. section 5 exception handling rev. 1.00 sep. 13, 2007 page 101 of 1102 rej09b0365-0100 5.6.2 interrupt exception handling interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiple-interrupt control. the source to start interrupt exception handling and the vector address differ depending on the product. for details, refer to section 6, interrupt controller. the interrupt exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. an exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to pc, and program execution starts from that address. 5.7 instruction exception handling there are three instructions that cause exception handling: trap instruction, sleep instruction, and illegal instruction. 5.7.1 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all time s in the program execution state. the trap instruction exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. an exception handling vector table address co rresponding to the vect or number specified in the trapa instruction is generated, the start addr ess of the exception serv ice routine is loaded from the vector table to pc, and progra m execution starts fr om that address. a start address is read from the vector table corr esponding to a vector number from 0 to 3, as specified in the instruction code. table 5.8 shows the state of ccr and exr after execution of trap instruction exception handling. section 5 exception handling rev. 1.00 sep. 13, 2007 page 102 of 1102 rej09b0365-0100 table 5.8 status of ccr and exr aft er trap instruction exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 ? [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. 5.7.2 sleep instruction exception handling the sleep instruction exception handling starts when a sleep instruction is executed with the ssby bit in sbycr set to 0 and the slpie bit in sbycr set to 1. the sleep instruction exception handling can always be executed in the program ex ecution state. in the exception handling, the cpu operates as follows. 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is update d and the t bit is cleared to 0. 3. an exception handling vector table address co rresponding to the vect or number specified in the sleep instruction is generated, the start addr ess of the excepti on service routine is loaded from the vector table to pc, and progra m execution starts from that address. bus masters other than the cpu may gain the bus mastership after a sleep instruction has been executed. in such cases the sleep instruction will be started when the transactions of a bus master other than the cpu has been completed and the cpu has gained the bus mastership. table 5.9 shows the state of ccr and exr after execution of sleep instruction exception handling. for details, see section 24.10, sleep instruction exception handling. section 5 exception handling rev. 1.00 sep. 13, 2007 page 103 of 1102 rej09b0365-0100 table 5.9 shows the state of ccr and exr after execution of sleep instruction exception handling. table 5.9 status of ccr and exr aft er sleep instruction exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 7 [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. 5.7.3 exception handling by illegal instruction the illegal instructions are general illegal instructions and slot illegal instructions. the exception handling by the general illegal instruction starts when an undefined code is executed. the exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the pc contents) at a delay slot (immediately after a delayed branch instruction) is executed. the exception handling by the general illegal instruction and slot illegal instruction is always exec utable in the program execution state. the exception handling is as follows: 1. the contents of pc, ccr, and exr are saved in the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. an exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception servi ce routine is loaded from the vector table to pc, and program execution starts from that address. section 5 exception handling rev. 1.00 sep. 13, 2007 page 104 of 1102 rej09b0365-0100 table 5.10 shows the state of ccr and exr afte r execution of illegal instruction exception handling. table 5.10 status of ccr and exr after illegal instruction exception handling ccr exr interrupt control mode i ui t i2 to i0 0 1 ? ? ? 2 1 ? 0 ? [legend] 1: set to 1 0: cleared to 0 ? : retains the previous value. 5.8 stack status after exception handling figure 5.3 shows the stack after completion of exception handling. ccr pc (24 bits) sp exr reserved * ccr pc (24 bits) sp advanced mode interrupt control mode 0 interrupt control mode 2 note: * ignored on return. figure 5.3 stack status after exception handling section 5 exception handling rev. 1.00 sep. 13, 2007 page 105 of 1102 rej09b0365-0100 5.9 usage note when performing stack-man ipulating access, this lsi assumes that the lowest address bit is 0. the stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (sp: er7) sh ould always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructio ns to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) performing stack manipulation while sp is set to an odd value leads to an ad dress error. figure 5.4 shows an example of operatio n when the sp value is odd. sp ccr : pc : r1l : sp : condition code register program counter general register r1l stack pointer ccr sp sp r1l h'fffefa h'fffefb h'fffefc h'fffefd h'fffefe h'fffeff pc pc trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address [legend] note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. (address error occurred) figure 5.4 operation when sp value is odd section 5 exception handling rev. 1.00 sep. 13, 2007 page 106 of 1102 rej09b0365-0100 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 107 of 1102 rej09b0365-0100 section 6 interrupt controller 6.1 features ? two interrupt control modes any of two interrupt control modes can be set by means of bits intm1 and intm0 in the interrupt control register (intcr). ? priority can be assigned by the in terrupt priority register (ipr) ipr provides for setting interrupt priory. eight levels can be set for each module for all interrupts except for the interrupt requests listed below. the following eight interrupt requests are given priority of 8, therefor e they are accepted at all times. ? nmi ? illegal instructions ? trace ? trap instructions ? cpu address error ? dma address error (occurred in the dtc and dmac) ? sleep instruction ? ubc break interrupt ? independent vector addresses all interrupt sources are assigned independent v ector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? seventeen external interrupts nmi is the highest-priority inte rrupt, and is accepted at all times. rising edge or falling edge detection can be selected for nmi. falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq15 to irq0 . ? dtc and dmac control dtc and dmac can be activated by means of interrupts. ? cpu priority control function the priority levels can be assigned to the cpu, dtc, and dmac. the priority level of the cpu can be automatically assigned on an exception generation. priority can be given to the cpu interrupt exception handling over that of the dtc and dmac transfer. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 108 of 1102 rej09b0365-0100 a block diagram of the interrupt controller is shown in figure 6.1. intcr ipr nmi input irq input internal interrupt sources wovi to adi1 intm1, intm0 nmieg nmi input unit irq input unit cpu priority dtc priority interrupt controller priority determination source selector cpu interrupt request cpu vector dtc vector activation request clear signal dtc activation request i i2 to i0 ccr exr cpu dtc intcr: cpupcr: iscr: ier: isr: interrupt control register cpu priority control register irq sense control register irq enable register irq status register ssier: ipr: dtcer: dtccr: software standby release irq enable register interrupt priority register dtc enable register dtc control register [legend] iscr ssier ier dtcer dtc priority control dtccr isr dmac activation permission dmdr dmac dmac priority control cpupcr figure 6.1 block diagra m of interrupt controller section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 109 of 1102 rej09b0365-0100 6.2 input/output pins table 6.1 shows the pin configuration of the interrupt controller. table 6.1 pin configuration name i/o function nmi input nonmaskable external interrupt rising or falling edge can be selected. irq15 to irq0 input maskable external interrupts rising, falling, or both edges , or level sensing, can be independently selected. 6.3 register descriptions the interrupt controller has the following registers. ? interrupt control register (intcr) ? cpu priority control register (cpupcr) ? interrupt priority registers a to i, k to o, q, and r (ipra to ipri, iprk to ipro, iprq, and iprr) ? irq enable register (ier) ? irq sense control registers h and l (iscrh, iscrl) ? irq status register (isr) ? software standby release ir q enable register (ssier) section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 110 of 1102 rej09b0365-0100 6.3.1 interrupt cont rol register (intcr) intcr selects the interrupt control mode, and the edge which detects nmi. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 7 6 ? ? 0 0 r r reserved these are read-only bits and cannot be modified. 5 4 intm1 intm0 0 0 r/w r/w interrupt control select mode 1 and 0 these bits select either of two interrupt control modes for the interrupt controller. 00: interrupt control mode 0 interrupts are controlled by i bit in ccr. 01: setting prohibited. 10: interrupt control mode 2 interrupts are controlled by bits i2 to i0 in exr, and ipr. 11: setting prohibited. 3 nmieg 0 r/w nmi edge select selects the input edge for the nmi pin. 0: interrupt request generated at falling edge of nmi input 1: interrupt request generated at rising edge of nmi input 2 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 111 of 1102 rej09b0365-0100 6.3.2 cpu priority control register (cpupcr) cpupcr sets whether or not the cpu has priority over the dtc and dmac. the interrupt exception handling by the cpu can be given priority over that of the dtc and dmac transfer. the priority level of the dtc is set by bits dt cp2 to dtcp0 in cpupcr. the priority level of the dmac is set by the dmac co ntrol register for each channel. bit bit name initial value r/w note: * when the ipsete bit is set to 1, the cpu priority is automatically updated, so these bits cannot be modified. 7 cpupce 0 r/w 6 dtcp2 0 r/w 5 dtcp1 0 r/w 4 dtcp0 0 r/w 3 ipsete 0 r/w 2 cpup2 0 r/(w) * 1 cpup1 0 r/(w) * 0 cpup0 0 r/(w) * bit bit name initial value r/w description 7 cpupce 0 r/w cpu priority control enable controls the cpu priority control function. setting this bit to 1 enables the cpu priority control over the dtc and dmac. 0: cpu always has the lowest priority 1: cpu priority control enabled 6 5 4 dtcp2 dtcp1 dtcp0 0 0 0 r/w r/w r/w dtc priority level 2 to 0 these bits set the dtc priority level. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 3 ipsete 0 r/w interrupt priority set enable controls the function which automatically assigns the interrupt priority level of t he cpu. setting this bit to 1 automatically sets bits cpup2 to cpup0 by the cpu interrupt mask bit (i bit in ccr or bits i2 to i0 in exr). 0: bits cpup2 to cpup0 ar e not updated automatically 1: the interrupt mask bit value is reflected in bits cpup2 to cpup0 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 112 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 1 0 cpup2 cpup1 cpup0 0 0 0 r/(w) * r/(w) * r/(w) * cpu priority level 2 to 0 these bits set the cpu priority level. when the cpupce is set to 1, the cpu priority control function over the dtc and dmac becomes valid and the priority of cpu processing is assigned in accordance with the settings of bits cpup2 to cpup0. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) note: * when the ipsete bit is set to 1, the cpu priori ty is automatically updated, so these bits cannot be modified. 6.3.3 interrupt priority registers a to i, k to o, q, and r (ipra to ipri, iprk to ipro, iprq, and iprr) ipr sets priory (levels 7 to 0) for interrupts other than nmi. setting a value in the range from b'000 to b'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. for the correspondence between the interrupt sources and the ipr settings, see table 6.2. bit bit name initial value r/w 15 ? 0 r 14 ipr14 1 r/w 13 ipr13 1 r/w 12 ipr12 1 r/w 11 ? 0 r 10 ipr10 1 r/w 9 ipr9 1 r/w 8 ipr8 1 r/w bit bit name initial value r/w 7 ? 0 r 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 ? 0 r 2 ipr2 1 r/w 1 ipr1 1 r/w 0 ipr0 1 r/w section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 113 of 1102 rej09b0365-0100 bit bit name initial value r/w description 15 ? 0 r reserved this is a read-only bit and cannot be modified. 14 13 12 ipr14 ipr13 ipr12 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 11 ? 0 r reserved this is a read-only bit and cannot be modified. 10 9 8 ipr10 ipr9 ipr8 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 7 ? 0 r reserved this is a read-only bit and cannot be modified. 6 5 4 ipr6 ipr5 ipr4 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 114 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 ? 0 r reserved this is a read-only bit and cannot be modified. 2 1 0 ipr2 ipr1 ipr0 1 1 1 r/w r/w r/w sets the priority level of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 6.3.4 irq enable register (ier) ier enables interrupt requests irq15 to irq0. bit bit name initial value r/w 15 irq15e 0 r/w 14 irq14e 0 r/w 13 irq13e 0 r/w 12 irq12e 0 r/w 11 irq11e 0 r/w 10 irq10e 0 r/w 9 irq9e 0 r/w 8 irq8e 0 r/w bit bit name initial value r/w 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w bit bit name initial value r/w description 15 irq15e 0 r/w irq15 enable the irq15 interrupt request is enabled when this bit is 1. 14 irq14e 0 r/w irq14 enable the irq14 interrupt request is enabled when this bit is 1. 13 irq13e 0 r/w irq13 enable the irq13 interrupt request is enabled when this bit is 1. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 115 of 1102 rej09b0365-0100 bit bit name initial value r/w description 12 irq12e 0 r/w irq12 enable the irq12 interrupt request is enabled when this bit is 1. 11 irq11e 0 r/w irq11 enable the irq11 interrupt request is enabled when this bit is 1. 10 irq10e 0 r/w irq10 enable the irq10 interrupt request is enabled when this bit is 1. 9 irq9e 0 r/w irq9 enable the irq9 interrupt request is enabled when this bit is 1. 8 irq8e 0 r/w irq8 enable the irq8 interrupt request is enabled when this bit is 1. 7 irq7e 0 r/w irq7 enable the irq7 interrupt request is enabled when this bit is 1. 6 irq6e 0 r/w irq6 enable the irq6 interrupt request is enabled when this bit is 1. 5 irq5e 0 r/w irq5 enable the irq5 interrupt request is enabled when this bit is 1. 4 irq4e 0 r/w irq4 enable the irq4 interrupt request is enabled when this bit is 1. 3 irq3e 0 r/w irq3 enable the irq3 interrupt request is enabled when this bit is 1. 2 irq2e 0 r/w irq2 enable the irq2 interrupt request is enabled when this bit is 1. 1 irq1e 0 r/w irq1 enable the irq1 interrupt request is enabled when this bit is 1. 0 irq0e 0 r/w irq0 enable the irq0 interrupt request is enabled when this bit is 1. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 116 of 1102 rej09b0365-0100 6.3.5 irq sense control registers h and l (iscrh, iscrl) iscrh and iscrl select the sour ce that generates an interrupt request from irq15 to irq0 input. upon changing the setting of iscr, irqnf (n = 0 to 15) in isr is often set to 1 accidentally through an internal operation. in this case, an in terrupt exception handling is executed if an irqn interrupt request is enabled. in order to prevent such an accidental interrupt from occurring, the setting of iscr should be changed while the irqn interrupt is disabled, and then the irqnf in isr should be cleared to 0. ? iscrh bit bit name initial value r/w bit bit name initial value r/w 15 irq15sr 0 r/w 14 irq15sf 0 r/w 13 irq14sr 0 r/w 12 irq14sf 0 r/w 11 irq13sr 0 r/w 10 irq13sf 0 r/w 9 irq12sr 0 r/w 8 irq12sf 0 r/w 7 irq11sr 0 r/w 6 irq11sf 0 r/w 5 irq10sr 0 r/w 4 irq10sf 0 r/w 3 irq9sr 0 r/w 2 irq9sf 0 r/w 1 irq8sr 0 r/w 0 irq8sf 0 r/w ? iscrl bit bit name initial value r/w bit bit name initial value r/w 15 irq7sr 0 r/w 14 irq7sf 0 r/w 13 irq6sr 0 r/w 12 irq6sf 0 r/w 11 irq5sr 0 r/w 10 irq5sf 0 r/w 9 irq4sr 0 r/w 8 irq4sf 0 r/w 7 irq3sr 0 r/w 6 irq3sf 0 r/w 5 irq2sr 0 r/w 4 irq2sf 0 r/w 3 irq1sr 0 r/w 2 irq1sf 0 r/w 1 irq0sr 0 r/w 0 irq0sf 0 r/w section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 117 of 1102 rej09b0365-0100 ? iscrh bit bit name initial value r/w description 15 14 irq15sr irq15sf 0 0 r/w r/w irq15 sense control rise irq15 sense control fall 00: interrupt request generated by low level of irq15 01: interrupt request generated at falling edge of irq15 10: interrupt request generated at rising edge of irq15 11: interrupt request generated at both falling and rising edges of irq15 13 12 irq14sr irq14sf 0 0 r/w r/w irq14 sense control rise irq14 sense control fall 00: interrupt request generated by low level of irq14 01: interrupt request generated at falling edge of irq14 10: interrupt request generated at rising edge of irq14 11: interrupt request generated at both falling and rising edges of irq14 11 10 irq13sr irq13sf 0 0 r/w r/w irq13 sense control rise irq13 sense control fall 00: interrupt request generated by low level of irq13 01: interrupt request generated at falling edge of irq13 10: interrupt request generated at rising edge of irq13 11: interrupt request generated at both falling and rising edges of irq13 9 8 irq12sr irq12sf 0 0 r/w r/w irq12 sense control rise irq12 sense control fall 00: interrupt request generated by low level of irq12 01: interrupt request generated at falling edge of irq12 10: interrupt request generated at rising edge of irq12 11: interrupt request generated at both falling and rising edges of irq12 7 6 irq11sr irq11sf 0 0 r/w r/w irq11 sense control rise irq11 sense control fall 00: interrupt request generated by low level of irq11 01: interrupt request generated at falling edge of irq11 10: interrupt request generated at rising edge of irq11 11: interrupt request generated at both falling and rising edges of irq11 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 118 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 4 irq10sr irq10sf 0 0 r/w r/w irq10 sense control rise irq10 sense control fall 00: interrupt request generated by low level of irq10 01: interrupt request generated at falling edge of irq10 10: interrupt request generated at rising edge of irq10 11: interrupt request generated at both falling and rising edges of irq10 3 2 irq9sr irq9sf 0 0 r/w r/w irq9 sense control rise irq9 sense control fall 00: interrupt request generated by low level of irq9 01: interrupt request generated at falling edge of irq9 10: interrupt request generated at rising edge of irq9 11: interrupt request generated at both falling and rising edges of irq9 1 0 irq8sr irq8sf 0 0 r/w r/w irq8 sense control rise irq8 sense control fall 00: interrupt request generated by low level of irq8 01: interrupt request generated at falling edge of irq8 10: interrupt request generated at rising edge of irq8 11: interrupt request generated at both falling and rising edges of irq8 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 119 of 1102 rej09b0365-0100 ? iscrl bit bit name initial value r/w description 15 14 irq7sr irq7sf 0 0 r/w r/w irq7 sense control rise irq7 sense control fall 00: interrupt request generated by low level of irq7 01: interrupt request generated at falling edge of irq7 10: interrupt request generated at rising edge of irq7 11: interrupt request generated at both falling and rising edges of irq7 13 12 irq6sr irq6sf 0 0 r/w r/w irq6 sense control rise irq6 sense control fall 00: interrupt request generated by low level of irq6 01: interrupt request generated at falling edge of irq6 10: interrupt request generated at rising edge of irq6 11: interrupt request generated at both falling and rising edges of irq6 11 10 irq5sr irq5sf 0 0 r/w r/w irq5 sense control rise irq5 sense control fall 00: interrupt request generated by low level of irq5 01: interrupt request generated at falling edge of irq5 10: interrupt request generated at rising edge of irq5 11: interrupt request generated at both falling and rising edges of irq5 9 8 irq4sr irq4sf 0 0 r/w r/w irq4 sense control rise irq4 sense control fall 00: interrupt request generated by low level of irq4 01: interrupt request generated at falling edge of irq4 10: interrupt request generated at rising edge of irq4 11: interrupt request generated at both falling and rising edges of irq4 7 6 irq3sr irq3sf 0 0 r/w r/w irq3 sense control rise irq3 sense control fall 00: interrupt request generated by low level of irq3 01: interrupt request generated at falling edge of irq3 10: interrupt request generated at rising edge of irq3 11: interrupt request generated at both falling and rising edges of irq3 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 120 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 4 irq2sr irq2sf 0 0 r/w r/w irq2 sense control rise irq2 sense control fall 00: interrupt request generated by low level of irq2 01: interrupt request generated at falling edge of irq2 10: interrupt request generated at rising edge of irq2 11: interrupt request generated at both falling and rising edges of irq2 3 2 irq1sr irq1sf 0 0 r/w r/w irq1 sense control rise irq1 sense control fall 00: interrupt request generated by low level of irq1 01: interrupt request generated at falling edge of irq1 10: interrupt request generated at rising edge of irq1 11: interrupt request generated at both falling and rising edges of irq1 1 0 irq0sr irq0sf 0 0 r/w r/w irq0 sense control rise irq0 sense control fall 00: interrupt request generated by low level of irq0 01: interrupt request generated at falling edge of irq0 10: interrupt request generated at rising edge of irq0 11: interrupt request generated at both falling and rising edges of irq0 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 121 of 1102 rej09b0365-0100 6.3.6 irq status register (isr) isr is an irq15 to irq0 interrupt request register. bit bit name initial value r/w 15 irq15f 0 r/(w) * 14 irq14f 0 r/(w) * 13 irq13f 0 r/(w) * 12 irq12f 0 r/(w) * 11 irq11f 0 r/(w) * 10 irq10f 0 r/(w) * 9 irq9f 0 r/(w) * 8 irq8f 0 r/(w) * bit bit name initial value r/w note: * only 0 can be written, to clear the flag. the bit manipulation instructions or memory operation instructions should be used to clear the flag. 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f 0 r/(w) * bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irq15f irq14f irq13f irq12f irq11f irq10f irq9f irq8f irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * [setting condition] ? when the interrupt selected by iscr occurs [clearing conditions] ? writing 0 after reading irqnf = 1 (n = 11 to 0) ? when interrupt exception handling is executed while low-level sensing is selected and irqn input is high ? when irqn interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 note: * only 0 can be written, to clear the flag. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 122 of 1102 rej09b0365-0100 6.3.7 software standby release irq enable register (ssier) ssier selects the irq interrupt used to leave software standby mode. the irq interrupt used to leave software standby mode should not be set as the dtc activation source. bit bit name initial value r/w 15 ssi15 0 r/w 14 ssi14 0 r/w 13 ssi13 0 r/w 12 ssi12 0 r/w 11 ssi11 0 r/w 10 ssi10 0 r/w 9 ssi9 0 r/w 8 ssi8 0 r/w bit bit name initial value r/w 7 ssi7 0 r/w 6 ssi6 0 r/w 5 ssi5 0 r/w 4 ssi4 0 r/w 3 ssi3 0 r/w 2 ssi2 0 r/w 1 ssi1 0 r/w 0 ssi0 0 r/w bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssi15 ssi14 ssi13 ssi12 ssi11 ssi10 ssi9 ssi8 ssi7 ssi6 ssi5 ssi4 ssi3 ssi2 ssi1 ssi0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w software standby release irq setting these bits select the irqn interrupt used to leave software standby mode (n = 15 to 0). 0: an irqn request is not sampled in software standby mode 1: when an irqn request occurs in software standby mode, this lsi leaves software standby mode after the oscillation settling time has elapsed section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 123 of 1102 rej09b0365-0100 6.4 interrupt sources 6.4.1 external interrupts there are seventeen external interrupts: nmi and ir q15 to irq0. these interrupts can be used to leave software standby mode. (1) nmi interrupts nonmaskable interrupt request (nm i) is the highest-priority interr upt, and is always accepted by the cpu regardless of the interrupt control mode or the settings of the cpu interrupt mask bits. the nmieg bit in intcr selects whether an interrupt is requested at the rising or falling edge on the nmi pin. when an nmi interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. ? sets the err bit of dtccr in the dtc to 1. ? sets the errf bit of dmdr_0 in the dmac to 1 ? clears the dte bits of dmdrs for all channels in the dmac to 0 to forcibly terminate transfer (2) irqn interrupts an irqn interrupt is requested by a signal input on pins irq15 to irq0 . irqn (n = 15 to 0) have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins irqn . ? enabling or disabling of interrupt requests irqn can be selected by ier. ? the interrupt priority can be set by ipr. ? the status of interrupt requests irqn is indicat ed in isr. isr flags can be cleared to 0 by software. the bit manipulation instructions and memory operation instructions should be used to clear the flag. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 124 of 1102 rej09b0365-0100 detection of irqn interrupts is enabled throug h the p1icr, p2icr, p5icr, and p6icr register settings, and does not change regardless of the output setting. however, when a pin is used as an external interrupt input pin, the pin must not be used as an i/o pin for another function by clearing the corresponding ddr bit to 0. a block diagram of interrupts irqn is shown in figure 6.2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit input buffer corresponding bit in icr irqnsf, irqnsr irqn input [legend] n = 15 to 0 figure 6.2 block diagra m of interrupts irqn when the irq sensing control in iscr is set to a low level of signal irqn , the level of irqn should be held low until an interrupt handling starts. then set the corresponding input signal irqn to high in the interrupt handling routine and clear the irqnf to 0. interrupts may not be executed when the corresponding input signal irqn is set to high before the interrupt handling begins. 6.4.2 internal interrupts the sources for internal interrupts from on-chip peripheral modules have the following features: ? for each on-chip peripheral module there are fl ags that indicate the in terrupt request status, and enable bits that enable or disable these interrupts. they can be controlled independently. when the enable bit is set to 1, an interrupt request is issued to the interrupt controller. ? the interrupt priority can be set by means of ipr. ? the dtc and dmac can be activated by a tpu, sci, or other interrupt request. ? the priority levels of dtc and dmac activation can be controlled by the dtc and dmac priority control functions. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 125 of 1102 rej09b0365-0100 6.5 interrupt exception handling vector table table 6.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. in the default priority order, a lower vector number corresponds to a higher priority. when interrupt control mode 2 is set, priority levels can be changed by setting the ipr contents. the priority for interrupt sources allocated to the same level in ipr follows the default priority, that is, they are fixed. table 6.2 interrupt sources , vector address offsets, and interrupt priority vector address offset * classification interrupt source vector number advanced mode middle mode maximum mode ipr priority dtc activation dmac activation external pin nmi 7 h'001c ? ? ? ubc ubc break interrupt 14 h'0038 ? high ? ? external pin irq0 64 h'0100 ipra14 to ipra12 o ? irq1 65 h'0104 ipra10 to ipra8 o ? irq2 66 h'0108 ipra6 to ipra4 o ? irq3 67 h'010c ipra2 to ipra0 o ? irq4 68 h'0110 iprb14 to iprb12 o ? irq5 69 h'0114 iprb10 to iprb8 o ? irq6 70 h'0118 iprb6 to iprb4 o ? irq7 71 h'011c iprb2 to iprb0 o ? irq8 72 h'0120 iprc14 to iprc12 o ? irq9 73 h'0124 iprc10 to iprc8 o ? irq10 74 h'0128 iprc6 to iprc4 o ? irq11 75 h'012c iprc2 to iprc0 o ? irq12 76 h'0130 iprd14 to iprd12 o ? irq13 77 h'0134 iprd10 to iprd8 o ? irq14 78 h'0138 iprd6 to iprd4 o ? irq15 79 h'013c iprd2 to iprd0 o ? ? reserved for system use 80 h'0140 ? ? ? wdt wovi 81 h'0144 ipre10 to ipre8 low ? ? section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 126 of 1102 rej09b0365-0100 vector address offset * classification interrupt source vector number advanced mode middle mode maximum mode ipr priority dtc activation dmac activation ? reserved for system use 82 h'0148 high ? ? ? reserved for system use 83 h'014c ? ? ? reserved for system use 84 h'0150 ? ? ? reserved for system use 85 h'0154 ? ? ? a/d_0 adi0 86 h'0158 iprf10 to iprf8 o o ? reserved for system use 87 h'015c ? ? ? tgi0a 88 h'0160 o o tpu_0 tgi0b 89 h'0164 iprf6 to iprf4 o ? tgi0c 90 h'0168 o ? tgi0d 91 h'016c o ? tci0v 92 h'0170 ? ? tgi1a 93 h'0174 o o tpu_1 tgi1b 94 h'0178 iprf2 to iprf0 o ? tci1v 95 h'017c ? ? tci1u 96 h'0180 ? ? tgi2a 97 h'0184 o o tpu_2 tgi2b 98 h'0188 iprg14 to iprg12 o ? tci2v 99 h'018c ? ? tci2u 100 h'0190 ? ? tgi3a 101 h'0194 o o tpu_3 tgi3b 102 h'0198 iprg10 to iprg8 o ? tgi3c 103 h'019c o ? tgi3d 104 h'01a0 o ? tci3v 105 h'01a4 ? ? tgi4a 106 h'01a8 o o tpu_4 tgi4b 107 h'01ac iprg6 to iprg4 o ? tci4v 108 h'01b0 ? ? tci4u 109 h'01b4 low ? ? section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 127 of 1102 rej09b0365-0100 vector address offset * classification interrupt source vector number advanced mode middle mode maximum mode ipr priority dtc activation dmac activation tgi5a 110 h'01b8 high o o tpu_5 tgi5b 111 h'01bc iprg2 to iprg0 o ? tci5v 112 h'01c0 ? ? tci5u 113 h'01c4 ? ? ? 114 h'01c8 ? ? reserved for system use 115 h'01cc ? ? ? cmi0a 116 h'01d0 o ? tmr_0 cmi0b 117 h'01d4 iprh14 to iprh12 o ? ov0i 118 h'01d8 ? ? cmi1a 119 h'01dc o ? tmr_1 cmi1b 120 h'01e0 iprh10 to iprh8 o ? ov1i 121 h'01e4 ? ? cmi2a 122 h'01e8 o ? tmr_2 cmi2b 123 h'01ec iprh6 to iprh4 o ? ov2i 124 h'01f0 ? ? cmi3a 125 h'01f4 o ? tmr_3 cmi3b 126 h'01f8 iprh2 to iprh0 o ? ov3i 127 h'01fc ? ? dmtend0 128 h'0200 ipri14 to ipri12 o ? dmac dmtend1 129 h'0204 ipri10 to ipri8 o ? dmtend2 130 h'0208 ipri6 to ipri4 o ? dmtend3 131 h'020c ipri2 to ipri0 o ? 132 h'0210 ? ? ? reserved for system use 133 h'0214 ? ? ? 134 h'0218 ? ? 135 h'021c ? ? dmeend0 136 h'0220 o ? dmac dmeend1 137 h'0224 iprk14 to iprk12 o ? dmeend2 138 h'0228 o ? dmeend3 139 h'022c low o ? section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 128 of 1102 rej09b0365-0100 vector address offset * classification interrupt source vector number advanced mode middle mode maximum mode ipr priority dtc activation dmac activation 140 h'0230 high ? ? ? reserved for system use 141 h'0234 ? ? ? 142 h'0238 ? ? 143 h'023c ? ? eri0 144 h'0240 ? ? sci_0 rxi0 145 h'0244 iprk6 to iprk4 o o txi0 146 h'0248 o o tei0 147 h'024c ? ? eri1 148 h'0250 ? ? sci_1 rxi1 149 h'0254 iprk2 to iprk0 o o txi1 150 h'0258 o o tei1 151 h'025c ? ? eri2 152 h'0260 ? ? sci_2 rxi2 153 h'0264 iprl14 to iprl12 o o txi2 154 h'0268 o o tei2 155 h'026c ? ? eri3 156 h'0270 ? ? sci_3 rxi3 157 h'0274 iprl10 to iprl8 o o txi3 158 h'0278 o o tei3 159 h'027c ? ? eri4 160 h'0280 ? ? sci_4 rxi4 161 h'0284 iprl6 to iprl4 o o txi4 162 h'0288 o o tei4 163 h'028c low ? ? section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 129 of 1102 rej09b0365-0100 vector address offset * classification interrupt source vector number advanced mode middle mode maximum mode ipr priority dtc activation dmac activation tgi6a 164 h'0290 high o o tgi6b 165 h'0294 o ? tgi6c 166 h'0298 o ? tgi6d 167 h'029c iprl2 to iprl0 o ? tpu_6 tci6v 168 h'02a0 iprm14 to iprm12 ? ? tgi7a 169 h'02a4 o o tgi7b 170 h'02a8 iprm10 to iprm8 o ? tci7v 171 h'02ac ? ? tpu_7 tci7u 172 h'02b0 iprm6 to iprm4 ? ? tgi8a 173 h'02b4 o o tgi8b 174 h'02b8 iprm2 to iprm0 o ? tci8v 175 h'02bc ? ? tpu_8 tci8u 176 h'02c0 iprn14 to iprn12 ? ? tgi9a 177 h'02c4 o o tgi9b 178 h'02c8 o ? tgi9c 179 h'02cc o ? tgi9d 180 h'02d0 iprn10 to iprn8 o ? tpu_9 tci9v 181 h'02d4 iprn6 to iprn4 ? ? tgi10a 182 h'02d8 o o tgi10b 183 h'02dc iprn2 to iprn0 o ? reserved for system use 184 h'02e0 ? ? reserved for system use 185 h'02e4 ? ? ? tci10v 186 h'02e8 o ? tpu_10 tci10u 187 h'02ec ipro14 to ipro12 ? ? tgi11a 188 h'02f0 o o tgi11b 189 h'02f4 ipro10 to ipro8 o ? tci11v 190 h'02f8 ? ? tpu_11 tci11u 191 h'02fc ipro6 to ipro4 low ? ? section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 130 of 1102 rej09b0365-0100 vector address offset * classification interrupt source vector number advanced mode middle mode maximum mode ipr priority dtc activation dmac activation ? reserved for system use 192 | 215 h'0300 | h'035c ? high ? | ? ? | ? iic2_0 iici0 216 h'0360 ? ? ? reserved for system use 217 h'0364 iprq6 to iprq4 ? ? iic2_1 iici1 218 h'0368 ? ? ? reserved for system use 219 h'036c ? ? rxi5 220 h'0370 ? o sci_5 txi5 221 h'0374 iprq2 to iprq0 ? o eri5 222 h'0378 ? ? tei5 223 h'037c ? ? rxi6 224 h'0380 ? o sci_6 txi6 225 h'0384 iprr14 to iprr12 ? o eri6 226 h'0388 ? ? tei6 227 h'038c ? ? tmr_4 cmia4 or cmib4 228 h'0390 ? ? tmr_5 cmia5 or cmib5 229 h'0394 iprr10 to iprr8 ? ? tmr_6 cmia6 or cmib6 230 h'0398 ? ? tmr_7 cmia7 or cmib7 231 h'039c ? ? a/d_2 adi2 232 h'03a0 ? o ? reserved for system use 233 h'03a4 ? ? iic2_2 iici2 234 h'03a8 ? ? iic2_3 iici3 235 h'03ac iprr6 to iprr4 ? ? ? reserved for system use 236 h'03b0 ? ? ? a/d_1 adi1 237 h'03b4 iprr2 to iprr0 ? o ? reserved for system use 238 | 255 h'03b8 | h'03fc ? low ? | ? ? | ? note: * lower 16 bits of the start address. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 131 of 1102 rej09b0365-0100 6.6 interrupt control modes and interrupt operation the interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. interrupt operations differ depending on the interrupt control mode. the interrupt control mode is selected by intcr. table 6.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. table 6.3 interrupt control modes interrupt control mode priority setting register interrupt mask bit description 0 default i the priority levels of the interrupt sources are fixed default settings. the interrupts except for nmi is masked by the i bit. 2 ipr i2 to i0 eight priority leve ls can be set for interrupt sources except for nmi with ipr. 8-level interrupt mask control is performed by bits i2 to i0. 6.6.1 interrupt control mode 0 in interrupt control mode 0, interrupt requests except for nmi are masked by the i bit in ccr of the cpu. figure 6.3 shows a flowchart of th e interrupt acceptance oper ation in this case. 1. if an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. if the i bit in ccr is set to 1, nmi is accepted, and other interrupt requests are held pending. if the i bit is cleared to 0, an interrupt request is accepted. 3. for multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the cpu, and holds other interrupt requests pending. 4. when the cpu accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc and ccr contents are saved to the st ack area during the inte rrupt exception handling. the pc contents saved on the stack is the addres s of the first instructio n to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except nmi. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 132 of 1102 rej09b0365-0100 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. program execution state interrupt generated? nmi irq0 irq1 tei4 i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no pending figure 6.3 flowchart of proce dure up to interrupt acceptance in interrupt control mode 0 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 133 of 1102 rej09b0365-0100 6.6.2 interrupt control mode 2 in interrupt control mode 2, interrupt requests except for nmi are ma sked by comparing the interrupt mask level (i2 to i0 bits) in exr of th e cpu and the ipr setting. there are eight levels in mask control. figure 6.4 shows a flowchart of the interrupt acceptance ope ration in this case. 1. if an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. for multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to th e ipr setting, and holds other interrupt requests pending. if multiple interrupt requests have th e same priority, an interrupt re quest is selected according to the default setting shown in table 6.2. 3. next, the priority of the selected interrupt reque st is compared with the interrupt mask level set in exr. when the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt re quest with a priority over the interrupt mask level is accepted. 4. when the cpu accepts an interrupt request, it starts interrupt exce ption handling after execution of the current instruction has been completed. 5. the pc, ccr, and exr contents are saved to the stack area during interrupt exception handling. the pc saved on the stack is the addres s of the first instruction to be executed after returning from the interrupt handling routine. 6. the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority of the accepted interrupt. if the accepted interrupt is nm i, the interrupt mask level is set to h'7. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 134 of 1102 rej09b0365-0100 yes program execution state interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 6.4 flowchart of proce dure up to interrupt acceptance in interrupt control mode 2 section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 135 of 1102 rej09b0365-0100 6.6.3 interrupt except ion handling sequence figure 6.5 shows the interrupt exception handlin g sequence. the example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip memory. (12) (10) (6) (4) (2) (1) (5) (7) (9) (11) instruction prefetch interrupt acceptance interrupt level determination wait for end of instruction (3) (8) instruction prefetch in interrupt handling routine internal operation vector fetch stack internal operation interrupt request signal internal address bus internal read signal internal write signal internal data bus i (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp ? 2 sp ? 4 saved pc and saved ccr vector address start address of interrupt handling routine (vector address contents) start address of interrupt handling routine ((11) = (10)) first instruction of interrupt handling routine (6) (8) (9) (10) (11) (12) figure 6.5 interrupt exception handling section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 136 of 1102 rej09b0365-0100 6.6.4 interrupt response times table 6.4 shows interrupt response times ? the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the symbols for execution states used in table 6.4 ar e explained in table 6.5. this lsi is capable of fast word transfer to on -chip memory, so allocating the program area in on- chip rom and the stack ar ea in on-chip ram enable s high-speed processing. table 6.4 interrupt response times normal mode * 5 advanced mode maximum mode * 5 execution state interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 interrupt priority determination * 1 3 number of states until executing instruction ends * 2 1 to 19 + 2s i pc, ccr, exr stacking s k to 2s k * 6 2s k s k to 2s k * 6 2s k 2s k 2s k vector fetch s h instruction fetch * 3 2s i internal processing * 4 2 total (using on-chip memory) 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 notes: 1. two states for an internal interrupt. 2. in the case of the mulxs or divxs instruction 3. prefetch after interrupt acceptance or for an instruction in the inte rrupt handling routine. 4. internal operation after interru pt acceptance or after vector fetch 5. not available in this lsi. 6. when setting the sp value to 4n, the interrupt response time is s k ; when setting to 4n + 2, the interrupt response time is 2s k . section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 137 of 1102 rej09b0365-0100 table 6.5 number of execution states in interrupt ha ndling routine object of access external device 8-bit bus 16-bit bus symbol on-chip memory 2-state access 3-state access 2-state access 3-state access vector fetch s h 1 8 12 + 4m 4 6 + 2m instruction fetch s i 1 4 6 + 2m 2 3 + m stack manipulation s k 1 8 12 + 4m 4 6 + 2m [legend] m: number of wait cycles in an external device access. 6.6.5 dtc and dmac acti vation by interrupt the dtc and dmac can be activated by an interr upt. in this case, the following options are available: ? interrupt request to the cpu ? activation request to the dtc ? activation request to the dmac ? combination of the above for details on interrupt requests that can be us ed to activate the dtc an d dmac, see table 6.2, section 9, dma controller (dmac), and section 10, data transfer controller (dtc). figure 6.6 shows a block diagram of the dtc, dmac, and interrupt controller. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 138 of 1102 rej09b0365-0100 select signal dtcer dmrsr_0 to dmrsr_3 select signal irq interrupt on-chip peripheral module interrupt controller clear signal control signal dmac activation request signal clear signal dtc/cpu select circuit dmac select circuit dtc control circuit priority determination dtc dmac cpu interrupt request clear signal interrupt request interrupt request clear signal interrupt request clear signal interrupt request dtc activation request vector number cpu interrupt request vector number clear signal i, i2 to i0 figure 6.6 block diagram of dtc, dmac, and interrupt controller (1) selection of interrupt sources the activation source for each dmac channel is selected by dmrsr. th e selected activation source is input to the dmac through the select circuit. when transfer by an on-chip module interrupt is enabled (dtf1 = 1, dtf0 = 0, and dte = 1 in dmdr) and the dta bit in dmdr is set to 1, the interrupt source selected for the dm ac activation source is controlled by the dmac and cannot be used as a dtc activa tion source or cpu interrupt source. interrupt sources that are not controlled by the dmac are set for dtc activation sources or cpu interrupt sources by the dtce bit in dtcera to dtcerh of the dtc. specifying the disel bit in mrb of the dtc generates an interrupt request to the cpu by clearing the dtce bit to 0 after the individual dtc data transfer. note that when the dtc performs a predetermine d number of data transfers and the transfer counter indicates 0, an interrupt request is made to the cpu by clearing the dtce bit to 0 after the dtc data transfer. when the same interrupt source is set as both the dtc and dmac activation source and cpu interrupt source, the dtc and dmac must be given priority over the cpu. if the ipsete bit in cpupcr is set to 1, the priority is determined acc ording to the ipr settin g. therefore, the cpup setting or the ipr setting corresponding to the interrupt source must be set to lower than or equal to the dtcp and dmap setting. if the cpu is given priority over the dtc or dmac, the dtc or dmac may not be activated, and the data transfer may not be performed. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 139 of 1102 rej09b0365-0100 (2) priority determination the dtc activation source is select ed according to the default prio rity, and the selection is not affected by its mask level or priority level. for respective priority levels, see table 10.1, interrupt sources, dtc vector addresses, and corresponding dtces. (3) operation order if the same interrupt is selected as both the dtc activation sour ce and cpu interrupt source, the cpu interrupt exception handling is performed after th e dtc data transfer. if the same interrupt is selected as the dtc or dmac act ivation source or cpu interrupt source, respective operations are performed independently. table 6.6 lists the selection of interrupt sources and interrupt source clear control by setting the dta bit in dmdr of the dmac, the dtce bit in dtcera to dtcerh of the dtc, and the disel bit in mrb of the dtc. table 6.6 interrupt source se lection and clear control dmac setting dtc setting interrupt source selection/clear control dta dtce disel dmac dtc cpu 0 0 * o x 1 0 o x 1 o o 1 * * x x [legend] : the corresponding interrupt is used. the interrupt source is cleared. (the interrupt source flag must be cleared in the cpu interrupt handling routine.) o: the corresponding interrupt is used. the interrupt source is not cleared. x: the corresponding interrupt is not available. * : don't care. (4) usage note the interrupt sources of the sci, and a/d convert er are cleared according to the setting shown in table 6.6, when the dtc or dmac re ads/writes the prescribed register. to initiate multiple channels for the dtc with the same interrupt, the same priority (dtcp = dmap) should be assigned. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 140 of 1102 rej09b0365-0100 6.7 cpu priority control function over dtc and dmac the interrupt controller has a function to cont rol the priority among the dtc, dmac, and the cpu by assigning different priority levels to th e dtc, dmac, and cpu. since the priority level can automatically be assigned to the cpu on an in terrupt occurrence, it is possible to execute the cpu interrupt exception handling prior to the dtc or dmac transfer. the priority level of the cpu is assigned by b its cpup2 to cpup0 in cpupcr. the priority level of the dtc is assigned by bits dtcp2 to dtcp0 in cpupcr. the priority level of the dmac is assigned by bits dmap2 to dmap0 in dmdr for each channel. the priority control function over the dtc and dmac is enabled by setting the cpupce bit in cpupcr to 1. when the cpupce bit is 1, the dtc and dmac activation sources are controlled according to the respective priority levels. the dtc activation source is controlled according to the priority level of the cpu indicated by bits cpup2 to cpup0 and the priority level of th e dtc indicated by bits dtcp2 to dtcp0. if the cpu has priority, the dtc activation source is he ld. the dtc is activated when the condition by which the activation source is held is cancelled (cpupce = 1 and value of bits cpup2 to cpup0 is greater than that of bits dtcp2 to dtcp0). th e priority level of the dtc is assigned by the dtcp2 to dtcp0 bits regardless of the activation source. for the dmac, the priority level can be specif ied for each channel. th e dmac activation source is controlled according to the priority level of each dmac channel indicat ed by bits dmap2 to dmap0 and the priority level of the cpu. if the cpu has priority, the dmac activation source is held. the dmac is activated when the conditi on by which the activation source is held is cancelled (cpupce = 1 and value of bits cpup2 to cpup0 is greater than that of bits dmap2 to dmap0). if different priority levels are specified for channels, the channels of the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the cpu are held. there are two methods for assigning the priority level to the cpu by the ipsete bit in cpupcr. setting the ipsete bit to 1 enables a function to au tomatically assign the value of the interrupt mask bit of the cpu to the cpu priority level. clearin g the ipsete bit to 0 disables the function to automatically assign the priority level. theref ore, the priority level is assigned directly by software rewriting bits cpup2 to cpup0. even if the ipsete bit is 1, the priority level of the cpu is software assignable by rewriting the interrup t mask bit of the cpu (i bit in ccr or i2 to i0 bits in exr). section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 141 of 1102 rej09b0365-0100 the priority level which is automatically assigne d when the ipsete bit is 1 differs according to the interrupt control mode. in interrupt control mode 0, the i bit in ccr of the cpu is reflected in bit cpup2. bits cpup1 and cpup0 are fixed 0. in interrupt control mode 2, the values of bits i2 to i0 in exr of the cpu are reflected in bits cpup2 to cpup0. table 6.7 shows the cpu priority control. table 6.7 cpu priority control control status interrupt control mode interrupt priority interrupt mask bit ipsete in cpupcr cpup2 to cpup0 updating of cpup2 to cpup0 0 default i = any 0 b'111 to b'000 enabled i = 0 1 b'000 disabled i = 1 b'100 2 ipr setting i2 to i0 0 b'111 to b'000 enabled 1 i2 to i0 disabled section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 142 of 1102 rej09b0365-0100 table 6.8 shows a setting example of the priority control function over the dtc and dmac and the transfer request control state. a priority level can be independ ently set to each dmac channel, but the table only shows one channel for example. transfers through the dmac channels can be separately controlled by assigning different priority levels for channels. table 6.8 example of priority contro l function setting and control state transfer request control state interrupt control mode cpupce in cpupcr cpup2 to cpup0 dtcp2 to dtcp0 dmap2 to dmap0 dtc dmac 0 0 any any any enabled enabled 1 b'000 b'000 b'000 enabled enabled b'100 b'000 b'000 masked masked b'100 b'000 b'011 masked masked b'100 b'111 b'101 enabled enabled b'000 b'111 b'101 enabled enabled 2 0 any any any enabled enabled 1 b'000 b'000 b'000 enabled enabled b'000 b'011 b'101 enabled enabled b'011 b'011 b'101 enabled enabled b'100 b'011 b'101 masked enabled b'101 b'011 b'101 masked enabled b'110 b'011 b'101 masked masked b'111 b'011 b'101 masked masked b'101 b'011 b'101 masked enabled b'101 b'110 b'101 enabled enabled section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 143 of 1102 rej09b0365-0100 6.8 usage notes 6.8.1 conflict between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 6.7 shows an example in which the tciev bit in tier of the tpu is cleared to 0. the above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. internal address bus internal write signal p tciev tcfv tciv interrupt signal tier_0 write cycle by cpu tciv exception handling tier_0 address figure 6.7 conflict between int errupt generation and disabling similarly, when an interrupt is requested immediately before the dtc enable bit is changed to activate the dtc, dtc activation and the inte rrupt exception handling by the cpu are both executed. when changing the dtc enable bit, ma ke sure that an interrupt is not requested. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 144 of 1102 rej09b0365-0100 6.8.2 instructions th at disable interrupts instructions that disable interrupts immediat ely after execution are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always ex ecuted. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 6.8.3 times when interrupts are disabled there are times when interru pt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt accep tance for a 3-state period after the cpu has updated the mask level with an ldc, andc, o rc, or xorc instruction, and for a period of writing to the registers of the interrupt controller. 6.8.4 interrupts during execu tion of eepmov instruction interrupt operation differs between the eepmov.b and the eepmo v.w instructions. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the tr ansfer is completed. with the eepmov.w instruction, if an interrupt re quest is issued during the transfer, interrupt exception handling starts at the end of the individu al transfer cycle. the pc value saved on the stack in this case is the address of the next inst ruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 6.8.5 interrupts during execution of movmd and movs d instructions with the movmd or movsd instruction, if an in terrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. the pc value saved on the stack in this case is the address of the movmd or movsd instruction. the transfer of the remaining data is resumed after returning from the interrupt handling routine. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 145 of 1102 rej09b0365-0100 6.8.6 interrupts of peripheral modules to clear an interrupt source flag by the cpu using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. this makes the request signal synchronized with the peripheral module clock. for details, refer to section 23.5.1, notes on clock pulse generator. section 6 interrupt controller rev. 1.00 sep. 13, 2007 page 146 of 1102 rej09b0365-0100 section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 147 of 1102 rej09b0365-0100 section 7 user break controller (ubc) the user break controller (ubc) generates a ubc break interrupt request each time the state of the program counter matches a specified break condition. the ubc break interrupt is a non- maskable interrupt and is always accepted, regardle ss of the interrupt contro l mode and the state of the interrupt mask bit of the cpu. for each channel, the break control register (brcr) and break address register (bar) are used to specify the break condition as a combination of address bits and type of bus cycle. four break conditions are independently specifiable on four channels, a to d. 7.1 features ? number of break channels: four (channels a, b, c, and d) ? break comparison cond itions (each channel) ? address ? bus master (cpu cycle) ? bus cycle (instruction execution (pc break)) ? ubc break interrupt exception handling is executed immediately before execution of the instruction fetched from the specified address (pc break). ? module stop state can be set section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 148 of 1102 rej09b0365-0100 7.2 block diagram a ch pc condition match b ch pc condition match c ch pc condition match d ch pc condition match ubc break interrupt request break control mode control sequential control break address break control instruction execution pointer cpu status internal bus (input side) internal bus (output side) instruction execution pointer barah baral barbh barbl barch barcl bardh bardl brcra brcrb brcrc brcrd pc break control address comparator a ch condition match determination condition match determination condition match determination condition match determination address comparator b ch address comparator c ch address comparator d ch flag set control barah, baral: barbh, barbl: barch, barcl: bardh, bardl: brcra: brcrb: brcrc: brcrd: break address register a break address register b break address register c break address register d break control register a break control register b break control register c break control register d [legend] figure 7.1 block diagram of ubc section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 149 of 1102 rej09b0365-0100 7.3 register descriptions table 7.1 lists the register configuration of the ubc. table 7.1 register configuration register name abbreviation r/w initial value address access size barah r/w h'0000 h'ffa00 16 break address register a baral r/w h'0000 h'ffa02 16 bamrah r/w h'0000 h'ffa04 16 break address mask register a bamral r/w h'0000 h'ffa06 16 barbh r/w h'0000 h'ffa08 16 break address register b barbl r/w h'0000 h'ffa0a 16 bamrbh r/w h'0000 h'ffa0c 16 break address mask register b bamrbl r/w h'0000 h'ffa0e 16 barch r/w h'0000 h'ffa10 16 break address register c barcl r/w h'0000 h'ffa12 16 bamrch r/w h'0000 h'ffa14 16 break address mask register c bamrcl r/w h'0000 h'ffa16 16 bardh r/w h'0000 h'ffa18 16 break address register d bardl r/w h'0000 h'ffa1a 16 bamrdh r/w h'0000 h'ffa1c 16 break address mask register d bamrdl r/w h'0000 h'ffa1e 16 break control register a brcra r/w h'0000 h'ffa28 8/16 break control register b b rcrb r/w h'0000 h'ffa2c 8/16 break control register c brcrc r/w h'0000 h'ffa30 8/16 break control register d brcrd r/w h'0000 h'ffa34 8/16 section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 150 of 1102 rej09b0365-0100 7.3.1 break address register n (bara, barb, barc, bard) each break address register n (barn) consists of break address register nh (barnh) and break address register nl (barnl). together, barnh and barnl specify the address used as a break condition on channel n of the ubc. bit: initial value: r/w: bit: initial value: r/w: 31 barn31 0 r/w 30 barn30 0 r/w 29 barn29 0 r/w 28 barn28 0 r/w 27 barn27 0 r/w 24 barn24 0 r/w 26 barn26 0 r/w 25 barn25 0 r/w 23 barn23 0 r/w 22 barn22 0 r/w 21 barn21 0 r/w 20 barn20 0 r/w 19 barn19 0 r/w 16 barn16 0 r/w 18 barn18 0 r/w 17 barn17 0 r/w 15 barn15 0 r/w 14 barn14 0 r/w 13 barn13 0 r/w 12 barn12 0 r/w 11 barn11 0 r/w 8 barn8 0 r/w 10 barn10 0 r/w 9 barn9 0 r/w 7 barn7 0 r/w 6 barn6 0 r/w 5 barn5 0 r/w 4 barn4 0 r/w 3 barn3 0 r/w 0 barn0 0 r/w 2 barn2 0 r/w 1 barn1 0 r/w barnh barnl ? barnh bit bit name initial value r/w description 31 to 16 barn31 to barn16 all 0 r/w break address n31 to 16 these bits hold the upper bit values (bits 31 to 16) for the address break-condition on channel n. [legend] n = channels a to d ? barnl bit bit name initial value r/w description 15 to 0 barn15 to barn0 all 0 r/w break address n15 to 0 these bits hold the lower bit values (bits 15 to 0) for the address break-condition on channel n. [legend] n = channels a to d section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 151 of 1102 rej09b0365-0100 7.3.2 break address mask register n (bamra, ba mrb, bamrc, bamrd) be sure to write h'ff00 0000 to break address mask register n (bamrn). operation is not guaranteed if another value is written here. bit: initial value: r/w: bit: initial value: r/w: 31 bamrn31 0 r/w 30 bamrn30 0 r/w 29 bamrn29 0 r/w 28 bamrn28 0 r/w 27 bamrn27 0 r/w 24 bamrn24 0 r/w 26 bamrn26 0 r/w 25 bamrn25 0 r/w 23 bamrn23 0 r/w 22 bamrn22 0 r/w 21 bamrn21 0 r/w 20 bamrn20 0 r/w 19 bamrn19 0 r/w 16 bamrn16 0 r/w 18 bamrn18 0 r/w 17 bamrn17 0 r/w 15 bamrn15 0 r/w 14 bamrn14 0 r/w 13 bamrn13 0 r/w 12 bamrn12 0 r/w 11 bamrn11 0 r/w 8 bamrn8 0 r/w 10 bamrn10 0 r/w 9 bamrn9 0 r/w 7 bamrn7 0 r/w 6 bamrn6 0 r/w 5 bamrn5 0 r/w 4 bamrn4 0 r/w 3 bamrn3 0 r/w 0 bamrn0 0 r/w 2 bamrn2 0 r/w 1 bamrn1 0 r/w bamrnh bamrnl ? bamrnh bit bit name initial value r/w description 31 to 16 bamrn31 to bamrn16 all 0 r/w break address mask n31 to 16 be sure to write h'ff00 here before setting a break condition in the break control register. [legend] n = channels a to d ? bamrnl bit bit name initial value r/w description 15 to 0 bamrn15 to bamrn0 all 0 r/w break address mask n15 to 0 be sure to write h'0000 here before setting a break condition in the break control register. [legend] n = channels a to d section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 152 of 1102 rej09b0365-0100 7.3.3 break control register n (brcra, brcrb, brcrc, brcrd) brcra, brcrb, brcrc, and brcrd are used to specify and control conditions for channels a, b, c, and d of the ubc. bit: initial value: r/w: [legend] n = channels a to d 15 ? 0 r/w 14 ? 0 r/w 13 cmfcpn 0 r/w 12 ? 0 r/w 11 cpn2 0 r/w 8 ? 0 r/w 10 cpn1 0 r/w 9 cpn0 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 idn1 0 r/w 4 idn0 0 r/w 3 rwn1 0 r/w 0 ? 0 r/w 2 rwn0 0 r/w 1 ? 0 r/w bit bit name initial value r/w description 15 14 ? ? 0 0 r/w r/w reserved these bits are always read as 0. the write value should always be 0. 13 cmfcpn 0 r/w condition match cpu flag ubc break source flag that indicates satisfaction of a specified cpu bus cycle condition. 0: the cpu cycle condition for channel n break requests has not been satisfied. 1: the cpu cycle condition for channel n break requests has been satisfied. 12 ? 0 r/w reserved these bits are always read as 0. the write value should always be 0. 11 10 9 cpn2 cpn1 cpn0 0 0 0 r/w r/w r/w cpu cycle select these bits select cpu cycl es as the bus cycle break condition for the given channel. 000: break requests will not be generated. 001: the bus cycle break condition is cpu cycles. 01x: setting prohibited 1xx: setting prohibited 8 7 6 ? ? ? 0 0 0 r/w r/w r/w reserved these bits are always read as 0. the write value should always be 0. section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 153 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 4 idn1 idn0 0 0 r/w r/w break condition select these bits select the pc break as the source of ubc break interrupt requests for the given channel. 00: break requests will not be generated. 01: ubc break condition is the pc break. 1x: setting prohibited 3 2 rwn1 rwn0 0 0 r/w r/w read select these bits select read cycles as the bus cycle break condition for the given channel. 00: break requests will not be generated. 01: the bus cycle break condition is read cycles. 1x: setting prohibited 1 0 ? ? 0 0 r/w r/w reserved these bits are always read as 0. the write value should always be 0. [legend] n = channels a to d section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 154 of 1102 rej09b0365-0100 7.4 operation the ubc does not detect condition matches in standby states (sleep mode, all module clock stop mode, software standby mode, deep software standby, and hardware standby mode). 7.4.1 setting of break control conditions 1. the address condition for the break is set in break address register n (barn). a mask for the address is set in break address mask register n (bamrn). 2. the bus and break conditions are set in br eak control register n (brcrn). bus conditions consist of cpu cycle, pc break, and reading. condition comparison is not performed when the cpu cycle setting is cpn = b'000, the pc break setting is idn = b'00, or the read setting is rwn = b'00. 3. the condition match cpu flag (cmfcpn) is set in the event of a break condition match on the corresponding channel. these flags are set wh en the break condition matches but are not cleared when it no long er does. to confirm setting of the sa me flag again, read the flag once from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0 to it after reading it as 1). [legend] n = channels a to d 7.4.2 pc break 1. when specifying a pc break, speci fy the address as the first addres s of the required instruction. if the address for a pc break condition is not the first address of an instruction, a break will never be generated. 2. the break occurs after fetching and execution of the target instruction have been confirmed. in cases of contention between a break before instruction execution and a user maskable interrupt, priority is given to the break before instruction execution. 3. a break will not be generated even if a break be fore instruction execution is set in a delay slot. 4. the pc break condition is generated by specif ying cpu cycles as the bus condition in break control register n (brcrn.cpn0 = 1), pc break as the break condition (idn0 = 1), and read cycles as the bus-cycle condition (rwn0 = 1). [legend] n = channels a to d section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 155 of 1102 rej09b0365-0100 7.4.3 condition match flag condition match flags are set when the break conditions match. the condition match flags of the ubc are listed in table 7.2. table 7.2 list of condition match flags register flag bit source brcra cmfcpa (bit 13) indicates that t he condition matches in the cpu cycle for channel a brcrb cmfcpb (bit 13) indicates that t he condition matches in the cpu cycle for channel b brcrc cmfcpc (bit 13) indicates that t he condition matches in the cpu cycle for channel c brcrd cmfcpd (bit 13) indicates that t he condition matches in the cpu cycle for channel d section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 156 of 1102 rej09b0365-0100 7.5 usage notes 1. pc break usage note ? contention between a sleep instru ction (to place the chip in the sleep state or on software standby) and pc break if a break before a pc break instruction is se t for the instruction after a sleep instruction and the sleep instruction is executed with th e ssby bit cleared to 0, break interrupt exception handling is executed without sleep mode being entered. in this case, the instruction after the sleep instruction is executed after the rte instruction. when the ssby bit is set to 1, break interru pt exception handling is executed after the oscillation settling time has elapsed subsequent to the transition to software standby mode. when an interrupt is the canceling source, interrupt exception handling is executed after the rte instruction, and the instruction following the sleep instruction is then executed. sleep break interr upt exception handling interr upt exception handling software standby (pc break source ) (cancelling source ) cancelling source clk figure 7.2 contention between sleep inst ruction (software standby) and pc break 2. prohibition on setting of pc break ? setting of a ubc break interrupt for program within the ubc break interrupt handling routine is prohibited. 3. the procedure for clearing a ubc flag bit (condition match flag) is shown below. a flag bit is cleared by writing 0 to it after reading it as 1. as the register that cont ains the flag bits is accessible in byte units, bit manipulation instructions can be used. section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 157 of 1102 rej09b0365-0100 cks register read the value read as 1 is retained register write flag bit flag bit is set to 1 flag bit is cleared to 0 figure 7.3 flag bit clearing sequence (condition match flag) 4. after setting break conditions for the ubc, an unexpected ubc break interrupt may occur after the execution of an illegal instruction. this depends on the value of the program counter and the internal bus cycle. section 7 user break controller (ubc) rev. 1.00 sep. 13, 2007 page 158 of 1102 rej09b0365-0100 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 159 of 1102 rej09b0365-0100 section 8 bus controller (bsc) this lsi has an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters; cpu, dmac, and dtc. 8.1 features ? manages external address space in area units manages the external address space divided into eight areas chip select signals ( cs0 to cs7 ) can be output for each area bus specifications can be set independently for each area 8-bit access or 16-bit access can be selected for each area burst rom, byte control sram, or address/data multiplexed i/o interface can be set an endian conversion function is provid ed to connect a device of little endian ? basic bus interface this interface can be connect ed to the sram and rom 2-state access or 3-state access can be selected for each area program wait cycles can be inserted for each area wait cycles can be inserted by the wait pin. extension cycles can be inserted while csn is asserted for each area (n = 0 to 7) the negation timing of the read strobe signal ( rd ) can be modified ? byte control sram interface byte control sram interface can be set for areas 0 to 7 the sram that has a byte control pin can be directly connected ? burst rom interface burst rom interface can be set for areas 0 and 1 burst rom interface parameters can be set independently for areas 0 and 1 ? address/data multiplexed i/o interface address/data multiplexed i/o interf ace can be set for areas 3 to 7 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 160 of 1102 rej09b0365-0100 ? idle cycle insertion idle cycles can be inserted between ex ternal read accesses to different areas idle cycles can be inserted before the exte rnal write access after an external read access idle cycles can be inserted before the exte rnal read access after an external write access idle cycles can be inserted before the extern al access after a dmac si ngle address transfer (write access) ? write buffer function external write cycles and internal accesses can be executed in parallel write accesses to the on-chip pe ripheral module and on-chip memory accesses can be executed in parallel dmac single address transf ers and internal accesses can be executed in parallel ? external bus release function ? bus arbitration function includes a bus arbiter that arbitrates bus mastership among the cpu, dmac, dtc, and external bus master ? multi-clock function the internal peripheral functions can be operated in synchronization with the peripheral module clock (p ). accesses to the external address sp ace can be operated in synchronization with the external bus clock (b ). ? the bus start ( bs ) and read/write (rd/ wr ) signals can be output. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 161 of 1102 rej09b0365-0100 a block diagram of the bus controller is shown in figure 8.1. address selector area decoder internal bus control unit internal data bus [legend] internal bus control signals external bus control unit external bus arbiter internal bus arbiter cpu address bus cs7 to cs0 wait breq back breqo dtc address bus dmac address bus cpu bus mastership acknowledge signal dtc bus mastership acknowledge signal cpu bus mastership request signal dtc bus mastership request signal dmac bus mastership acknowledge signal dmac bus mastership request signal external bus control signals control register abwcr astcr wtcra wtcrb rdncr csacr idlcr bcr1 bcr2 endiancr sramcr bromcr mpxcr abwcr: astcr: wtcra: wtcrb: rdncr: csacr: bus width control register access state control register wait control register a wait control register b read strobe timing control register cs assertion period control register idlcr: bcr1: bcr2: endiancr: sramcr: bromcr: mpxcr: idle control register bus control register 1 bus control register 2 endian control register sram mode control register burst rom interface control register address/data multiplexed i/o control register figure 8.1 block diagram of bus controller section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 162 of 1102 rej09b0365-0100 8.2 register descriptions the bus controller has the following registers. ? bus width control register (abwcr) ? access state control register (astcr) ? wait control register a (wtcra) ? wait control register b (wtcrb) ? read strobe timing control register (rdncr) ? cs assertion period control register (csacr) ? idle control register (idlcr) ? bus control register 1 (bcr1) ? bus control register 2 (bcr2) ? endian control register (endiancr) ? sram mode control register (sramcr) ? burst rom interface contro l register (bromcr) ? address/data multiplexed i/o control register (mpxcr) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 163 of 1102 rej09b0365-0100 8.2.1 bus width control register (abwcr) abwcr specifies the data bus width for each area in the external address space. bit bit name initial value r/w 15 abwh7 1 r/w 14 abwh6 1 r/w 13 abwh5 1 r/w 12 abwh4 1 r/w 11 abwh3 1 r/w 10 abwh2 1 r/w 9 abwh1 1 r/w 8 abwh0 1/0 r/w bit bit name initial value r/w note: * initial value at 16-bit bus initiation is h'feff, and that at 8-bit bus initiation is h'ffff. 7 abwl7 1 r/w 6 abwl6 1 r/w 5 abwl5 1 r/w 4 abwl4 1 r/w 3 abwl3 1 r/w 2 abwl2 1 r/w 1 abwl1 1 r/w 0 abwl0 1 r/w bit bit name initial value * 1 r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 abwh7 abwh6 abwh5 abwh4 abwh3 abwh2 abwh1 abwl0 abwl7 abwl6 abwl5 abwl4 abwl3 abwl2 abwl1 abwl0 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w area 7 to 0 bus width control these bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. abwhn abwln (n = 7 to 0) x 0: setting prohibited 0 1: area n is designated as 16-bit access space 1 1: area n is designated as 8-bit access space * 2 [legend] x: don't care notes: 1. initial value at 16-bit bus initiation is h'feff, and that at 8-bit bus initiation is h'ffff. 2. an address space specified as byte contro l sram interface must not be specified as 8- bit access space. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 164 of 1102 rej09b0365-0100 8.2.2 access state control register (astcr) astcr designates each area in the external addres s space as either 2-st ate access space or 3-state access space and enables/disabl es wait cycle insertion. bit bit name initial value r/w 15 ast7 1 r/w 14 ast6 1 r/w 13 ast5 1 r/w 12 ast4 1 r/w 11 ast3 1 r/w 10 ast2 1 r/w 9 ast1 1 r/w 8 ast0 1 r/w bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 14 13 12 11 10 9 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w area 7 to 0 access state control these bits select whether the corresponding area is to be designated as 2-state acce ss space or 3-state access space. wait cycle insertion is enabled or disabled at the same time. 0: area n is designated as 2-state access space wait cycle insertion in area n access is disabled 1: area n is designated as 3-state access space wait cycle insertion in area n access is enabled (n = 7 to 0) 7 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 165 of 1102 rej09b0365-0100 8.2.3 wait control registers a and b (wtcra, wtcrb) wtcra and wtcrb select the number of program wait cycles for each area in the external address space. bit bit name initial value r/w 15 ? 0 r wtcra wtcrb 14 w72 1 r/w 13 w71 1 r/w 12 w70 1 r/w 11 ? 0 r 10 w62 1 r/w 9 w61 1 r/w 8 w60 1 r/w bit bit name initial value r/w 7 ? 0 r 6 w52 1 r/w 5 w51 1 r/w 4 w50 1 r/w 3 ? 0 r 2 w42 1 r/w 1 w41 1 r/w 0 w40 1 r/w bit bit name initial value r/w 15 ? 0 r 14 w32 1 r/w 13 w31 1 r/w 12 w30 1 r/w 11 ? 0 r 10 w22 1 r/w 9 w21 1 r/w 8 w20 1 r/w bit bit name initial value r/w 7 ? 0 r 6 w12 1 r/w 5 w11 1 r/w 4 w10 1 r/w 3 ? 0 r 2 w02 1 r/w 1 w01 1 r/w 0 w00 1 r/w section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 166 of 1102 rej09b0365-0100 ? wtcra bit bit name initial value r/w description 15 ? 0 r reserved this is a read-only bit and cannot be modified. 14 13 12 w72 w71 w70 1 1 1 r/w r/w r/w area 7 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 7 while bit ast7 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 ? 0 r reserved this is a read-only bit and cannot be modified. 10 9 8 w62 w61 w60 1 1 1 r/w r/w r/w area 6 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 6 while bit ast6 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 ? 0 r reserved this is a read-only bit and cannot be modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 167 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 5 4 w52 w51 w50 1 1 1 r/w r/w r/w area 5 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 5 while bit ast5 in astcr is 1. 000: program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 ? 0 r reserved this is a read-only bit and cannot be modified. 2 1 0 w42 w41 w40 1 1 1 r/w r/w r/w area 4 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 4 while bit ast4 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 168 of 1102 rej09b0365-0100 ? wtcrb bit bit name initial value r/w description 15 ? 0 r reserved this is a read-only bit and cannot be modified. 14 13 12 w32 w31 w30 1 1 1 r/w r/w r/w area 3 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 3 while bit ast3 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 ? 0 r reserved this is a read-only bit and cannot be modified. 10 9 8 w22 w21 w20 1 1 1 r/w r/w r/w area 2 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 2 while bit ast2 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 ? 0 r reserved this is a read-only bit and cannot be modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 169 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 5 4 w12 w11 w10 1 1 1 r/w r/w r/w area 1 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 1 while bit ast1 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 3 ? 0 r reserved this is a read-only bit and cannot be modified. 2 1 0 w02 w01 w00 1 1 1 r/w r/w r/w area 0 wait control 2 to 0 these bits select the number of program wait cycles when accessing area 0 while bit ast0 in astcr is 1. 000: program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 170 of 1102 rej09b0365-0100 8.2.4 read strobe timing control register (rdncr) rdncr selects the negation timing of the read strobe signal ( rd ) when reading the external address spaces specified as a ba sic bus interface or the address/ data multiplexed i/o interface. bit bit name initial value r/w 15 rdn7 0 r/w 14 rdn6 0 r/w 13 rdn5 0 r/w 12 rdn4 0 r/w 11 rdn3 0 r/w 10 rdn2 0 r/w 9 rdn1 0 r/w 8 rdn0 0 r/w bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 14 13 12 11 10 9 8 rdn7 rdn6 rdn5 rdn4 rdn3 rdn2 rdn1 rdn0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w read strobe timing control rdn7 to rdn0 set the negation timing of the read strobe in a corresponding area read access. as shown in figure 8.2, the read strobe for an area for which the rdnn bit is set to 1 is negated one half- cycle earlier than that for an area for which the rdnn bit is cleared to 0. the read data setup and hold time are also given one half-cycle earlier. 0: in an area n read access, the rd signal is negated at the end of the read cycle 1: in an area n read access, the rd signal is negated one half-cycle before t he end of the read cycle (n = 7 to 0) 7 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. notes: 1. in an external address space which is specified as byte control sram interface, the rdncr setting is ignored and the same operation when rdnn = 1 is performed. 2. in an external address space which is specified as burst rom interface, the rdncr setting is ignored during cpu read accesses and the same operation when rdnn = 0 is performed. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 171 of 1102 rej09b0365-0100 bus cycle t 1 t 2 rd b data rd data rdnn = 0 rdnn = 1 t 3 (n = 7 to 0) figure 8.2 read strobe negation timing (example of 3-state access space) 8.2.5 cs assertion period control registers (csacr) csacr selects whether or not the asserti on periods of the chip select signals ( csn ) and address signals for the basic bus, byte-control sram, burst rom, and address/data multiplexed i/o interface are to be extended. extend ing the assertion period of the csn and address signals allows the setup time and hold time of read strobe ( rd ) and write strobe ( lhwr / llwr ) to be assured and to make the write data setup time and hol d time for the write strobe become flexible. bit bit name initial value r/w 15 csxh7 0 r/w 14 csxh6 0 r/w 13 csxh5 0 r/w 12 csxh4 0 r/w 11 csxh3 0 r/w 10 csxh2 0 r/w 9 csxh1 0 r/w 8 csxh0 0 r/w bit bit name initial value r/w 7 csxt7 0 r/w 6 csxt6 0 r/w 5 csxt5 0 r/w 4 csxt4 0 r/w 3 csxt3 0 r/w 2 csxt2 0 r/w 1 csxt1 0 r/w 0 csxt0 0 r/w section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 172 of 1102 rej09b0365-0100 bit bit name initial value r/w description 15 14 13 12 11 10 9 8 csxh7 csxh6 csxh5 csxh4 csxh3 csxh2 csxh1 csxh0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w cs and address signal assertion period control 1 these bits specify whether or not the th cycle is to be inserted (see figure 8.3). when an area for which bit csxhn is set to 1 is accessed, one th cycle, in which the csn and address signals are asserted, is inserted before the normal access cycle. 0: in access to area n, the csn and address assertion period (th) is not extended 1: in access to area n, the csn and address assertion period (th) is extended (n = 7 to 0) 7 6 5 4 3 2 1 0 csxt7 csxt6 csxt5 csxt4 csxt3 csxt2 csxt1 csxt0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w cs and address signal assertion period control 2 these bits specify whether or not the tt cycle is to be inserted (see figure 8.3). when an area for which bit csxtn is set to 1 is accessed, one tt cycle, in which the csn and address signals are retained, is inserted after the normal access cycle. 0: in access to area n, the csn and address assertion period (tt) is not extended 1: in access to area n, the csn and address assertion period (tt) is extended (n = 7 to 0) note: * in burst rom interface, the csxtn setti ngs are ignored during cpu read accesses. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 173 of 1102 rej09b0365-0100 read data write data bus cycle t h t 1 t 2 t 3 t t b address csn as bs rd/ wr rd read write data bus data bus lhwr , llwr figure 8.3 cs and address assertio n period extension (example of basic bus interface, 3-state access space, and rdnn = 0) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 174 of 1102 rej09b0365-0100 8.2.6 idle control register (idlcr) idlcr specifies the idle cycle insertion c onditions and the number of idle cycles. bit bit name initial value r/w 15 idls3 1 r/w 14 idls2 1 r/w 13 idls1 1 r/w 12 idls0 1 r/w 11 idlcb1 1 r/w 10 idlcb0 1 r/w 9 idlca1 1 r/w 8 idlca0 1 r/w bit bit name initial value r/w 7 idlsel7 0 r/w 6 idlsel6 0 r/w 5 idlsel5 0 r/w 4 idlsel4 0 r/w 3 idlsel3 0 r/w 2 idlsel2 0 r/w 1 idlsel1 0 r/w 0 idlsel0 0 r/w bit bit name initial value r/w description 15 idls3 1 r/w idle cycle insertion 3 inserts an idle cycle between the bus cycles when the dmac single address transfer (write cycle) is followed by external access. 0: no idle cycle is inserted 1: an idle cycle is inserted 14 idls2 1 r/w idle cycle insertion 2 inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle. 0: no idle cycle is inserted 1: an idle cycle is inserted 13 idls1 1 r/w idle cycle insertion 1 inserts an idle cycle between the bus cycles when the external read cycles of different areas continue. 0: no idle cycle is inserted 1: an idle cycle is inserted section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 175 of 1102 rej09b0365-0100 bit bit name initial value r/w description 12 idls0 1 r/w idle cycle insertion 0 inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle. 0: no idle cycle is inserted 1: an idle cycle is inserted 11 10 idlcb1 idlcb0 1 1 r/w r/w idle cycle state number select b specifies the number of idle cycles to be inserted for the idle condition specified by idls1 and idls0. 00: no idle cycle is inserted 01: 2 idle cycles are inserted 00: 3 idle cycles are inserted 01: 4 idle cycles are inserted 9 8 idlca1 idlca0 1 1 r/w r/w idle cycle state number select a specifies the number of idle cycles to be inserted for the idle condition specified by idls3 to idls0. 00: 1 idle cycle is inserted 01: 2 idle cycles are inserted 10: 3 idle cycles are inserted 11: 4 idle cycles are inserted 7 6 5 4 3 2 1 0 idlsel7 idlsel6 idlsel5 idlsel4 idlsel3 idlsel2 idlsel1 idlsel0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w idle cycle number select specifies the number of idle cycles to be inserted for each area for the idle insert ion condition specified by idls1 and idls0. 0: number of idle cycles to be inserted for area n is specified by idlca1 and idlca0. 1: number of idle cycles to be inserted for area n is specified by idlcb1 and idlcb0. (n = 7 to 0) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 176 of 1102 rej09b0365-0100 8.2.7 bus control register 1 (bcr1) bcr1 is used for selection of the external bus released state protocol, enabling/disabling of the write data buffer function, and enabling/disabling of the wait pin input. bit bit name initial value r/w 15 brle 0 r/w 14 breqoe 0 r/w 13 ? 0 r 12 ? 0 r 11 ? 0 r/w 10 ? 0 r/w 9 wdbe 0 r/w 8 waite 0 r/w bit bit name initial value r/w 7 dkc 0 r/w 6 ? 0 r/w 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 brle 0 r/w external bus release enable enables/disables external bus release. 0: external bus release disabled breq , back , and breqo pins can be used as i/o ports 1: external bus release enabled for details, see section 11, i/o ports. 14 breqoe 0 r/w breqo pin enable controls outputting the bus request signal ( breqo ) to the external bus master in the external bus released state when an internal bus master performs an external address space access. 0: breqo output disabled breqo pin can be used as i/o port 1: breqo output enabled section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 177 of 1102 rej09b0365-0100 bit bit name initial value r/w description 13, 12 ? all 0 r reserved these are read-only bits and cannot be modified. 11, 10 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 9 wdbe 0 r/w write data buffer enable the write data buffer function can be used for an external write cycle and a dmac single address transfer cycle. the changed setting may not affect an external access immediately after the change. 0: write data buffer function not used 1: write data buffer function used 8 waite 0 r/w wait pin enable selects enabling/disabling of wait input by the wait pin. 0: wait input by wait pin disabled wait pin can be used as i/o port 1: wait input by wait pin enabled for details, see section 11, i/o ports. 7 dkc 0 r/w dack control selects the timing of dmac transfer acknowledge signal assertion. 0: dack signal is asserted at the b falling edge 1: dack signal is asserted at the b rising edge 6 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 5 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. note: when external bus release is enabled or input by the wait pin is enabled, make sure to set the icr bit to 1. for details , see section 11, i/o ports. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 178 of 1102 rej09b0365-0100 8.2.8 bus control register 2 (bcr2) bcr2 is used for bus arbitration control of the cpu, dmac, and dtc, and enabling/disabling of the write data buffer function to the peripheral modules. bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r/w 4 ibccs 0 r/w 3 ? 0 r 2 ? 0 r 1 ? 1 r/w 0 pwdbe 0 r/w bit bit name initial value r/w description 7, 6 ? all 0 r reserved these are read-only bits and cannot be modified. 5 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 4 ibccs 0 r/w internal bus cycle control select selects the internal bus arbiter function. 0: releases the bus mastership according to the priority 1: executes the bus cycles alternatively when a cpu bus mastership request conflicts with a dmac or dtc bus mastership request 3, 2 ? all 0 r reserved these are read-only bits and cannot be modified. 1 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 0 pwdbe 0 r/w peripheral module write data buffer enable specifies whether or not to use the write data buffer function for the peripher al module write cycles. 0: write data buffer function not used 1: write data buffer function used section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 179 of 1102 rej09b0365-0100 8.2.9 endian control register (endiancr) endiancr selects the endian format for each area of the external address space. though the data format of this lsi is big endian, data can be transferred in the little endian format during external address space access. note that the data format for the areas used as a program area or a stack area should be big endian. bit bit name initial value r/w 7 le7 0 r/w 6 le6 0 r/w 5 le5 0 r/w 4 le4 0 r/w 3 le3 0 r/w 2 le2 0 r/w 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 7 6 5 4 3 2 le7 le6 le5 le4 le3 le2 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w little endian select selects the endian for the corresponding area. 0: data format of area n is specified as big endian 1: data format of area n is specified as little endian (n = 7 to 2) 1, 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 180 of 1102 rej09b0365-0100 8.2.10 sram mode control register (sramcr) sramcr specifies the bus interface of each area in the external address space as a basic bus interface or a byte co ntrol sram interface. in areas specified as 8-bit access space by abw cr, the sramcr setting is ignored and the byte control sram interface cannot be specified. bit bit name initial value r/w 15 bcsel7 0 r/w 14 bcsel6 0 r/w 13 bcsel5 0 r/w 12 bcsel4 0 r/w 11 bcsel3 0 r/w 10 bcsel2 0 r/w 9 bcsel1 0 r/w 8 bcsel0 0 r/w bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w description 15 14 13 12 11 10 9 8 bcsel7 bcsel6 bcsel5 bcsel4 bcsel3 bcsel2 bcsel1 bcsel0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w byte control sram interface select selects the bus interface for the corresponding area. when setting a bit to 1, the bus interface select bits in bromcr and mpxcr must be cleared to 0. 0: area n is basic bus interface 1: area n is byte control sram interface (n = 7 to 0) 7 to 0 ? all 0 r reserved these are read-only bits and cannot be modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 181 of 1102 rej09b0365-0100 8.2.11 burst rom interface control register (bromcr) bromcr specifies the burst rom interface. bit bit name initial value r/w 15 bsrm0 0 r/w 14 bsts02 0 r/w 13 bsts01 0 r/w 12 bsts00 0 r/w 11 ? 0 r 10 ? 0 r 9 bswd01 0 r/w 8 bswd00 0 r/w bit bit name initial value r/w 7 bsrm1 0 r/w 6 bsts12 0 r/w 5 bsts11 0 r/w 4 bsts10 0 r/w 3 ? 0 r 2 ? 0 r 1 bswd11 0 r/w 0 bswd10 0 r/w bit bit name initial value r/w description 15 bsrm0 0 r/w area 0 burst rom interface select specifies the area 0 bus interface. to set this bit to 1, clear bit bcsel0 in sramcr to 0. 0: basic bus interface or byte-control sram interface 1: burst rom interface 14 13 12 bsts02 bsts01 bsts00 0 0 0 r/w r/w r/w area 0 burst cycle select specifies the number of burst cycles of area 0 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 11, 10 ? all 0 r reserved these are read-only bits and cannot be modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 182 of 1102 rej09b0365-0100 bit bit name initial value r/w description 9 8 bswd01 bswd00 0 0 r/w r/w area 0 burst word number select selects the number of words in burst access to the area 0 burst rom interface 00: up to 4 words (8 bytes) 01: up to 8 words (16 bytes) 10: up to 16 words (32 bytes) 11: up to 32 words (64 bytes) 7 bsrm1 0 r/w area 1 burst rom interface select specifies the area 1 bus inte rface as a basic interface or a burst rom interface. to set this bit to 1, clear bit bcsel1 in sramcr to 0. 0: basic bus interface or byte-control sram interface 1: burst rom interface 6 5 4 bsts12 bsts11 bsts10 0 0 0 r/w r/w r/w area 1 burst cycle select specifies the number of cycles of area 1 burst cycle 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles 3, 2 ? all 0 r reserved these are read-only bits and cannot be modified. 1 0 bswd11 bswd10 0 0 r/w r/w area 1 burst word number select selects the number of words in burst access to the area 1 burst rom interface 00: up to 4 words (8 bytes) 01: up to 8 words (16 bytes) 10: up to 16 words (32 bytes) 11: up to 32 words (64 bytes) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 183 of 1102 rej09b0365-0100 8.2.12 address/data multiplexed i/o control register (mpxcr) mpxcr specifies the address/data multiplexed i/o interface. bit bit name initial value r/w 15 mpxe7 0 r/w 14 mpxe6 0 r/w 13 mpxe5 0 r/w 12 mpxe4 0 r/w 11 mpxe3 0 r/w 10 ? 0 r 9 ? 0 r 8 ? 0 r bit bit name initial value r/w 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 addex 0 r/w bit bit name initial value r/w description 15 14 13 12 11 mpxe7 mpxe6 mpxe5 mpxe4 mpxe3 0 0 0 0 0 r/w r/w r/w r/w r/w address/data multiplex ed i/o interface select specifies the bus interface for the corresponding area. to set this bit to 1, clear the bcseln bit in sramcr to 0. 0: area n is specified as a basic interface or a byte control sram interface. 1: area n is specified as an address/data multiplexed i/o interface (n = 7 to 3) 10 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 addex 0 r/w address output cycle extension specifies whether a wait cycle is inserted for the address output cycle of addr ess/data multiplexed i/o interface. 0: no wait cycle is inserted for the address output cycle 1: one wait cycle is inse rted for the address output cycle section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 184 of 1102 rej09b0365-0100 8.3 bus configuration figure 8.4 shows the internal bus configuration of this lsi. the internal bus of this lsi consists of the following three types. ? internal system bus a bus that connects the cpu, dtc, dmac, on-chip ram, on-chip rom, internal peripheral bus, and external access bus. ? internal peripheral bus a bus that accesses registers in the bus cont roller, interrupt controller, and dmac, and registers of peripheral modules such as sci and timer. ? external access cycle a bus that accesses external devices via the external bus interface. cpu dtc b synchronization p synchronization i synchronization bus controller, interrupt controller, power-down controller external bus interface peripheral functions on-chip ram internal system bus on-chip rom internal peripheral bus write data buffer write data buffer external access bus dmac figure 8.4 internal bus configuration section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 185 of 1102 rej09b0365-0100 8.4 multi-clock function and number of access cycles the internal functions of th is lsi operate synchronousl y with the system clock (i ), the peripheral module clock (p ), or the external bus clock (b ). table 8.1 shows the synchronization clock and their corresponding functions. table 8.1 synchronization clocks and their corresponding functions synchronization clock function name i mcu operating mode interrupt controller bus controller cpu dtc dmac internal memory clock pulse generator power down control p i/o ports tpu ppg tmr wdt sci a/d d/a iic2 b external bus interface the frequency of each synchronization clock (i , p , and b ) is specified by the system clock control register (sckcr) independently. for further details, see section 23, clock pulse generator. there will be cases when p and b are equal to i and when p and b are different from i according to the sckcr specificati ons. in any case, access cycles for internal peripheral functions and external space is perfor med synchronously with p and b , respectively. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 186 of 1102 rej09b0365-0100 for example, in an external address sp ace access where the frequency rate of i and b is n : 1, the operation is performed in synchronization with b . in this case, external 2-state access space is 2n cycles and external 3-state acce ss space is 3n cycles (no wait cycl es is inserted) if the number of access cycles is counted based on i . if the frequencies of i , p and b are different, the start of bu s cycle may not synchronize with p or b according to the bus cycle in itiation timing. in this case, clock synchronization cycle (tsy) is inserted at the beginning of each bus cycle. for example, if an external address space access occurs when the frequency rate of i and b is n : 1, 0 to n-1 cycles of tsy may be inserted. if an internal peripheral module access occurs when the frequency rate of i and p is m : 1, 0 to m-1 cycles of tsy may be inserted. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 187 of 1102 rej09b0365-0100 figure 8.5 shows the external 2-state acce ss timing when the frequency rate of i and b is 4 : 1. figure 8.6 shows the external 3-state acce ss timing when the frequency rate of i and b is 2 : 1. divided clock synchronization cycle t 1 address i b as csn rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 read lhwr llwr write t 2 t sy bs rd/ wr figure 8.5 system clock: external bus clock = 4:1, external 2-state access section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 188 of 1102 rej09b0365-0100 divided clock synchronization cycle t 1 address i b as csn rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 read lhwr llwr write t 2 t sy t 3 bs rd/ wr figure 8.6 system clock: external bus clock = 2:1, external 3-state access section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 189 of 1102 rej09b0365-0100 8.5 external bus 8.5.1 input/output pins table 8.2 shows the pin configuration of the bus controller and table 8.3 shows the pin functions on each interface. table 8.2 pin configuration name symbol i/o function bus cycle start bs output signal indicating that the bus cycle has started address strobe/ address hold as / ah output ? strobe signal indicating that the basic bus, byte control sram, or burst rom space is accessed and address output on address bus is enabled ? signal to hold the address during access to the address/data multiplexed i/o interface read strobe rd output strobe signal indicating that the basic bus, byte control sram, burst rom, or address/data multiplexed i/o space is being read read/write rd/ wr output ? signal indicating the input or output direction ? write enable signal of the sram during access to the byte control sram space low-high write/ lower-upper byte select lhwr / lub output ? strobe signal indicating that the basic bus, burst rom, or address/data mu ltiplexed i/o space is written to, and the upper byte (d15 to d8) of data bus is enabled ? strobe signal indicating that the byte control sram space is accessed, and the upper byte (d15 to d8) of data bus is enabled low-low write/ lower-lower byte select llwr / llb output ? strobe signal indicating that the basic bus, burst rom, or address/data mu ltiplexed i/o space is written to, and the lower byte (d7 to d0) of data bus is enabled ? strobe signal indicating that the byte control sram space is accessed, and the lower byte (d7 to d0) of data bus is enabled section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 190 of 1102 rej09b0365-0100 name symbol i/o function chip select 0 cs0 output strobe signal indica ting that area 0 is selected chip select 1 cs1 output strobe signal indicati ng that area 1 is selected chip select 2 cs2 output strobe signal indicati ng that area 2 is selected chip select 3 cs3 output strobe signal indicati ng that area 3 is selected chip select 4 cs4 output strobe signal indicati ng that area 4 is selected chip select 5 cs5 output strobe signal indicati ng that area 5 is selected chip select 6 cs6 output strobe signal indicati ng that area 6 is selected chip select 7 cs7 output strobe signal indicati ng that area 7 is selected wait wait input wait request signal when accessing external address space. bus request breq input request signal for release of bus to external bus master bus request acknowledge back output acknowledge signal indicating that bus has been released to external bus master bus request output breqo output external bus request signal used when internal bus master accesses external address space in the external-bus released state data transfer acknowledge 3 (dmac_3) dack3 output data transfer acknowledge signal for dmac_3 single address transfer data transfer acknowledge 2 (dmac_2) dack2 output data transfer acknowledge signal for dmac_2 single address transfer data transfer acknowledge 1 (dmac_1) dack1 output data transfer acknowledge signal for dmac_1 single address transfer data transfer acknowledge 0 (dmac_0) dack0 output data transfer acknowledge signal for dmac_0 single address transfer external bus clock b output external bus clock section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 191 of 1102 rej09b0365-0100 table 8.3 pin functions in each interface initial state basic bus byte control sram burst rom address/data multiplexed i/o pin name 16 8 single- chip 16 8 16 16 8 16 8 remarks b output output ? o o o o o o o cs0 output output ? o o o o o ? ? cs1 ? ? ? o o o o o ? ? cs2 ? ? ? o o o ? ? ? ? cs3 ? ? ? o o o ? ? o o cs4 ? ? ? o o o ? ? o o cs5 ? ? ? o o o ? ? o o cs6 ? ? ? o o o ? ? o o cs7 ? ? ? o o o ? ? o o bs ? ? ? o o o o o o o rd/ wr ? ? ? o o o o o o o as output output ? o o o o o ? ? ah ? ? ? ? ? ? ? ? o o rd output output ? o o o o o o o lhwr / lub output output ? o ? o o ? o ? llwr / llb output output ? o o o o o o o wait ? ? ? o o o o o o o controlled by waite [legend] o: used as a bus control signal ? : not used as a bus control signal (used as a port input when initialized) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 192 of 1102 rej09b0365-0100 8.5.2 area division the bus controller divides the 16-mbyte address sp ace into eight areas, and performs bus control for the external address space in ar ea units. chip select signals ( cs0 to cs7 ) can be output for each area. figure 8.7 shows an area division of the 16-mbyte address space. for details on address map, see section 3, mcu operating modes. 16-mbyte space area 0 (2 mbytes) area 1 (2 mbytes) area 2 (8 mbytes) area 3 (2 mbytes) area 4 (1 mbyte) area 5 (1 mbyte ? 8 kbytes) area 6 (8 kbytes ? 256 bytes) area 7 (256 bytes) h'000000 h'1fffff h'200000 h'3fffff h'400000 h'bfffff h'c00000 h'dfffff h'e00000 h'efffff h'f00000 h'ffdfff h'ffe000 h'fffeff h'ffff00 h'ffffff figure 8.7 address space area division section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 193 of 1102 rej09b0365-0100 8.5.3 chip select signals this lsi can output chip select signals ( cs0 to cs7 ) for areas 0 to 7. the signal outputs low when the corresponding external address space area is accessed. figure 8.8 shows an example of csn (n = 0 to 7) signal output timing. enabling or disabling of csn signal output is set by the port function control register (pfcr). for details, see section 11.3, port function controller. in on-chip rom disabled extended mode, pin cs0 is placed in the output state after a reset. pins cs1 to cs7 are placed in the input state after a reset and so the correspond ing pfcr bits should be set to 1 when outputting signals cs1 to cs7 . in on-chip rom enabled extended mode, pins cs0 to cs7 are all placed in the input state after a reset and so the corresponding pfcr bits should be set to 1 when outputting signals cs0 to cs7 . the pfcr can specify multiple cs outputs for a pin. if multiple csn outputs are specified for a single pin by the pfcr, cs to be output are generated by mixing all the cs signals. in this case, the settings for the external bus interface areas in which the csn signals are output to a single pin should be the same. figure 8.9 shows the signal output timing when the cs signals to be output to areas 5 and 6 are output to the same pin. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 194 of 1102 rej09b0365-0100 16-mbyte space area 0 (2 mbytes) area 1 (2 mbytes) area 2 (8 mbytes) area 3 (2 mbytes) area 4 (1 mbyte) area 5 (1 mbyte ? 8 kbytes) area 6 (8 kbytes ? 256 bytes) area 7 (256 bytes) h'000000 h'1fffff h'200000 h'3fffff h'400000 h'bfffff h'c00000 h'dfffff h'e00000 h'efffff h'f00000 h'ffdfff h'ffe000 h'fffeff h'ffff00 h'ffffff figure 8.8 csn signal output timing (n = 0 to 7) output waveform b area 5 access cs6 cs5 area 6 access area 5 access area 6 access address bus figure 8.9 timing when cs signal is output to the same pin section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 195 of 1102 rej09b0365-0100 8.5.4 external bus interface the type of the external bus in terfaces, bus width, endian form at, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space. the bus width and the number of access cycles fo r both on-chip memory and intern al i/o registers are fixed, and are not affected by the external bus settings. (1) type of external bus interface four types of external bus interfaces are provid ed and can be selected in area units. table 8.4 shows each interface name, description, area name to be set for each interface. table 8.5 shows the areas that can be specified for each interface. the initial state of each area is a basic bus interface. table 8.4 interface names and area names interface description area name basic interface directly connected to rom and ram basic bus space byte control sram interface directly connected to byte sram with byte control pin byte control sram space burst rom interface directly connected to the rom that allows page access burst rom space address/data multiplexed i/o interface directly connected to the peripheral lsi that requires address and data multiplexing address/data multiplexed i/o space table 8.5 areas specifiab le for each interface areas interface related registers 0 1 2 3 4 5 6 7 basic interface o o o o o o o o byte control sram interface sramcr o o o o o o o o burst rom interface bromcr o o ? ? ? ? ? ? address/data multiplexed i/o interface mpxcr ? ? ? o o o o o (2) bus width a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space and an ar ea for which a 16-bit bus is selected functions section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 196 of 1102 rej09b0365-0100 as a 16-bit access space. in addition, the bus width of address/data multiplexed i/o space is 8 bits or 16 bits, and the bus width for the byte control sram space is 16 bits. the initial state of the bus width is specified by the operating mode. if all areas are designated as 8-bit access space, 8-b it bus mode is set; if any area is designated as 16-bit access space, 16-b it bus mode is set. (3) endian format though the endian format of this lsi is big endian, data can be converted into little endian format when reading or writing to the external address space. areas 7 to 2 can be specified as either big endian or little endian format by the le7 to le2 bits in endiancr. the initial state of each area is the big endian format. note that the data format for the areas used as a program area or a stack area should be big endian. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 197 of 1102 rej09b0365-0100 (4) number of access cycles (a) basic bus interface the number of access cycles in the basic bus interface can be specifi ed as two or three cycles by the astcr. an area specified as 2-state acce ss is specified as 2-state access space; an area specified as 3-state access is sp ecified as 3-state access space. for the 2-state access space, a wait cycle insertio n is disabled. for the 3-state access space, a program wait (0 to 7 cycles) specified by wtcra and wtcrb or an external wait by wait can be inserted. number of access cycles in the basic bus interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1, 2) [+ number of external wait cycles by the wait pin] assertion period of the chip select signal can be extended by csacr. (b) byte control sram interface the number of access cycles in th e byte control sram interface is the same as that in the basic bus interface. number of access cycles in byte control sram interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1, 2) [+ number of external wait cycles by the wait pin] (c) burst rom interface the number of access cycles at fu ll access in the burst rom interface is the same as that in the basic bus interface. the number of access cycles in the burst access can be specified as one to eight cycles by the bsts bit in bromcr. number of access cycles in the burst rom interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1) [+number of external wait cycles by the wait pin] + number of burst access cycles (1 to 8) number of burst accesses (0 to 63) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 198 of 1102 rej09b0365-0100 (d) address/data multiplexed i/o interface the number of access cycles in da ta cycle of the address/data multiplexed i/o interface is the same as that in the basic bus interface. the nu mber of access cycles in address cycle can be specified as two or three cycles by the addex bit in mpxcr. number of access cycles in the addr ess/data multiplexed i/o interface = number of address output cycles (2, 3) + number of data output cycles (2, 3) + number of program wait cycles (0 to 7) + number of cs extension cycles (0, 1, 2) [+number of external wait cycles by the wait pin] table 8.6 lists the number of access cycles for each interface. table 8.6 number of access cycles = = = = = = = tma [2,3] = tma [2,3] th [0,1] th [0,1] th [0,1] th [0,1] th [0,1] th [0,1] +th [0,1] +th [0,1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t1 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +t2 [1] +tt [0,1] +tt [0,1] +tt [0,1] +tt [0,1] +tt [0,1] +tt [0,1] [2 to 4] [3 to 12 + n] [2 to 4] [3 to 12 + n] [(2 to 3) + (1 to 8) m] [(2 to 11 + n) + (1 to 8) m] [4 to 7] [5 to 15 + n] +tpw [0 to 7] +tpw [0 to 7] +tpw [0 to 7] +tpw [0 to 7] +ttw [n] +ttw [n] +ttw [n] +ttw [n] +t3 [1] +t3 [1] +t3 [1] +t3 [1] basic bus interface byte control sram interface burst rom interface address/data multiplexed i/o interface +tb [(1 to 8) m] +tb [(1 to 8) m] [legend] numbers: number of access cycles n: pin wait (0 to ) m: number of burst accesses (0 to 63) (5) strobe assert/negate timings the assert and negate timings of the strobe signals can be modified as we ll as number of access cycles. ? read strobe ( rd ) in the basic bus interface ? chip select assertion period extens ion cycles in the basic bus interface ? data transfer acknowledge ( dack3 to dack0 ) output for dmac single address transfers section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 199 of 1102 rej09b0365-0100 8.5.5 area and extern al bus interface (1) area 0 area 0 includes on-chip rom. a ll of area 0 is used as extern al address space in on-chip rom disabled extended mode, and the space excludin g on-chip rom is external address space in on- chip rom enabled extended mode. when area 0 external address space is accessed, the cs0 signal can be output. either of the basic bus interface, byte contro l sram interface, or burst rom interface can be selected for area 0 by bit bsrm0 in bromcr and bit bcsel0 in sramcr. table 8.7 shows the external interface of area 0. table 8.7 area 0 ex ternal interface register setting interface bsrm0 of bromcr bcsel0 of sramcr basic bus interface 0 0 byte control sram interface 0 1 burst rom interface 1 0 setting prohibited 1 1 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 200 of 1102 rej09b0365-0100 (2) area 1 in externally extended mode, all of area 1 is external address space. in on-chip rom enabled extended mode, the space excluding on-ch ip rom is external address space. when area 1 external address space is accessed, the cs1 signal can be output. either of the basic bus interface, byte control sram, or burst ro m interface can be selected for area 1 by bit bsrm1 in bromcr and bit bcsel1 in sramcr. table 8.8 shows the external interface of area 1. table 8.8 area 1 ex ternal interface register setting interface bsrm1 of bromcr bcsel1 of sramcr basic bus interface 0 0 byte control sram interface 0 1 burst rom interface 1 0 setting prohibited 1 1 (3) area 2 in externally extended mode, all of area 2 is external address space. when area 2 external address space is accessed, the cs2 signal can be output. either the basic bus interface or byte control sr am interface can be selected for area 2 by bit bcsel2 in sramcr. table 8.9 shows th e external interf ace of area 2. table 8.9 area 2 ex ternal interface register setting interface bcsel2 of sramcr basic bus interface 0 byte control sram interface 1 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 201 of 1102 rej09b0365-0100 (4) area 3 in externally extended mode, all of area 3 is external address space. when area 3 external address space is accessed, the cs3 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 3 by bit mpxe3 in mpxcr and bit bcsel3 in sramcr. table 8.10 shows the external interface of area 3. table 8.10 area 3 external interface register setting interface mpxe3 of mpxcr bcsel3 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 (5) area 4 in externally extended mode, all of area 4 is external address space. when area 4 external address space is accessed, the cs4 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 4 by bit mpxe4 in mpxcr and bit bcsel4 in sramcr. table 8.11 shows the external interface of area 4. table 8.11 area 4 external interface register setting interface mpxe4 of mpxcr bcsel4 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 202 of 1102 rej09b0365-0100 (6) area 5 area 5 includes the on-chip ra m and access prohibited sp aces. in external extended mode, area 5, other than the on-chip ram and access prohibited spaces, is external address space. note that the on-chip ram is enabled when the rame bit in syscr are set to 1. if the rame bit in syscr is cleared to 0, the on- chip ram is disabled and the corresponding addresses are an external address space. for details, s ee section 3, mcu operating modes. when area 5 external address space is accessed, the cs5 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 5 by the mpxe5 bit in mpxcr and the bcsel5 bit in sramcr. table 8.12 shows the external interface of area 5. table 8.12 area 5 external interface register setting interface mpxe5 of mpxcr bcsel5 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 203 of 1102 rej09b0365-0100 (7) area 6 area 6 includes internal i/o regi sters. in external extended mo de, area 6 other than on-chip i/o register area is external address space. when area 6 external address space is accessed, the cs6 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 6 by the mpxe6 bit in mpxcr and the bcsel6 bit in sramcr. table 8.13 shows the external interface of area 6. table 8.13 area 6 external interface register setting interface mpxe6 of mpxcr bcsel6 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 (8) area 7 area 7 includes internal i/o regi sters. in external extended mode , area 7 other than internal i/o register area is external address space. when area 7 external address space is accessed, the cs7 signal can be output. either of the basic bus interface, byte control sram interface, or address/data multiplexed i/o interface can be selected for area 7 by the mpxe7 bit in mpxcr and the bcsel7 bit in sramcr. table 8.14 shows the external interface of area 7. table 8.14 area 7 external interface register setting interface mpxe7 of mpxcr bcsel7 of sramcr basic bus interface 0 0 byte control sram interface 0 1 address/data multiplexed i/o interface 1 0 setting prohibited 1 1 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 204 of 1102 rej09b0365-0100 8.5.6 endian and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and contro ls whether the upper byte data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-b it access space), the data size, and endian format when accessing external address space. (1) 8-bit access space with the 8-bit access space, the lower byte data bu s (d7 to d0) is always used for access. the amount of data that can be accessed at one tim e is one byte: a word access is performed as two byte accesses, and a longword acces s, as four byte accesses. figures 8.10 and 8.11 illustrate data alignmen t control for the 8-bit access space. figure 8.10 shows the data alignment when the data endian format is specified as big endian. figure 8.11 shows the data alignment when the data endi an format is specified as little endian. longword access address access count 23 7 15 8 0 7 data size byte byte byte byte byte byte byte byte word 1 1st 1st 2nd 1st 2nd 3rd 4th 2 4 bus cycle data size data bus d15 d8 d7 d0 rd 7 15 31 8 0 24 16 0 lhwr / lub llwr / llb strobe signal n n n figure 8.10 access sizes and data alignment control for 8-bit access space (big endian) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 205 of 1102 rej09b0365-0100 longword access address access count 15 15 23 16 24 31 data size byte byte byte byte byte byte byte byte word 1 1st 1st 2nd 1st 2nd 3rd 4th 2 4 bus cycle data size data bus d15 d8 d7 d0 rd 7 7 7 0 8 0 8 0 lhwr / lub llwr / llb strobe signal n n n figure 8.11 access sizes and data alig nment control for 8-bit access space (little endian) (2) 16-bit access space with the 16-bit access space, the upper byte data bu s (d15 to d8) and lower byte data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word. figures 8.12 and 8.13 illustrate data alignmen t control for the 16-bit access space. figure 8.12 shows the data alignment when the data endian format is specified as big endian. figure 8.13 shows the data alignment when the data endi an format is specified as little endian. in big endian, byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performe d by using the lower byte data bus. in little endian, byte access for an even address is performed by using the lower byte data bus, and byte access for an odd address is performe d by using the third byte data bus. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 206 of 1102 rej09b0365-0100 longword access address access count 15 31 24 0 7 access size byte byte byte byte byte word word word word byte byte word 1 1 1 1st 1st 1st 1st 2nd 1st 2nd 1st 2nd 3rd 2 2 3 bus cycle data size data bus d15 d8 d7 d0 rd 15 23 8 8 7 0 7 0 7 0 23 16 16 15 8 31 24 7 0 15 8 7 0 lhwr / lub llwr / llb strobe signal even (2n) (2n) odd even (2n+1) odd (2n+1) odd (2n+1) even (2n) figure 8.12 access sizes and data alignment control for 16-bit access space (big endian) longword access address access count 15 31 24 0 7 access size byte byte byte byte byte word word word word byte byte word 1 1 1 1st 1st 1st 1st 2nd 1st 2nd 1st 2nd 3rd 2 2 3 bus cycle data size 15 23 8 8 7 0 7 0 7 0 23 16 16 15 8 31 24 7 0 15 8 7 0 even (2n) (2n) odd even (2n+1) odd (2n+1) odd (2n+1) even (2n) data bus d15 d8 d7 d0 rd lhwr / lub llwr / llb strobe signal figure 8.13 access sizes and data alig nment control for 16 -bit access space (little endian) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 207 of 1102 rej09b0365-0100 8.6 basic bus interface the basic bus interface can be connected direc tly to the rom and sram . the bus specifications can be specified by the abwcr, ast cr, wtcra, wtcrb, rdncr, csacr, and endiancr. 8.6.1 data bus data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and contro ls whether the upper byte data bus (d15 to d8) or lower byte data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-b it access space), the data size, and endian format when accessing external address space,. for details, s ee section 8.5.6, endian and data alignment. 8.6.2 i/o pins used for basic bus interface table 8.15 shows the pins us ed for basic bus interface. table 8.15 i/o pins for basic bus interface name symbol i/o function bus cycle start bs output signal indicating that the bus cycle has started address strobe as * output strobe signal indicati ng that an address output on the address bus is valid during access read strobe rd output strobe signal indicating the read access read/write rd/ wr output signal indicating the data bus input or output direction low-high write lhwr output strobe signal indicating that the upper byte (d15 to d8) is valid during write access low-low write llwr output strobe signal indicating that the lower byte (d7 to d0) is valid during write access chip select 0 to 7 cs0 to cs7 output strobe signal indicati ng that the area is selected wait wait input wait request signal used when an external address space is accessed note: * when the address/data multiplexed i/o is selected, this pin only functions as the ah output and does not function as the as output. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 208 of 1102 rej09b0365-0100 8.6.3 basic timing this section describes the basic timing when the data is specified as big endian. (1) 16-bit 2-state access space figures 8.14 to 8.16 sh ow the bus timing of 16 -bit 2-state access space. when accessing 16-bit access space, the upper byte data bus (d 15 to d8) is used for even addresses access, and the lower byte data bus (d7 to d0) is used for odd addr esses. no wait cycles can be inserted. 1. n = 0 to 7 2. when rdnn = 0 3. when dkc = 0 valid invalid valid t 1 t 2 address csn as rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr read write notes: high level high-z b bus cycle bs rd/ wr dack figure 8.14 16-bit 2-stat e access space bus timing (b yte access for even address) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 209 of 1102 rej09b0365-0100 invalid valid t 1 t 2 address csn as rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr dack read write high level high-z b bus cycle valid bs rd/ wr 1. n = 0 to 7 2. when rdnn = 0 3. when dkc = 0 notes: figure 8.15 16-bit 2-stat e access space bus timing (b yte access for odd address) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 210 of 1102 rej09b0365-0100 valid valid t 1 t 2 address csn as rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr dack read write b bus cycle valid valid bs rd/ wr 1. n = 0 to 7 2. when rdnn = 0 3. when dkc = 0 notes: figure 8.16 16-bit 2-stat e access space bus timing (w ord access for even address) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 211 of 1102 rej09b0365-0100 (2) 16-bit 3-state access space figures 8.17 to 8.19 sh ow the bus timing of 16-b it 3-state access space. when accessing 16-bit acces s space, the upper byte data bus (d 15 to d8) is used for even addresses, and the lower byte data bus (d7 to d0) is used for odd addresses. wait cycles can be inserted. valid invalid t 1 t 2 t 3 address csn as rd dack d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr high level high-z b bus cycle valid bs rd/ wr read write 1. n = 0 to 7 2. when rdnn = 0 3. when dkc = 0 notes: figure 8.17 16-bit 3-stat e access space bus timing (b yte access for even address) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 212 of 1102 rej09b0365-0100 invalid valid t 1 t 2 t 3 address csn as rd dack d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr high level high-z b bus cycle valid bs rd/ wr read write 1. n = 0 to 7 2. when rdnn = 0 3. when dkc = 0 notes: figure 8.18 16-bit 3-stat e access space bus timing (w ord access for odd address) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 213 of 1102 rej09b0365-0100 valid valid t 1 t 2 t 3 address csn as rd b bus cycle valid valid rd d15 to d8 d7 to d0 d15 to d8 d7 to d0 lhwr llwr read write bs rd/ wr dack 1. n = 0 to 7 2. when rdnn = 0 3. when dkc = 0 notes: figure 8.19 16-bit 3-stat e access space bus timing (w ord access for even address) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 214 of 1102 rej09b0365-0100 8.6.4 wait control this lsi can extend the bus cycle by inserting wait cycles (tw) when the ex ternal address space is accessed. there are two ways of inserting wait cy cles: program wait (tpw) insertion and pin wait (ttw) insertion using the wait pin. (1) program wait insertion from 0 to 7 wait cycles can be inserted automatically between the t 2 state and t 3 state for 3-state access space, according to the settings in wtcra and wtcrb. (2) pin wait insertion for 3-state access space, when th e waite bit in bcr1 is set to 1 and the corresponding icr bit is set to 1, wait input by means of the wait pin is enabled. when the external address space is accessed in this state, a program wait (tpw) is first inserted according to the wtcra and wtcrb settings. if the wait pin is low at the falling edge of b in the last t2 or tpw cycle, another ttw cycle is inserted until the wait pin is brought high. the pin wait insertion is effective when the tw cycles are inserted to seven cycles or mo re, or when the number of tw cycles to be inserted is changed according to the external devices. the waite bit is common to all areas. for details on icr, see section 11, i/o ports. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 215 of 1102 rej09b0365-0100 figure 8.20 shows an example of wait cycle insertion timing. afte r a reset, the 3-state access is specified, the program wait is inse rted for seven cycles, and the wait input is disabled. wait by program wait t 1 address b as csn rd data bus read read data lhwr , llwr write data write notes: 1. upward arrows indicate the timing of wait pin sampling. 2. n = 0 to 7 3. when rdnn = 0 wait data bus t 2 t pw t tw t tw t 3 wait by wait pin bs rd/ wr figure 8.20 example of wa it cycle insertion timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 216 of 1102 rej09b0365-0100 8.6.5 read strobe ( rd ) timing the read strobe timing can be modified in area units by setting bits rdn7 to rdn0 in rdncr to 1. note that the rd timing with respect to the dack rising edge will change if the read strobe timing is modified by setting rdnn to 1 when the dmac is used in the single address mode. figure 8.21 shows an example of timing when the read strobe timing is changed in the basic bus 3- state access space. bus cycle t 1 t 2 address bus b csn as rd t 3 data bus rd data bus rdnn = 0 rdnn = 1 bs rd/ wr dack 1. n = 0 to 7 2. when dkc = 0 notes: figure 8.21 example of read strobe timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 217 of 1102 rej09b0365-0100 8.6.6 extension of chip select ( cs ) assertion period some external i/o devices require a setu p time and hold time between address and cs signals and strobe signals such as rd , lhwr , and llwr . settings can be made in csacr to insert cycles in which only the cs , as , and address signals are asserted before and after a basic bu s space access cycle. extension of the cs assertion period can be set in area units. with the cs assertion extension period in wr ite access, the data setup and hold times are less stringent since the write data is output to the data bus. figure 8.22 shows an example of the timing when the cs assertion period is extended in basic bus 3-state access space. both extension cycle th inserted before the basi c bus cycle and extension cycle tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. insertion or non- insertion can be specified for the th cycle wi th the upper eight bits (csxh7 to csxh0) in csacr, and for the tt cycle with the lower eight bits (csxt7 to csxt0). section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 218 of 1102 rej09b0365-0100 t h t 1 t 2 t 3 t t address bus cycle b as csn rd data bus read data read lhwr , llwr write data write data bus bs rd/ wr dack 1. n = 0 to 7 2. when dkc = 0 notes: figure 8.22 example of timing when ch ip select assertion period is extended section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 219 of 1102 rej09b0365-0100 8.6.7 dack signal output timing for dmac single address transfers, the dack signal assert timing can be modified by using the dkc bit in bcr1. figure 8.23 shows the dack signal output timing. setting the dkc bit to 1 asserts the dack signal a half cycle earlier. t 1 t 2 bus cycle b address bus write data write read data read csn as rd data bus data bus lhwr , llwr bs rd/ wr dkc = 0 dkc = 1 dack notes: 1. n = 7 to 0 2. rdnn = 0 figure 8.23 dack signal output timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 220 of 1102 rej09b0365-0100 8.7 byte control sram interface the byte control sram interface is a memory interface for outputting a byte select strobe during a read or a write bus cycle. this interface has 16-b it data input/output pins and can be connected to the sram that has the upper byte select a nd the lower byte select strobes such as ub and lb . the operation of the byte contro l sram interface is the same as the basic bus interface except that: the byte select strobes ( lub and llb ) are output from the write strobe output pins ( lhwr and llwr ), respectively; th e read strobe ( rd ) negation timing is a half cy cle earlier than that in the case where rdnn = 0 in the basic bus interface regardless of the rdncr settings; and the rd/ wr signal is used as write enable. 8.7.1 byte control sram space setting byte control sram interface can be specified for areas 0 to 7. each area can be specified as byte control sram interface by setting bits bcseln (n = 0 to 7) in sramcr. for the area specified as burst rom interface or addr ess/data multiplexed i/o interface, the sramcr setting is invalid and byte control sram interface cannot be used. 8.7.2 data bus the bus width of the byte control sram space can be specified as 16- bit byte control sram space according to bits abwhn and abwln (n = 0 to 7) in abwcr. the area specified as 8-bit access space cannot be specified as the byte control sram space. for the 16-bit byte control sram space, data bus (d15 to d0) is valid. access size and data alignment are the same as the basic bus interface. for details, see section 8.5.6, endian and data alignment. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 221 of 1102 rej09b0365-0100 8.7.3 i/o pins used for by te control sram interface table 8.16 shows the pins used for the byte control sram interface. in the byte control sram inte rface, write strobe signals ( lhwr and llwr ) are output from the byte select strobes. the rd/ wr signal is used as a write enable signal. table 8.16 i/o pins for byte control sram interface pin when byte control sram is specified name i/o function as / ah as address strobe output strobe signal indi cating that the address output on the address bus is valid when a basic bus interface space or byte control sram space is accessed csn csn chip select output strobe signal indicating that area n is selected rd rd read strobe output output enable for the sram when the byte control sram space is accessed rd/ wr rd/ wr read/write output write enable signal for the sram when the byte control sram space is accessed lhwr / lub lub lower-upper byte select output upper byte select when the 16-bit byte control sram space is accessed llwr / llb llb lower-lower byte select output lower byte select when the 16-bit byte control sram space is accessed wait wait wait input wait request signal used when an external address space is accessed a20 to a0 a20 to a0 address pin output address output pin d15 to d0 d15 to d0 data pin input/ output data input/output pin section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 222 of 1102 rej09b0365-0100 8.7.4 basic timing (1) 2-state access space figure 8.24 shows the bus timing when the byte control sram space is specified as a 2-state access space. data buses used for 16-bit access space is the same as those in basic bus interface. no wait cycles can be inserted. b address d15 to d8 d7 to d0 high level d15 to d8 d7 to d0 bus cycle csn as rd lub llb dack bs rd/ wr rd rd/ wr t 1 t 2 note: n = 0 to 7 valid valid read write valid valid figure 8.24 16-bit 2-stat e access space bus timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 223 of 1102 rej09b0365-0100 (2) 3-state access space figure 8.25 shows the bus timing when the byte control sram space is specified as a 3-state access space. data buses used for 16-bit access space is the same as those in the basic bus interface. wait cycles can be inserted. b address high level bus cycle csn as t 1 t 2 t 3 valid valid valid valid d15 to d8 d7 to d0 d15 to d8 d7 to d0 rd lub llb dack bs rd/ wr rd rd/ wr note: n = 0 to 7 read write figure 8.25 16-bit 3-st ate access space bus timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 224 of 1102 rej09b0365-0100 8.7.5 wait control the bus cycle can be extended for the byte contro l sram interface by inserting wait cycles (tw) in the same way as the basic bus interface. (1) program wait insertion from 0 to 7 wait cycles can be inserted automa tically between t2 cycle and t3 cycle for the 3- state access space in area units, according to the settings in wtcra and wtcrb. (2) pin wait insertion for 3-state access space, when the waite bit in bcr1 is set to 1, the corresponding ddr bit is cleared to 0, and the icr bit is set to 1, wait input by means of the wait pin is enabled. for details on ddr and icr, see section 11, i/o ports. figure 8.26 shows an example of wait cycle insertion timing. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 225 of 1102 rej09b0365-0100 wait by program wait t 1 address b as dack lub , llb csn rd rd rd/ wr rd/ wr data bus read data read bs write data high level write notes: 1. upward arrows indicate the timing of wait pin sampling. 2. n = 0 to 7 wait data bus t 2 t pw t tw t tw t 3 wait by wait pin figure 8.26 example of wa it cycle insertion timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 226 of 1102 rej09b0365-0100 8.7.6 read strobe ( rd ) when the byte control sram space is specified , the rdncr setting for the corresponding space is invalid. the read strobe negation timing is the same timing as when rdnn = 1 in the basic bus interface. note that the rd timing with respect to the dack rising edge becomes different. 8.7.7 extension of chip select ( cs ) assertion period in the byte control sram interface, the extension cycles can be inserted before and after the bus cycle in the same way as the basic bus interface. fo r details, see section 8. 6.6, extension of chip select ( cs ) assertion period. 8.7.8 dack signal output timing for dmac single address transfers, the dack signal assert timing can be modified by using the dkc bit in bcr1. figure 8.27 shows the dack signal output timing. setting the dkc bit to 1 asserts the dack signal a half cycle earlier. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 227 of 1102 rej09b0365-0100 b address d15 to d8 d7 to d0 high level d15 to d8 d7 to d0 dkc = 0 dkc = 1 bus cycle csn as rd lub llb bs dack rd/ wr rd rd/ wr t 1 t 2 valid valid read write valid valid figure 8.27 dack signal output timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 228 of 1102 rej09b0365-0100 8.8 burst rom interface in this lsi, external address space areas 0 and 1 can be designated as burst rom space, and burst rom interfacing performed. the burst rom interface enables ro m with page access capability to be accessed at high speed. areas 1 and 0 can be designated as burst ro m space by means of bits bsrm1 and bsrm0 in bromcr. consecutive burst accesses of up to 32 words can be performe d, according to the setting of bits bswdn1 and bswdn0 (n = 0, 1) in bromcr. from one to eight cycles can be selected for burst access. settings can be made independently for area 0 and area 1. in the burst rom interface, th e burst access covers only cpu read accesses. other accesses are performed with the similar method to the basic bus interface. 8.8.1 burst rom space setting burst rom interface can be specified for areas 0 and 1. areas 0 an d 1 can be specified as burst rom space by setting bits bsrm n (n = 0, 1) in bromcr. 8.8.2 data bus the bus width of the burst rom space can be sp ecified as 8-bit or 16 -bit burst rom interface space according to the abwhn and abwl n bits (n = 0, 1) in abwcr. for the 8-bit bus width, data bus (d7 to d0) is valid. for the 16-bit bus width, data bus (d15 to d0) is valid. access size and data alignment are the same as the basic bus interface. for details, see section 8.5.6, endian and data alignment. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 229 of 1102 rej09b0365-0100 8.8.3 i/o pins used for burst rom interface table 8.17 shows the pins used for the burst rom interface. table 8.17 i/o pins used for burst rom interface name symbol i/o function bus cycle start bs output signal indicati ng that the bus cycle has started. address strobe as output strobe signal indicating that an address output on the address bus is valid during access read strobe rd output strobe signal indicating the read access read/write rd/ wr output signal indicating the data bus input or output direction low-high write lhwr output strobe signal indicating that the upper byte (d15 to d8) is valid during write access low-low write llwr output strobe signal indicating that the lower byte (d7 to d0) is valid during write access chip select 0 to 7 cs0 to cs7 output strobe signal indicati ng that the area is selected wait wait input wait request signal used when an external address space is accessed section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 230 of 1102 rej09b0365-0100 8.8.4 basic timing the number of access cycles in the initial cycle (full access) on the burst rom interface is determined by the basic bus interface settings in abwcr, astcr, wtcra, wtcrb, and bits csxhn in csacr (n = 0 to 7). when area 0 or area 1 designa ted as burst rom space is read by the cpu, the settings in rdncr and bits cs xtn in csacr (n = 0 to 7) are ignored. from one to eight cycles can be selected for th e burst cycle, according to the settings of bits bsts02 to bsts00 and bsts12 to bsts10 in bromcr. wait cycles cannot be inserted. in addition, 4-word, 8-word, 16-w ord, or 32-word consecutive burst access can be performed according to the settings of bsts01, bsts00 , bsts11, and bsts10 bits in bromcr. the basic access timing for bu rst rom space is shown in figures 8.28 and 8.29. t 1 t 2 t 1 t 2 t 1 t 2 t 3 b upper address bus note: n = 1, 0 lower address bus data bus full access burst access csn as rd bs rd/ wr figure 8.28 example of burst rom acce ss timing (astn = 1, two burst cycles) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 231 of 1102 rej09b0365-0100 t 1 t 2 t 1 t 1 b upper address bus lower address bus data bus full access burst access csn as rd bs rd/ wr note: n = 1, 0 figure 8.29 example of burst rom acce ss timing (astn = 0, one burst cycle) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 232 of 1102 rej09b0365-0100 8.8.5 wait control as with the basic bus interface, either program wait insertion or pin wait insertion by the wait pin can be used in the initial cycle (full access) on the burst rom interfa ce. see section 8.6.4, wait control. wait cycles cannot be inserted in a burst cycle. 8.8.6 read strobe ( rd ) timing when the burst rom space is read by the cpu, the rdncr setting for the corresponding space is invalid. the read strobe negation timing is the same timing as when rdnn = 0 in the basic bus interface. 8.8.7 extension of chip select ( cs ) assertion period in the burst rom interface, the exte nsion cycles can be inserted in the same way as the basic bus interface. for the burst rom space, the burst access can be enab led only in read access by the cpu. in this case, the setting of the corresponding csxtn bit in csacr is ignored and an extension cycle can be inserted only before the full acce ss cycle. note that no extension cycle can be inserted before or after the burst access cycles. in accesses other than read accesses by the cpu, the burst rom space is equivalent to the basic bus interface space. accordingly, ex tension cycles can be inserted before and after the burst access cycles. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 233 of 1102 rej09b0365-0100 8.9 address/data multiplexed i/o interface if areas 3 to 7 of external address space are specified as address/data multiplexed i/o space in this lsi, the address/data multiplexed i/o interface can be performed. in the address/data multiplexed i/o interface, peripheral lsis th at require the multiplexed address/data can be connected directly to this lsi. 8.9.1 address/data multiplexed i/o space setting address/data multiplexed i/o interface can be sp ecified for areas 3 to 7. each area can be specified as the address/data multiplexed i/o space by setting b its mpxen (n = 3 to 7) in mpxcr. 8.9.2 address/data multiplex in the address/data multiplexed i/o space, data bus is multiplexed with address bus. table 8.18 shows the relationship between the bus width and address output. table 8.18 address/data multiplex bus width cycle data pins address data address data 8 bits 16 bits pi7 - - a15 d15 pi6 - - a14 d14 pi5 - - a13 d13 pi4 - - a12 d12 pi3 - - a11 d11 pi2 - - a10 d10 pi1 - - a9 d9 pi0 - - a8 d8 ph7 a7 d7 a7 d7 ph6 a6 d6 a6 d6 ph5 a5 d5 a5 d5 ph4 a4 d4 a4 d4 ph3 a3 d3 a3 d3 ph2 a2 d2 a2 d2 ph1 a1 d1 a1 d1 ph0 a0 d0 a0 d0 8.9.3 data bus the bus width of the address/data multiplexed i/o space can be specified for either 8-bit access space or 16-bit access space by th e abwhn and abwln bits (n = 3 to 7) in abwcr. for the 8-bit access space, d7 to d0 are valid for both addr ess and data. for 16-bit access space, d15 to d0 are valid for both address and data. if the address/data multiplexed i/o space is accessed, the corresponding address w ill be output to the address bus. for details on access size and data alignment, s ee section 8.5.6, endian and data alignment. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 234 of 1102 rej09b0365-0100 8.9.4 i/o pins used for address/data multiplexed i/o interface table 8.19 shows the pins used for the address/data multiplexed i/o interface. table 8.19 i/o pins for address/ data multiplexed i/o interface pin when byte control sram is specified name i/o function csn csn chip select output chip select (n = 3 to 7) when area n is specified as the address/data multiplexed i/o space as / ah ah * address hold output signal to hold an address when the address/data multiplexed i/o space is specified rd rd read strobe output signal indicating that the address/data multiplexed i/o space is being read lhwr / lub lhwr low-high write output strobe signal indicating that the upper byte (d15 to d8) is valid when the address/data multiplexed i/o space is written llwr / llb llwr low-low write output strobe signal indicating that the lower byte (d7 to d0) is valid when the address/data multiplexed i/o space is written d15 to d0 d15 to d0 address/data input/ output address and data multiplexed pins for the address/data multiplexed i/o space. only d7 to d0 are valid when the 8-bit space is specified. d15 to d0 are valid when the 16-bit space is specified. a20 to a0 a20 to a0 address output address output pin wait wait wait input wait request signal used when the external address space is accessed bs bs bus cycle start output signal to indicate the bus cycle start rd/ wr rd/ wr read/write output signal indicating t he data bus input or output direction note: * the ah output is multiplexed with the as output. at the timing that an area is specified as address/data multiplexed i/o, this pin starts to function as the ah output meaning that this pin cannot be used as the as output. at this time, when other areas set to the basic bus interface is accessed, this pin does not function as the as output. until an area is specified as address/data multiplex ed i/o, be aware that this pin functions as the as output. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 235 of 1102 rej09b0365-0100 8.9.5 basic timing the bus cycle in the address/data multiplexed i/o in terface consists of an address cycle and a data cycle. the data cycle is based on the basi c bus interface timing sp ecified by the abwcr, astcr, wtcra, wtcrb, rdncr, and csacr. figures 8.30 and 8.31 show the basic access timings. t ma1 t ma2 t 2 t 1 b address bus d7 to d0 d7 to d0 address cycle data cycle csn llwr ah rd dack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 8.30 8-bit access space acce ss timing (abwhn = 1, abwln = 1) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 236 of 1102 rej09b0365-0100 rd t ma1 t ma2 t 2 t 1 b address bus d15 to d0 d15 to d0 address cycle bus cycle data cycle csn lhwr llwr ah dack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 8.31 16-bit access space acces s timing (abwhn = 0, abwln = 1) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 237 of 1102 rej09b0365-0100 8.9.6 address cycle control an extension cycle (tmaw) can be inserted be tween tma1 and tma2 cycles to extend the ah signal output period by setting the addex bit in mpxcr. by inserting the tmaw cycle, the address setup for ah and the ah minimum pulse width can be assured. figure 8.32 shows the access timing when the address cycle is three cycles. t ma1 t maw t ma2 t 2 t 1 b address bus d15 to d0 d15 to d0 address cycle data cycle csn lhwr llwr ah rd dack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 8.32 access timing of 3 address cycles (addex = 1) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 238 of 1102 rej09b0365-0100 8.9.7 wait control in the data cycle of the address/data multiplexed i/o interface, program wait insertion and pin wait insertion by the wait pin are enabled in the same way as in the basic bus interface. for details, see section 8.6.4, wait control. wait control settings do not affect the address cycles. 8.9.8 read strobe ( rd ) timing in the address/data multiplexed i/o interface, the read strobe timing of data cycles can be modified in the same way as in basic bus interface. for details, see section 8.6.5, read strobe ( rd ) timing. figure 8.33 shows an example when the read strobe timing is modified. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 239 of 1102 rej09b0365-0100 t ma1 t ma2 t 2 t 1 b address bus d15 to d0 d15 to d0 address cycle data cycle csn rd ah rd dack bs rd/ wr note: n = 3 to 7 address read data address read data rdnn = 0 rdnn = 1 figure 8.33 read strobe timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 240 of 1102 rej09b0365-0100 8.9.9 extension of chip select ( cs ) assertion period in the address/data multiplexed inte rface, the extension cycles can be inserted before and after the bus cycle. for details, see section 8.6.6, extension of chip select ( cs ) assertion period. figure 8.34 shows an exam ple of the chip select ( cs ) assertion period extension timing. t ma1 t ma2 t 2 t t t 1 t h b address bus d15 to d0 d15 to d0 address cycle bus cycle data cycle csn lhwr llwr ah rd dack bs rd/ wr note: n = 3 to 7 address read data address write data read write figure 8.34 chip select ( cs ) assertion period extensio n timing in data cycle section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 241 of 1102 rej09b0365-0100 when consecutively reading from the same area co nnected to a peripheral lsi whose data hold time is long, data outputs from the peripheral ls i and this lsi may conflict. inserting the chip select assertion period extension cycle afte r the access cycle can avoid the data conflict. figure 8.35 shows an example of the operation. in the figure, both bus cycles a and b are read access cycles to the address/data multiplexed i/o sp ace. an example of the data conflict is shown in (a), and an example of avoiding the data conflict by the cs assertion period extension cycle in (b). b address bus data bus bus cycle a bus cycle b cs ah rd (a) without cs assertion period extension cycle (csxtn = 0) (b) with cs assertion period extension cycle (csxtn = 1) data hold time is long. data conflict b address bus data bus bus cycle a bus cycle b cs ah rd figure 8.35 consecutive read accesses to same area (address/data multiplexed i/o space) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 242 of 1102 rej09b0365-0100 8.9.10 dack signal output timing for dmac single address transfers, the dack signal assert timing can be modified by using the dkc bit in bcr1. figure 8.36 shows the dack signal output timing. setting the dkc bit to 1 asserts the dack signal a half cycle earlier. t ma1 t ma2 t 2 t 1 b dkc = 0 dkc = 1 address bus d15 to d0 d15 to d0 address cycle data cycle csn rd ah rd dack bs rd/ wr note: n = 3 to 7 address read data rdnn = 0 rdnn = 1 address read data figure 8.36 dack signal output timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 243 of 1102 rej09b0365-0100 8.10 idle cycle in this lsi, idle cycles can be inserted between the consecutive external ac cesses. by inserting the idle cycle, data conflicts between rom read cycl e whose output floating time is long and an access cycle from/to high-speed memory or i/o interface can be prevented. 8.10.1 operation when this lsi consecutively accesses external addres s space, it can insert an idle cycle between bus cycles in the following four cases. these conditions are determined by the sequence of read and write and previously accessed area. 1. when read cycles of different areas in the external address sp ace occur consecutively 2. when an external write cycle occurs immediately after an external read cycle 3. when an external read cycle occurs immediately after an external write cycle 4. when an external access occu rs immediately after a dmac si ngle address transfer (write cycle) up to four idle cycles can be inserted under the conditions shown above. the number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data from a subsequently accessed device. under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of idle cycles can be selected from setting a specified by bits idlca1 and idlca0 in idlcr or setting b specified by bits idlcb1 and idlcb0 in idlcr: setting a can be selected from one to four cycles, and setting b can be selected from one or two to four cycles. setting a or b can be specified for each area by setting bits idlsel7 to idlsel0 in idlcr. note that bits idlsel7 to idlsel0 correspond to the previously accessed area of the consecutive accesses. the number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert idle cycles after write, can be determined by setting a as described above. after the reset release, idlcr is initialized to four idle cycle insertion under all conditions 1 to 4 shown above. table 8.20 shows the correspondence between conditio ns 1 to 4 and number of idle cycles to be inserted for each area. table 8.21 shows the corre spondence between the number of idle cycles to be inserted specified by settings a and b, and number of cycles to be inserted. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 244 of 1102 rej09b0365-0100 table 8.20 number of idle cycle in sertion selection in each area bit settings idlsn idlseln area for previous access insertion condition n setting n = 0 to 7 0 1 2 3 4 5 6 7 0 ? invalid 0 a a a a a a a a consecutive reads in different areas 1 1 1 b b b b b b b b 0 ? invalid 0 a a a a a a a a write after read 0 1 1 b b b b b b b b 0 invalid read after write 2 1 ? a 0 invalid external access after single address transfer 3 1 ? a [legend] a: number of idle cycle insertion a is selected. b: number of idle cycle insertion b is selected. invalid: no idle cycle is inserted for the corresponding condition. table 8.21 number of idle cycle insertions bit settings a b idlca1 idlca0 idlcb1 idlcb0 number of cycles ? ? 0 0 0 0 0 ? ? 1 0 1 0 1 2 1 0 1 0 3 1 1 1 1 4 section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 245 of 1102 rej09b0365-0100 (1) consecutive reads in different areas if consecutive reads in different areas occur while bit idls1 in idlcr is set to 1, idle cycles specified by bits idlca1 and id lca0 when bit idlseln in idl cr is cleared to 0, or bits idlcb1 and idlcb0 when bit idls eln is set to 1 are inserted at the start of the second read cycle (n = 0 to 7). figure 8.37 shows an example of the operation in th is case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a read cycle for sram, each being located in a different area. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data conflict is prevented. data hold time is long. data conflict bus cycle a bus cycle b (a) no idle cycle inserted (idls1 = 0) (b) idle cycle inserted b address bus cs (area a) cs (area b) rd data bus t 1 t 2 t 3 t 1 t 2 bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (idls1 = 1, idlseln = 0, idlca1 = 0, idlca0 = 0) figure 8.37 example of idle cycle operat ion (consecutive read s in different areas) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 246 of 1102 rej09b0365-0100 (2) write after read if an external write occurs after an external read while bit idls0 in idlcr is set to 1, idle cycles specified by bits idlca1 and idlca0 when bit idlseln in idlcr is cleared to 0 when idlseln = 0, or bits idlcb1 and idlcb0 when idlseln is set to 1 are inserted at the start of the write cycle (n = 0 to 7). figure 8.38 shows an example of the operation in th is case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data conflict is prevented. data hold time is long. data conflict bus cycle a bus cycle b b address bus cs (area a) cs (area b) rd llwr data bus t 1 t 2 t 3 t 1 t 2 (b) idle cycle inserted bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (a) no idle cycle inserted (idls0 = 0) (idls0 = 1, idlseln = 0, idlca1 = 0, idlca0 = 0) figure 8.38 example of idle cy cle operation (write after read) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 247 of 1102 rej09b0365-0100 (3) read after write if an external read occurs after an external write while bit idls2 in idlcr is set to 1, idle cycles specified by bits idlca1 and idlca0 are inserted at the start of the read cycle (n = 0 to 7). figure 8.39 shows an example of the operation in this case. in this exampl e, bus cycle a is a cpu write cycle and bus cycle b is a read cycle from th e sram. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the cpu write data and read data from an sram device. in (b), an idle cy cle is inserted, and a data conflict is prevented. output floating time is long. data conflict bus cycle a bus cycle b b address bus cs (area a) cs (area b) rd llwr data bus t 1 t 2 t 3 t 1 t 2 bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (a) no idle cycle inserted (idls2 = 0) (b) idle cycle inserted (idls2 = 1, idlca1 = 0, idlca0 = 0) figure 8.39 example of idle cy cle operation (read after write) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 248 of 1102 rej09b0365-0100 (4) external access after si ngle address transfer write if an external access occurs after a single address transfer write while bit idls3 in idlcr is set to 1, idle cycles specified by bits idlca1 and idlca0 are inserted at the start of the external access (n = 0 to 7). figure 8.40 shows an example of the operation in this case. in this example, bus cycle a is a single address transfer (wr ite cycle) and bus cycle b is a cpu writ e cycle. in (a), an idle cycle is not inserted, and a conflict occurs in bus cycle b between the external device write data and this lsi write data. in (b), an idle cycle is inserted, and a data conflict is prevented. output floating time is long. data conflict bus cycle a bus cycle b (a) no idle cycle inserted (idls3 = 0) b address bus cs (area a) cs (area b) llwr dack data bus t 1 t 2 t 3 t 1 t 2 (b) idle cycle inserted bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 (idls3 = 1, idlca1 = 0, idlca0 = 0) figure 8.40 example of idle cycle operation (write after single address transfer write) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 249 of 1102 rej09b0365-0100 (5) external nop cycl es and idle cycles a cycle in which an external space is not accessed du e to internal operations is called an external nop cycle. even when an external nop cycle occu rs between consecutive ex ternal bus cycles, an idle cycle can be inserted. in this case, the numb er of external nop cycl es is included in the number of idle cycles to be inserted. figure 8.41 shows an example of external nop and idle cycle insertion. t 1 t 2 t 3 t pw t 1 t 2 t 3 t pw t i t i address bus no external access (nop) specified number of idle cycles or more including no external access cycles (nop) idle cycle (remaining) following bus cycle preceding bus cycle (condition: number of idle cycles to be inserted when different reads continue: 4 cycles) data bus b cs (area b) cs (area a) rd figure 8.41 idle cycle insertion example section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 250 of 1102 rej09b0365-0100 (6) relationship between chip select ( cs ) signal and read ( rd ) signal depending on the system's load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 8.42. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the rd signal in bus cycle a and the cs signal in bus cycle b. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset releas e, idle cycle indicated in (b) is set. bus cycle a bus cycle b b address bus cs (area a) cs (area b) rd t 1 t 2 t 3 t 1 t 2 bus cycle a bus cycle b t 1 t 2 t 3 t 1 t i t 2 overlap time may occur between the cs (area b) and rd (a) no idle cycle inserted (idls1 = 0) (b) idle cycle inserted (idls1 = 1, idlseln = 0, idlca1 = 0, idlca0 = 0) figure 8.42 relationship between chip select ( cs ) and read ( rd ) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 251 of 1102 rej09b0365-0100 table 8.22 idle cycles in mi xed accesses to normal space idls idlsel idlca idlcb previous access next access 3 2 1 0 7 to 0 1 0 1 0 idle cycle ? ? 0 ? ? ? ? ? ? disabled normal space read normal space read ? ? 1 ? 0 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1 ? ? 0 0 0 cycle inserted 0 1 2 cycle inserted 1 0 3 cycles inserted 1 1 4 cycles inserted ? ? ? 0 ? ? ? ? ? disabled normal space read normal space write ? ? ? 1 0 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 1 ? ? 0 0 0 cycle inserted 0 1 2 cycle inserted 1 0 3 cycles inserted 1 1 4 cycles inserted ? 0 ? ? ? ? ? ? ? disabled normal space write normal space read ? 1 ? ? ? 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted 0 ? ? ? ? ? ? ? ? disabled single address transfer write normal space read 1 ? ? ? ? 0 0 ? ? 1 cycle inserted 0 1 2 cycles inserted 1 0 3 cycles inserted 1 1 4 cycles inserted section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 252 of 1102 rej09b0365-0100 8.10.2 pin states in idle cycle table 8.23 shows the pin st ates in an idle cycle. table 8.23 pin states in idle cycle pins pin state a20 to a0 contents of following bus cycle d15 to d0 high impedance csn (n = 7 to 0) high as high rd high bs high rd/ wr high ah low lhwr , llwr high dackn (n = 3 to 0) high section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 253 of 1102 rej09b0365-0100 8.11 bus release this lsi can release the external bus in response to a bus request from an external device. in the external bus released state, intern al bus masters continue to operate as long as there is no external access. in addition, in the external bus released state, the breqo signal can be driven low to output a bus request externally. 8.11.1 operation in external extended mode, when the brle bit in bcr1 is set to 1 and the icr bits for the corresponding pin are set to 1, the bus can be released to the external. driving the breq pin low issues an external bus request to this lsi. when the breq pin is sampled, at the prescribed timing, the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing th e external bus released state. for details on ddr and icr, see section 11, i/o ports. in the external bus released state, the cpu, dtc, and dmac can access the internal space using the internal bus. when the cpu, dtc, or dmac attempts to access the exte rnal address space, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. if the breqoe bit in bcr1 is set to 1, the breqo pin can be driven low when any of the following requests are issued, to request cancellation of the bus request externally. ? when the cpu, dtc, or dmac attemp ts to access the external address space ? when a sleep instruction is executed to place the chip in software standby mode or all- module-clock-stop mode ? when sckcr is written to for setting the clock frequency if an external bus release request and external access occur simultaneously, the priority is as follows: (high) external bus release > extern al access by cpu, dtc, or dmac (low) section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 254 of 1102 rej09b0365-0100 8.11.2 pin states in external bus released state table 8.24 shows pin states in th e external bus released state. table 8.24 pin states in bus released state pins pin state a20 to a0 high impedance d15 to d0 high impedance bs high impedance csn (n = 7 to 0) high impedance as high impedance ah high impedance rd/ wr high impedance rd high impedance lub , llb high impedance lhwr , llwr high impedance dackn (n = 3 to 0) high level section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 255 of 1102 rej09b0365-0100 8.11.3 transition timing figure 8.43 shows the timing for transition to the bus released state. b address bus csn lhwr , llwr as hi-z hi-z [1] [2] [3] [4] [7] [5] [6] [8] hi-z hi-z hi-z hi-z rd breq back breqo external space access cycle cpu cycle external bus released state data bus t 1 t 2 [1] a low level of the breq signal is sampled at the rising edge of the b signal. [2] the bus control signals are driven high at the end of the external space access cycle. it takes two cycles or more after the low level of the breq signal is sampled. [3] the back signal is driven low, releasing bus to the external bus master. [4] the breq signal state sampling is continued in the external bus released state. [5] a high level of the breq signal is sampled. [6] the external bus released cycles are ended one cycle after the breq signal is driven high. [7] when the external space is accessed by an internal bus master during external bus released while the breqoe bit is set to 1, the breqo signal goes low. [8] normally the breqo signal goes high at the rising edge of the back signal. figure 8.43 bus released state transition timing section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 256 of 1102 rej09b0365-0100 8.12 internal bus 8.12.1 access to internal address space the internal address spaces of this lsi are the on-chip rom space, on-chip ram space, and register space for the on-chip peripheral module s. the number of cycles necessary for access differs according the space. table 8.25 shows the number of access cycles for each on-chip memory space. table 8.25 number of access cycl es for on-chip memory spaces access space access number of access cycles read one i cycle on-chip rom space write three i cycles read one i cycle on-chip ram space write one i cycle in access to the registers for on -chip peripheral modul es, the number of access cycles differs according to the register to be accessed. when the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access in the same way as for external bus clock division. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 257 of 1102 rej09b0365-0100 table 8.26 lists the number of access cycles for registers of on-chip peripheral modules. table 8.26 number of access cycles for registers of on-chip peripheral modules number of cycles module to be accessed read write write data buffer function dmac registers two i two i disabled mcu operating mode, clock pulse generator, power-down control registers, interrupt controller, bus controller, and dtc registers two i three i disabled i/o port registers of pfcr and wdt two p three p disabled i/o port registers other than pfcr and portn, ppg0, tpu, tmr0, tmr1, sci0 to sci4, iic2_0, iic2_1, d/a, and a/d_0 registers two p two p enabled i/o port registers of portn, tmr2, tmr3, sci5, sci6, iic2_2, iic2_3, a/d_1, a/d_2, and ppg1 registers three p three p enabled section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 258 of 1102 rej09b0365-0100 8.13 write data buffer function 8.13.1 write data buffer function for external data bus this lsi has a write data buffer function for the external data bus. using the write data buffer function enables internal accesses in parallel with external writes or dmac single address transfers. the write data buffer function is made available by setting the wdbe bit to 1 in bcr1. figure 8.44 shows an example of the timing when the write data buffer function is used. when this function is used, if an external address space write or a dmac single address transfer continues for two cycles or longer, and there is an internal access next, an exte rnal write only is executed in the first two cycles. however, fr om the next cycle onward, intern al accesses (on-chip memory or internal i/o register read/write ) and the external address space wr ite rather than waiting until it ends are executed in parallel. on-chip memory read peripheral module read peripheral module address external write cycle on-chip memory 2 on-chip memory 1 external address internal address bus b address bus csn lhwr , llwr d15 to d0 external space write t 1 t 2 t 3 i figure 8.44 example of timing when write data buffer function is used section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 259 of 1102 rej09b0365-0100 8.13.2 write data buffer func tion for peripheral modules this lsi has a write data buffer function for th e peripheral module access. using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel. the write data buffer function is made available by setting the pwdbe bit in bcr2 to 1. for details on the on-chip peripheral module registers, see table 8.26, number of access cycles for registers of on-chip peripheral modules in section 8.12, internal bus. figure 8.45 shows an example of the timing when the write data buffer function is used. when this function is used, if an internal i/o register write continues for two cycles or longer and then there is an on-chip ram, an on-chip rom, or an exte rnal access, internal i/o register write only is performed in the first two cycles. however, from the next cycle onward an internal memory or an external access and internal i/o regi ster write are executed in para llel rather than waiting until it ends. on-chip memory read peripheral module write peripheral module address internal address bus p i internal i/o address bus internal i/o data bus figure 8.45 example of timing when peripheral module write data buffer function is used section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 260 of 1102 rej09b0365-0100 8.14 bus arbitration this lsi has bus arbiters that arbitrate bus ma stership operations (bus arbitration). this lsi incorporates internal access and external access bu s arbiters that can be used and controlled independently. the internal bus arbiter handles the cpu, dtc, and dmac accesses. the external bus arbiter handles the external access by the cp u, dtc, and dmac and external bus release request (external bus master). the bus arbiters determine priorities at the prescr ibed timing, and permit use of the bus by means of the bus request acknowledge signal. 8.14.1 operation the bus arbiter detects the bus mast ers' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal , it takes possession of the bus until that signal is canceled. the priority of the internal bus arbitration: (high) dmac > dtc > cpu (low) the priority of the external bus arbitration: (high) external bus release request > external access by the cpu, dtc, and dmac (low) if the dmac or dtc accesses continue, the cpu ca n be given priority over the dmac or dtc to execute the bus cycles alternatively between them by setting the ibccs bit in bcr2. in this case, the priority between the dm ac and dtc does not change. an internal bus access by the cpu, dtc, or dmac and an external bus access by an external bus release request can be executed in parallel. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 261 of 1102 rej09b0365-0100 8.14.2 bus transfer timing even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. there ar e specific timings at which each bu s master can release the bus. (1) cpu the cpu is the lowest-priority bus master, and if a bus request is received from the dtc or dmac, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is at the en d of the bus cycle. in sleep mode, the bus is transferred synchronously with the clock. note, however, that the bus cannot be transferre d in the following cases. ? the word or longword access is performed in some divisions. ? stack handling is performed in multiple bus cycles. ? transfer data read or write by memory transfer instructions, block transfer instructions, or tas instruction. (in the block transfer instructions, the bus ca n be transferred in the write cycle and the following transfer data read cycle.) ? from the target read to write in the bit manipulation instructions or memory operation instructions. (in an instruction that performs no write operatio n according to the instruction condition, up to a cycle corresponding the write cycle) (2) dtc the dtc sends the internal bus arbiter a request for the bus wh en an activation request is generated. when the dtc accesses an external bu s space, the dtc first takes control of the bus from the internal bus arbiter and then requ ests a bus to the external bus arbiter. once the dtc takes control of the bus, the dtc co ntinues the transfer pro cessing cycles. if a bus master whose priority is higher than the dtc re quests the bus, the dtc transfers the bus to the higher priority bus master. if the ibccs bit in bcr2 is set to 1, the dtc transfers the bus to the cpu. note, however, that the bu s cannot be transferred in the following cases. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 262 of 1102 rej09b0365-0100 ? during transfer information read ? during the first data transfer ? during transfer information write back the dtc releases the bus when the cons ecutive transfer cy cles completed. (3) dmac the dmac sends the internal bus arbiter a request for the bus when an activation request is generated. when the dmac accesses an external bus space, the dmac first takes control of the bus from the internal bus arbiter and then requ ests a bus to the external bus arbiter. after the dmac takes control of the bus, it may con tinue the transfer proce ssing cycles or release the bus at the end of every bus cycle depending on the conditions. the dmac continues transfers without releasing the bus in the following case: ? between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle if no bus master of a higher priority than the dmac requests the bus and the ibccs bit in bcr2 is cleared to 0, the dmac continues transfers without releasing the bus in the following cases: ? during 1-block transfers in the block transfer mode ? during transfers in the burst mode in other cases, the dmac transfers th e bus at the end of the bus cycle. (4) external bus release when the breq pin goes low and an external bus release request is issued while the brle bit in bcr1 is set to 1 with the corresponding icr bit set to 1, a bus request is sent to the bus arbiter. external bus release can be performed on completion of an external bus cycle. 8.15 bus controller operation in reset in a reset, this lsi, including the bus controlle r, enters the reset state immediately, and any executing bus cycle is aborted. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 263 of 1102 rej09b0365-0100 8.16 usage notes (1) setting registers the bsc registers must be specified before accessi ng the external address space. in on-chip rom disabled mode, the bsc registers must be specifie d before accessing the external address space for other than an instruction fetch access. (2) external bus release function and all-module-clock-stop mode in this lsi, if the acse bit in mstpcra is set to 1, and then a sleep instruction is executed with the setting for all peripheral module clocks to be stopped (mstpcra and mstpcrb = h'ffffffff) or for operation of the 8-bit timer module alone (mstpcra and mstpcrb = h'f[f to c]ffffff), and a transition is made to the sleep state, the all-module-clock-stop mode is entered in which the clock is also stopped for the bus controller and i/o ports. for details, see section 24, power-down modes. in this state, the external bus release function is halted. to use the external bus release function in sleep mode, the acse bit in mstpcr must be cleare d to 0. conversely, if a sleep instruction to place the chip in all-module-clock-stop mode is ex ecuted in the external bus released state, the transition to all-module-clock-stop mode is de ferred and performed until after the bus is recovered. (3) external bus release function and software standby in this lsi, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip rom, et c., and no external access occurs. if a sleep instruction to place the chip in software standb y mode is executed whil e the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. also, since clock oscillation ha lts in software standby mode, if the breq signal goes low in this mode, indicating an external bus releas e request, the request cannot be answered until the chip has recovered from the software standby mode. note that the back and breqo pins are both in the high-imped ance state in software standby mode. (4) breqo output timing when the breqoe bit is set to 1 and the breqo signal is output, both the breqo and back signals may go low simultaneously. this will occu r if the next external access request occurs while internal bus arbitration is in progress after the chip samples a low level of the breq signal. section 8 bus controller (bsc) rev. 1.00 sep. 13, 2007 page 264 of 1102 rej09b0365-0100 section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 265 of 1102 rej09b0365-0100 section 9 dma controller (dmac) this lsi includes a 4-chan nel dma controller (dmac). 9.1 features ? maximum of 4-g byte address space can be accessed ? byte, word, or longword can be set as data transfer unit ? maximum of 4-g bytes (4,294,967,295 bytes) can be set as total transfer size supports free-running mode in which tota l transfer size setting is not needed ? dmac activation methods are auto -request, on-chip module interr upt, and external request. auto request: cpu activates (cycle st ealing or burst access can be selected) on-chip module interrupt: interrupt requests from on-chip peripheral modules can be selected as an activation source external request: low level or falling edge detection of the dreq signal can be selected. external request is available for all four channels. ? dual or single address mode can be selected as address mode dual address mode: both source and de stination are specified by addresses single address mode: either source or destination is specified by the dreq signal and the other is specified by address ? normal, repeat, or block transfer ca n be selected as transfer mode normal transfer mode: one byte, one word, or one longword data is transferred at a single transfer request repeat transfer mode: one byte, one word, or one longword data is transferred at a single transfer request repeat size of data is transfer red and then a transfer address returns to the transfer start address up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size block transfer mode: one block data is transferred at a single transfer request up to 65,536 bytes/words/longwords can be set as block size section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 266 of 1102 rej09b0365-0100 ? extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available one bit (two bytes) to 27 bits (128 mbytes) for transfer source and destination can be set as extended repeat areas ? address update can be selected from fixed address, offset additio n, and increment or decrement by 1, 2, or 4 address update by offset addition enables to tr ansfer data at addresses which are not placed continuously ? word or longword data can be transferred to an address which is not aligned with the respective boundary data is divided according to its address (byte or word) when it is transferred ? two types of interrupts ca n be requested to the cpu a transfer end interrupt is genera ted after the number of data sp ecified by the transfer counter is transferred. a transfer esca pe end interrupt is generated wh en the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 267 of 1102 rej09b0365-0100 a block diagram of the dmac is shown in figure 9.1. external pins dreqn dackn tendn interrupt signals requested to the cpu by each channel internal activation sources internal activation source detector controller dmdr_n dmrsr_n dacr_n dofr_n internal address bus internal data bus dsar_n ddar_n dtcr_n dbsr_n module data bus address buffer data buffer operation unit operation unit ... [legend] dsar_n: dma source address register dreqn : dma transfer request ddar_n: dma destination address register dackn : dma transfer acknowledge dofr_n: dma offset register tendn : dma transfer end dtcr_n: dma transfer count register n = 0 to 3 dbsr_n: dma block size register dmdr_n: dma mode control register dacr_n: dma address control register dmrsr_n: dma module request select register figure 9.1 block diagram of dmac section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 268 of 1102 rej09b0365-0100 9.2 input/output pins table 9.1 shows the pin configuration of the dmac. table 9.1 pin configuration channel pin name abbr. i/o function 0 dma transfer request 0 dreq0 input channel 0 external request dma transfer acknowledge 0 dack0 output channel 0 single address transfer acknowledge dma transfer end 0 tend0 output channel 0 transfer end 1 dma transfer request 1 dreq1 input channel 1 external request dma transfer acknowledge 1 dack1 output channel 1 single address transfer acknowledge dma transfer end 1 tend1 output channel 1 transfer end 2 dma transfer request 2 dreq2 input channel 2 external request dma transfer acknowledge 2 dack2 output channel 2 single address transfer acknowledge dma transfer end 2 tend2 output channel 2 transfer end 3 dma transfer request 3 dreq3 input channel 3 external request dma transfer acknowledge 3 dack3 output channel 3 single address transfer acknowledge dma transfer end 3 tend3 output channel 3 transfer end section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 269 of 1102 rej09b0365-0100 9.3 register descriptions the dmac has the following registers. channel 0: ? dma source address register_0 (dsar_0) ? dma destination address register_0 (ddar_0) ? dma offset register_0 (dofr_0) ? dma transfer count re gister_0 (dtcr_0) ? dma block size register_0 (dbsr_0) ? dma mode control register_0 (dmdr_0) ? dma address control register_0 (dacr_0) ? dma module request select register_0 (dmrsr_0) channel 1: ? dma source address register_1 (dsar_1) ? dma destination address register_1 (ddar_1) ? dma offset register_1 (dofr_1) ? dma transfer count re gister_1 (dtcr_1) ? dma block size register_1 (dbsr_1) ? dma mode control register_1 (dmdr_1) ? dma address control register_1 (dacr_1) ? dma module request select register_1 (dmrsr_1) channel 2: ? dma source address register_2 (dsar_2) ? dma destination address register_2 (ddar_2) ? dma offset register_2 (dofr_2) ? dma transfer count re gister_2 (dtcr_2) ? dma block size register_2 (dbsr_2) ? dma mode control register_2 (dmdr_2) ? dma address control register_2 (dacr_2) ? dma module request select register_2 (dmrsr_2) section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 270 of 1102 rej09b0365-0100 channel 3: ? dma source address register_3 (dsar_3) ? dma destination address register_3 (ddar_3) ? dma offset register_3 (dofr_3) ? dma transfer count re gister_3 (dtcr_3) ? dma block size register_3 (dbsr_3) ? dma mode control register_3 (dmdr_3) ? dma address control register_3 (dacr_3) ? dma module request select register_3 (dmrsr_3) 9.3.1 dma source addr ess register (dsar) dsar is a 32-bit readable/writable register that specifies the transfer source address. dsar updates the transfer source addres s every time data is transferred. when ddar is specified as the destination address (the dirs bit in dacr is 1) in single address mode, dsar is ignored. although dsar can always be read from by the cpu, it must be read from in longwords and must not be written to while data for the channel is being transferred. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 271 of 1102 rej09b0365-0100 9.3.2 dma destination address register (ddar) ddar is a 32-bit readable/writable register that specifies the transfer de stination address. ddar updates the transfer destination ad dress every time data is transferre d. when dsar is specified as the source address (the dirs bit in dacr is 0) in single address mode, ddar is ignored. although ddar can always be read from by the cpu, it must be read from in longwords and must not be written to while data fo r the channel is being transferred. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 272 of 1102 rej09b0365-0100 9.3.3 dma offset register (dofr) dofr is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. although different values are specified for individual channels, the same values must be specified for the source an d destination sides of a single channel. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 273 of 1102 rej09b0365-0100 9.3.4 dma transfer count register (dtcr) dtcr is a 32-bit readable/writable re gister that specifies the size of data to be transferred (total transfer size). to transfer 1-byte data in total, set h'00000001 in dtcr. when h'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred wi th the transf er counter stopped (free running mo de). when h'ffffffff is set, the total transfer size is 4 gbytes (4,294,967,295), which is the maximum size. while data is being transferred, this register indicates the remaining transfer size. the value co rresponding to its data access size is subtracted every time data is transferred (byte: ? 1, word: ? 2, and longword: ? 4). although dtcr can always be read from by the cpu, it must be read from in longwords and must not be written to while data for the channel is being transferred. 31 0 r/w 30 0 r/w 29 0 r/w 28 0 r/w 27 0 r/w 24 0 r/w 26 0 r/w 25 0 r/w bit bit name initial value r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 16 0 r/w 18 0 r/w 17 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 274 of 1102 rej09b0365-0100 9.3.5 dma block size register (dbsr) dbsr specifies the repeat size or block size. dbsr is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. 31 bkszh31 0 r/w 30 bkszh30 0 r/w 29 bkszh29 0 r/w 28 bkszh28 0 r/w 27 bkszh27 0 r/w 24 bkszh24 0 r/w 26 bkszh26 0 r/w 25 bkszh25 0 r/w bit bit name initial value r/w 23 bkszh23 0 r/w 22 bkszh22 0 r/w 21 bkszh21 0 r/w 20 bkszh20 0 r/w 19 bkszh19 0 r/w 16 bkszh16 0 r/w 18 bkszh18 0 r/w 17 bkszh17 0 r/w bit bit name initial value r/w 15 bksz15 0 r/w 14 bksz14 0 r/w 13 bksz13 0 r/w 12 bksz12 0 r/w 11 bksz11 0 r/w 8 bksz8 0 r/w 10 bksz10 0 r/w 9 bksz9 0 r/w bit bit name initial value r/w 7 bksz7 0 r/w 6 bksz6 0 r/w 5 bksz5 0 r/w 4 bksz4 0 r/w 3 bksz3 0 r/w 0 bksz0 0 r/w 2 bksz2 0 r/w 1 bksz1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 31 to 16 bkszh31 to bkszh16 undefined r/w specify the repeat size or block size. when h'0001 is set, the repeat or block size is one byte, one word, or one longword. when h'0000 is set, it means the maximum value (refer to table 9.1). while the dma is in operation, the setting is fixed. 15 to 0 bksz15 to bksz0 undefined r/w indicate the remaining repeat or block size while the dma is in operation. the value is decremented by 1 every time data is transferred. when the remaining size becomes 0, the value of t he bkszh bits is loaded. set the same value as the bkszh bits. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 275 of 1102 rej09b0365-0100 table 9.2 data access size, va lid bits, and settable size mode data access size bkszh valid bits bksz valid bits settable size (byte) byte 31 to 16 15 to 0 1 to 65,536 repeat transfer and block transfer word 2 to 131,072 longword 4 to 262,144 9.3.6 dma mode control register (dmdr) dmdr controls the dmac operation. ? dmdr_0 31 dte 0 r/w 30 dacke 0 r/w 29 tende 0 r/w 28 ? 0 r/w 27 dreqs 0 r/w 24 ? 0 r 26 nrd 0 r/w 25 ? 0 r bit bit name initial value r/w 23 act 0 r 22 ? 0 r 21 ? 0 r 20 ? 0 r 19 errf 0 r/(w) * 16 dtif 0 r/(w) * 18 ? 0 r 17 esif 0 r/(w) * bit bit name initial value r/w 15 dtsz1 0 r/w 14 dtsz0 0 r/w 13 mds1 0 r/w 12 mds0 0 r/w 11 tseie 0 r/w 8 dtie 0 r/w 10 ? 0 r 9 esie 0 r/w bit bit name initial value r/w 7 dtf1 0 r/w 6 dtf0 0 r/w 5 dta 0 r/w 4 ? 0 r 3 ? 0 r 0 dmap0 0 r/w 2 dmap2 0 r/w 1 dmap1 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit after having been read as 1, to clear the flag. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 276 of 1102 rej09b0365-0100 ? dmdr_1 to dmdr_3 31 dte 0 r/w 30 dacke 0 r/w 29 tende 0 r/w 28 ? 0 r/w 27 dreqs 0 r/w 24 ? 0 r 26 nrd 0 r/w 25 ? 0 r bit bit name initial value r/w 23 act 0 r 22 ? 0 r 21 ? 0 r 20 ? 0 r 19 ? 0 r 16 dtif 0 r/(w) * 18 ? 0 r 17 esif 0 r/(w) * bit bit name initial value r/w 15 dtsz1 0 r/w 14 dtsz0 0 r/w 13 mds1 0 r/w 12 mds0 0 r/w 11 tseie 0 r/w 8 dtie 0 r/w 10 ? 0 r 9 esie 0 r/w bit bit name initial value r/w 7 dtf1 0 r/w 6 dtf0 0 r/w 5 dta 0 r/w 4 ? 0 r 3 ? 0 r 0 dmap0 0 r/w 2 dmap2 0 r/w 1 dmap1 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit after having been read as 1, to clear the flag. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 277 of 1102 rej09b0365-0100 bit bit name initial value r/w description 31 dte 0 r/w data transfer enable enables/disables a data transfer for the corresponding channel. when this bit is set to 1, it indicates that the dmac is in operation. setting this bit to 1 starts a transfer when the auto- request is selected. when the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. while data is being transferred, clearing this bit to 0 stops the transfer. in block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. if an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. operating modes and transfer methods must not be changed while this bit is set to 1. 0: disables a data transfer 1: enables a data transfer (dma is in operation) [clearing conditions] ? when the specified total transfer size of transfers is completed ? when a transfer is stopped by an overflow interrupt by a repeat size end ? when a transfer is stopped by an overflow interrupt by an extended repeat size end ? when a transfer is stopped by a transfer size error interrupt ? when clearing this bit to 0 to stop a transfer in block transfer mode, this bit changes after the current block transfer. ? when an address error or an nmi interrupt is requested ? in the reset state or hardware standby mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 278 of 1102 rej09b0365-0100 bit bit name initial value r/w description 30 dacke 0 r/w dack signal output enable enables/disables the dack signal output in single address mode. this bit is ignored in dual address mode. 0: disables dack signal output 1: enables dack signal output 29 tende 0 r/w tend signal output enable enables/disables the tend signal output. 0: disables tend signal output 1: enables tend signal output 28 ? 0 r/w reserved initial value should not be changed. 27 dreqs 0 r/w dreq select selects whether a low level or the falling edge of the dreq signal used in external request mode is detected. 0: low level detection 1: falling edge detection (the first transfer after a transfer enabled is detected on a low level) 26 nrd 0 r/w next request delay selects the accepting timing of the next transfer request. 0: starts accepting the next transfer request after completion of the current transfer 1: starts accepting the next transfer request one cycle after completion of the current transfer 25, 24 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 23 act 0 r active state indicates the operating state for the channel. 0: waiting for a transfer request or a transfer disabled state by clearing the dte bit to 0 1: active state 22 to 20 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 279 of 1102 rej09b0365-0100 bit bit name initial value r/w description 19 errf 0 r/(w) * system error flag indicates that an address error or an nmi interrupt has been generated. this bit is available only in dmdr_0. setting this bit to 1 prohibits writing to the dte bit for all the channels. this bit is reserved in dmdr_1 to dmdr_3. it is always read as 0 and cannot be modified. 0: an address error or an nmi interrupt has not been generated 1: an address error or an nmi interrupt has been generated [clearing condition] ? when clearing to 0 after reading errf = 1 [setting condition] ? when an address error or an nmi interrupt has been generated however, when an address error or an nmi interrupt has been generated in dmac module stop mode, this bit is not set to 1. 18 ? 0 r reserved this bit is always read as 0 and cannot be modified. 17 esif 0 r/(w) * transfer escape interrupt flag indicates that a transfer escape end interrupt has been requested. a transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: a transfer escape end interrupt has not been requested 1: a transfer escape end interrupt has been requested [clearing conditions] ? when setting the dte bit to 1 ? when clearing to 0 before reading esif = 1 [setting conditions] ? when a transfer size error interrupt is requested ? when a repeat size end interrupt is requested ? when a transfer end interrupt by an extended repeat area overflow is requested section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 280 of 1102 rej09b0365-0100 bit bit name initial value r/w description 16 dtif 0 r/(w) * data transfer interrupt flag indicates that a transfer end interrupt by the transfer counter has been requested. 0: a transfer end interrupt by the transfer counter has not been requested 1: a transfer end interrupt by the transfer counter has been requested [clearing conditions] ? when setting the dte bit to 1 ? when clearing to 0 after reading dtif = 1 [setting condition] ? when dtcr reaches 0 and the transfer is completed 15 14 dtsz1 dtsz0 0 0 r/w r/w data access size 1 and 0 select the data access size for a transfer. 00: byte size (eight bits) 01: word size (16 bits) 10: longword size (32 bits) 11: setting prohibited 13 12 mds1 mds0 0 0 r/w r/w transfer mode select 1 and 0 select the transfer mode. 00: normal transfer mode 01: block transfer mode 10: repeat transfer mode 11: setting prohibited section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 281 of 1102 rej09b0365-0100 bit bit name initial value r/w description 11 tseie 0 r/w transfer size error interrupt enable enables/disables a transfer size error interrupt. when the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the dte bit is cleared to 0. at this time, the esif bit is set to 1 to indica te that a transfer size error interrupt has been requested. the sources of a transfer size error are as follows: ? in normal or repeat transfer mode, the total transfer size set in dtcr is less than the data access size ? in block transfer mode, the total transfer size set in dtcr is less than the block size 0: disables a transfer size error interrupt request 1: enables a transfer size error interrupt request 10 ? 0 r reserved this bit is always read as 0 and cannot be modified. 9 esie 0 r/w transfer escape interrupt enable enables/disables a transfer escape end interrupt request. when the esif bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the cpu or dtc. the transfer end interrupt request is cleared by clearing this bit or the esif bit to 0. 0: disables a transfer escape end interrupt 1: enables a transfer escape end interrupt 8 dtie 0 r/w data transfer end interrupt enable enables/disables a transfer end interrupt request by the transfer counter. when the dtif bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the cpu or dtc. the transfer end interrupt request is cleared by clearing this bit or the dtif bit to 0. 0: disables a transfer end interrupt 1: enables a transfer end interrupt section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 282 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 6 dtf1 dtf0 0 0 r/w r/w data transfer factor 1 and 0 select a dmac activation source. when the on-chip peripheral module setting is selected, the interrupt source should be selected by dmrsr. when the external request setting is selected, the sampling method should be selected by the dreqs bit. 00: auto request (cycle stealing) 01: auto request (burst access) 10: on-chip module interrupt 11: external request 5 dta 0 r/w data transfer acknowledge this bit is valid in dma transfer by the on-chip module interrupt source. this bit enables or disables to clear the source flag selected by dmrsr. 0: to clear the source in dma transfer is disabled. since the on-chip module interrupt source is not cleared in dma transfer, it should be cleared by the cpu or dtc transfer. 1: to clear the source in dma transfer is enabled. since the on-chip module interrupt source is cleared in dma transfer, it does not require an interrupt by the cpu or dtc transfer. 4, 3 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 283 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 1 0 dmap2 dmap1 dmap0 0 0 0 r/w r/w r/w dma priority level 2 to 0 select the priority level of the dmac when using the cpu priority control function over dtc and dmac. when the cpu has priority over the dmac, the dmac masks a transfer request and waits for the timing when the cpu priority becomes lower than the dmac priority. the priority levels can be set to the individual channels. this bit is valid when the cpupce bit in cpupcr is set to 1. 000: priority level 0 (low) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (high) note: * only 0 can be written to, to clear the flag. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 284 of 1102 rej09b0365-0100 9.3.7 dma address control register (dacr) dacr specifies the operating mode and transfer method. 31 ams 0 r/w 30 dirs 0 r/w 29 ? 0 r 28 ? 0 r 27 ? 0 r 24 ars0 0 r/w 26 rptie 0 r/w 25 ars1 0 r/w bit bit name initial value r/w 23 ? 0 r 22 ? 0 r 21 sat1 0 r/w 20 sat0 0 r/w 19 ? 0 r 16 dat0 0 r/w 18 ? 0 r 17 dat1 0 r/w bit bit name initial value r/w 15 sarie 0 r/w 14 ? 0 r 13 ? 0 r 12 sara4 0 r/w 11 sara3 0 r/w 8 sara0 0 r/w 10 sara2 0 r/w 9 sara1 0 r/w bit bit name initial value r/w 7 darie 0 r/w 6 ? 0 r 5 ? 0 r 4 dara4 0 r/w 3 dara3 0 r/w 0 dara0 0 r/w 2 dara2 0 r/w 1 dara1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 31 ams 0 r/w address mode select selects address mode from single or dual address mode. in single address mode, the dack pin is enabled according to the dacke bit. 0: dual address mode 1: single address mode 30 dirs 0 r/w single address direction select specifies the data transfer direction in single address mode. this bit s ignored in dual address mode. 0: specifies dsar as source address 1: specifies ddar as destination address 29 to 27 ? 0 r/w reserved these bits are always read as 0 and cannot be modified. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 285 of 1102 rej09b0365-0100 bit bit name initial value r/w description 26 rptie 0 r/w repeat size end interrupt enable enables/disables a repeat size end interrupt request. in repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate that a repeat size end interrupt is requested. even when the re peat area is not specified (ars1 = 1 and ars0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. in addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate that a repeat size end interrupt is requested. 0: disables a repeat size end interrupt 1: enables a repeat size end interrupt 25 24 ars1 ars0 0 0 r/w r/w area select 1 and 0 specify the block area or repeat area in block or repeat transfer mode. 00: specify the block area or repeat area on the source address 01: specify the block area or repeat area on the destination address 10: do not specify the block area or repeat area 11: setting prohibited 23, 22 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 21 20 sat1 sat0 0 0 r/w r/w source address update mode 1 and 0 select the update method of the source address (dsar). when dsar is not specified as the transfer source in single address mode, this bit is ignored. 00: source address is fixed 01: source address is updated by adding the offset 10: source address is updated by adding 1, 2, or 4 according to the data access size 11: source address is updated by subtracting 1, 2, or 4 according to the data access size section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 286 of 1102 rej09b0365-0100 bit bit name initial value r/w description 19, 18 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 17 16 dat1 dat0 0 0 r/w r/w destination address update mode 1 and 0 select the update method of the destination address (ddar). when ddar is not specified as the transfer destination in single address mode, this bit is ignored. 00: destination address is fixed 01: destination address is upda ted by adding the offset 10: destination address is upda ted by adding 1, 2, or 4 according to the data access size 11: destination address is upda ted by subtracting 1, 2, or 4 according to the data access size 15 sarie 0 r/w interrupt enable for source address extended area overflow enables/disables an interrupt request for an extended area overflow on the source address. when an extended repeat area overflow on the source address occurs while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. when block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. when setting the dte bit in dmdr of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. when the extended repeat area is not specified, this bit is ignored. 0: disables an interrupt request for an extended area overflow on the source address 1: enables an interrupt request for an extended area overflow on the source address 14, 13 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 287 of 1102 rej09b0365-0100 bit bit name initial value r/w description 12 11 10 9 8 sara4 sara3 sara2 sara1 sara0 0 0 0 0 0 r/w r/w r/w r/w r/w source address extended repeat area specify the extended repeat area on the source address (dsar). with the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. the extended repeat area size is specified from four bytes to 128 mbytes in units of byte and a power of 2. when the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. when an overflow in the extended repeat area occurs with the sarie bit set to 1, an interrupt can be requested. table 9.3 shows the settings and areas of the extended repeat area. 7 darie 0 r/w destination address extended repeat area overflow interrupt enable enables/disables an interrupt request for an extended area overflow on the destination address. when an extended repeat area overflow on the destination address occurs while this bit is set to 1, the dte bit in dmdr is cleared to 0. at this time, the esif bit in dmdr is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. when block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. when setting the dte bit in dmdr of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. when the extended repeat area is not specified, this bit is ignored. 0: disables an interrupt request for an extended area overflow on the destination address 1: enables an interrupt request for an extended area overflow on the destination address 6, 5 ? all 0 r reserved these bits are always read as 0 and cannot be modified. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 288 of 1102 rej09b0365-0100 bit bit name initial value r/w description 4 3 2 1 0 dara4 dara3 dara2 dara1 dara0 0 0 0 0 0 r/w r/w r/w r/w r/w destination address extended repeat area specify the extended rep eat area on the destination address (ddar). with the ex tended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. the extended repeat area size is specified from four bytes to 128 mbytes in units of byte and a power of 2. when the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. when an overflow in the extended repeat area occurs with the darie bit set to 1, an interrupt can be requested. table 9.3 shows the settings and areas of the extended repeat area. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 289 of 1102 rej09b0365-0100 table 9.3 settings and areas of extended repeat area sara4 to sara0 or dara4 to dara0 extended repeat area 00000 not specified 00001 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011 8 bytes specified as extended repeat area by the lower 3 bits of the address 00100 16 bytes specified as extended repeat area by the lower 4 bits of the address 00101 32 bytes specified as extended repeat area by the lower 5 bits of the address 00110 64 bytes specified as extended repeat area by the lower 6 bits of the address 00111 128 bytes specified as extended repeat area by the lower 7 bits of the address 01000 256 bytes specified as extended repeat area by the lower 8 bits of the address 01001 512 bytes specified as extended repeat area by the lower 9 bits of the address 01010 1 kbyte specified as extended repeat area by the lower 10 bits of the address 01011 2 kbytes specified as extended repeat area by the lower 11 bits of the address 01100 4 kbytes specified as extended repeat area by the lower 12 bits of the address 01101 8 kbytes specified as extended repeat area by the lower 13 bits of the address 01110 16 kbytes specified as extended repeat ar ea by the lower 14 bits of the address 01111 32 kbytes specified as extended repeat ar ea by the lower 15 bits of the address 10000 64 kbytes specified as extended repeat ar ea by the lower 16 bits of the address 10001 128 kbytes specified as extended repeat area by the lower 17 bits of the address 10010 256 kbytes specified as extended repeat area by the lower 18 bits of the address 10011 512 kbytes specified as extended repeat area by the lower 19 bits of the address 10100 1 mbyte specified as extended repeat area by the lower 20 bits of the address 10101 2 mbytes specified as extended repeat area by the lower 21 bits of the address 10110 4 mbytes specified as extended repeat area by the lower 22 bits of the address 10111 8 mbytes specified as extended repeat area by the lower 23 bits of the address 11000 16 mbytes specified as extended repeat ar ea by the lower 24 bits of the address 11001 32 mbytes specified as extended repeat ar ea by the lower 25 bits of the address 11010 64 mbytes specified as extended repeat ar ea by the lower 26 bits of the address 11011 128 mbytes specified as extended repeat area by the lower 27 bits of the address 111 setting prohibited [legend] : don't care section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 290 of 1102 rej09b0365-0100 9.3.8 dma module request select register (dmrsr) dmrsr is an 8-bit readable/writable register th at specifies the on-chip module interrupt source. the vector number of the interrupt source is specified in eight bits. however, 0 is regarded as no interrupt source. for the vector numbers of the interrupt sources, refer to table 9.5. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit bit name initial value r/w 9.4 transfer modes table 9.4 shows the dmac transfer modes. the tran sfer modes can be specifi ed to the individual channels. table 9.4 transfer modes address register address mode transfer mode activati on source common function source destina- tion dual address ? normal transfer ? repeat transfer ? block transfer repeat or block size = 1 to 65,536 bytes, 1 to 65,536 words, or 1 to 65,536 longwords ? auto request (activated by cpu) ? on-chip module interrupt ? external request ? total transfer size: 1 to 4 gbytes or not specified ? offset addition ? extended repeat area function dsar ddar single address ? instead of specifying the source or destination address registers, data is directly tr ansferred from/to the external device using the dack pin ? the same settings as above are available other than address register setting (e.g., above transfer modes can be specified) ? one transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) dsar/ dack dack / ddar section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 291 of 1102 rej09b0365-0100 when the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. when the total transfer size is not specified (dtcr = h'00000000), the transfer counter is stopped and the transfer is continue d without the limitation of the transfer count. 9.5 operations 9.5.1 address modes (1) dual address mode in dual address mode, the transfer source address is specified in ds ar and the transfer destination address is specified in ddar. a tr ansfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more th an two because one bus cycle is divided into multiple bus cycles). in the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. the read and write cycles are not separated. othe r bus cycles (bus cycle by other bus masters, refresh cycle, and extern al bus release cycle) are not generated between read and write cycles. the tend signal output is enabled or disabled by the tende bit in dmdr. the tend signal is output in two bus cycles. when an idle cycle is inserted before the bus cycle, the tend signal is also output in the idle cycle. the dack signal is not output. figure 9.2 shows an example of the signal timing in dual address mode and figure 9.3 shows the operation in dual address mode. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 292 of 1102 rej09b0365-0100 address bus b rd wr tend dma read cycle dma write cycle dsar ddar figure 9.2 example of signal timing in dual address mode transfer address t a address b a address update setting is as follows: source address increment fixed destination address address t b figure 9.3 operations in dual address mode (2) single address mode in single address mode, data between an external device and an external memory is directly transferred using the dack pin instead of dsar or ddar. a transfer at a time is performed in one bus cycle. in this mode, the data bus widt h must be the same as the data access size. for details on the data bus width, see section 8, bus controller (bsc). the dmac accesses an external device as the tr ansfer source or destination by outputting the strobe signal ( dack ) to the external device with dack and accesses the other transfer target by outputting the address. accordingly, the dma transf er is performed in one bus cycle. figure 9.4 shows an example of a transfer between an exte rnal memory and an external device with the dack pin. in this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 293 of 1102 rej09b0365-0100 the transfer direction is decided by the dirs bit in dacr which sp ecifies an external device with the dack pin as the transfer source or destination. when dirs = 0, data is transferred from an external memory (dsar) to an external device with the dack pin. when dirs = 1, data is transferred from an ex ternal device with the dack pin to an external memory (ddar). the settings of registers which are not used as th e transfer source or de stination are ignored. the dack signal output is enabled in single address mode by the dacke bit in dmdr. the dack signal is low active. the tend signal output is enabled or disabled by the tende bit in dmdr. the tend signal is output in one bus cycle. when an idle cycl e is inserted before the bus cycle, the tend signal is also output in the idle cycle. figure 9.5 shows an example of timing charts in single address mode and figure 9.6 shows an example of operation in single address mode. lsi data flow external address bus external data bus dmac dack dreq external memory external device with dack figure 9.4 data flow in single address mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 294 of 1102 rej09b0365-0100 dma cycle dsar address for external memory space rd signal for external memory space data output by external memory address bus b rd wr dack tend data bus dma cycle ddar address for external memory space wr signal for external memory space b address bus transfer from external memory to external device with dack rd wr dack tend data bus data output by external device with dac k transfer from external device with dack to external memory high high figure 9.5 example of signal timing in single address mode transfer address t address b dac k figure 9.6 operations in single address mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 295 of 1102 rej09b0365-0100 9.5.2 transfer modes (1) normal transfer mode in normal transfer mode, one data access size of data is transferred at a single transfer request. up to 4 gbytes can be specified as a total transfer size by dtcr. dbsr is ignored in normal transfer mode. the tend signal is output only in the last dma transfer. the dack signal is output every time a transfer request is received and a transfer starts. figure 9.7 shows an example of the signal timing in normal transfer mode and figure 9.8 shows the operation in normal transfer mode. read write read write dma transfer cycle last dma transfer cycle bus cycle auto request transfer in dual address mode: external request transfer in single address mode: tend dma dma dreq bus cycle dack figure 9.7 example of signal timing in normal transfer mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 296 of 1102 rej09b0365-0100 transfer total transfer size (dtcr) address t a address b a address t b address b b figure 9.8 operations in normal transfer mode (2) repeat transfer mode in repeat transfer mode, one data access size of data is transferred at a singl e transfer request. up to 4 gbytes can be specified as a total transfer size by dtcr. the repeat size can be specified in dbsr up to 65536 data access size. the repeat area can be specified for the source or destination address side by bits ars1 and ars0 in dacr. the addr ess specified as the repeat area returns to the transfer star t address when the repeat size of transfers is comp leted. this operation is repeated until the total transfer size specified in dtcr is completed. when h'00000000 is specified in dtcr, it is regarded as the free running mode and repeat transfer is conti nued until the dte bit in dmdr is cleared to 0. in addition, a dma transfer can be stopped and a repeat size end interrupt can be requested to the cpu or dtc when the repeat size of transfers is completed. when the next transfer is requested after completion of a 1-repeat size data transfer while the rptie bit is set to 1, the dte bit in dmdr is cleared to 0 and the esif bit in dmdr is set to 1 to complete the transfer. at this time, an interrupt is requested to the cpu or dtc when the esie bit in dmdr is set to 1. the timings of the tend and dack signals are the same as in normal transfer mode. figure 9.9 shows the operation in repeat transfer mode while dual address mode is set. when the repeat area is specified as neither sour ce nor destination address side, the operation is the same as the normal transfer mode operation shown in figure 9.8. in this case, a repeat size end interrupt can also be requested to the cpu when the repeat size of transfers is completed. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 297 of 1102 rej09b0365-0100 transfer address t a address t b address b b address b a operation when the repeat area is specified to the source side repeat size = bkszh data access size total transfer size (dtcr) figure 9.9 operations in repeat transfer mode (3) block transfer mode in block transfer mode, one block size of data is transferred at a single transfer request. up to 4 gbytes can be specified as total transfer size by dtcr. the block size can be specified in dbsr up to 65536 data access size. while one block of data is being transferred, transfer requests from other channels are suspended. when the transfer is completed, the bu s is released to the other bus master. the block area can be specified fo r the source or destination address side by bits ars1 and ars0 in dacr. the addres s specified as the block area returns to the transfer star t address when the block size of data is completed. when the block area is specified as neither source nor destination address side, the operation continues without return ing the address to the tr ansfer start address. a repeat size end interrupt can be requested. the tend signal is output every time 1-block data is transferred in the last dma transfer cycle. when an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. for details, see section 9.5.5, extended repeat area function. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 298 of 1102 rej09b0365-0100 figure 9.10 shows an example of the dma transf er timing in block transfer mode. the transfer conditions are as follows: ? address mode: single address mode ? data access size: byte ? 1-block size: three bytes the block transfer mode operations in single address mode and in dual address mode are shown in figures 9.11 and 9.12, respectively. cpu cpu dmac dmac dmac cpu bus cycle tend dreq no cpu cycle generated transfer cycles for one block figure 9.10 operations in block transfer mode transfer address t address b dac k block bkszh data access size figure 9.11 operation in single a ddress mode in block transfer mode (block area specified) section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 299 of 1102 rej09b0365-0100 transfer address t a address b a address t b address b b nth block second block first block nth block second block first block bkszh data access size total transfer size (dtcr) figure 9.12 operation in dual a ddress mode in block transfer mode (block area not specified) section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 300 of 1102 rej09b0365-0100 9.5.3 activation sources the dmac is activated by an auto request, an on -chip module interrupt, and an external request. the activation source is specified by bits dtf1 and dtf0 in dmdr. (1) activation by auto request the auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. a transfer request is automatically generated inside the dmac. in auto request activation, setting the dte bit in dmdr starts a transfer. the bus mode can be selected from cycle steal ing and burst modes. (2) activation by on-chip module interrupt an interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. when a dma transfer is enabled (dte = 1), the dma transfer is started by an on-chip module interrupt. the activation source of the on-chip module inte rrupt is selected by the dma module request select register (dmrsr). the ac tivation sources are specified to the individual channels. table 9.5 is a list of on-chip module interrupts for the dmac. the interrupt request selected as the activation source can generate an interrupt request simultaneously to the cpu or dtc. for details, refer to section 6, interrupt controller. the dmac receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. therefore, the dmac is not affected by priority given in the interrupt controller. when the dmac is activated while dta = 1, the in terrupt request flag is automatically cleared by a dma transfer. if multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interr upt request flag is cleared. in this case, other channels may not be activated because the tr ansfer request is not held in the dmac. when the dmac is activated while dta = 0, the interrupt request flag is not cleared by the dmac and should be cleared by the cpu or dtc transfer. when an activation source is selected while dte = 0, the activation source does not request a transfer to the dmac. it requests an interrupt to the cpu or dtc. in addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the dte bit. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 301 of 1102 rej09b0365-0100 table 9.5 list of on-chip module interrupts to dmac on-chip module interrupt source on-chip module dmrsr (vector number) adi0 (conversion end interrupt for a/d converter unit 0) a/d_0 86 tgi0a (tgi0a input capture/compare match) tpu_0 88 tgi1a (tgi1a input capture/compare match) tpu_1 93 tgi2a (tgi2a input capture/compare match) tpu_2 97 tgi3a (tgi3a input capture/compare match) tpu_3 101 tgi4a (tgi4a input capture/compare match) tpu_4 106 tgi5a (tgi5a input capture/compare match) tpu_5 110 rxi0 (receive data full interrupt for sci channel 0) sci_0 145 txi0 (transmit data empty interr upt for sci channel 0) sci_0 146 rxi1 (receive data full interrupt for sci channel 1) sci_1 149 txi1 (transmit data empty interr upt for sci channel 1) sci_1 150 rxi2 (receive data full interrupt for sci channel 2) sci_2 153 txi2 (transmit data empty interr upt for sci channel 2) sci_2 154 rxi3 (receive data full interrupt for sci channel 3) sci_3 157 txi3 (transmit data empty interr upt for sci channel 3) sci_3 158 rxi4 (receive data full interrupt for sci channel 4) sci_4 161 txi4 (transmit data empty interr upt for sci channel 4) sci_4 162 tgi6a (tgi6a input capture/compare match) tpu_6 164 tgi7a (tgi7a input capture/compare match) tpu_7 169 tgi8a (tgi8a input capture/compare match) tpu_8 173 tgi9a (tgi9a input capture/compare match) tpu_9 177 tgi10a (tgi10a input capture/compare match) tpu_10 182 tgi11a (tgi11a input capture/compare match) tpu_11 188 rxi5 (receive data full interrupt for sci channel 5) sci_5 220 txi5 (transmit data empty interr upt for sci channel 5) sci_5 221 rxi6 (receive data full interrupt for sci channel 6) sci_6 224 txi6 (transmit data empty interr upt for sci channel 6) sci_6 225 adi2 (conversion end interrupt for a/d converter unit 2) a/d_2 232 adi1 (conversion end interrupt for a/d converter unit 1) a/d_1 237 section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 302 of 1102 rej09b0365-0100 (3) activation by external request a transfer is started by a transfer request signal ( dreq ) from an external device. when a dma transfer is enabled (dte = 1), th e dma transfer is started by the dreq assertion. when a dma transfer between on-chip peripheral modules is performed, select an activ ation source from the auto request and on-chip module interrupt (the external request cannot be used). a transfer request signal is input to the dreq pin. the dreq signal is detected on the falling edge or low level. whether the falling edge or low level detection is used is selected by the dreqs bit in dmdr. when an external request is selected as an ac tivation source, clear the ddr bit to 0 and set the icr bit to 1 for the corresponding pin. for details, see section 11, i/o ports. 9.5.4 bus access modes there are two types of bus access modes: cycle stealing and burst. when an activation source is the au to request, the cycle stealing or burst mode is selected by bit dtf0 in dmdr. when an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) cycle stealing mode in cycle stealing mode, the dmac releases the bu s every time one unit of transfers ( byte, word, longword, or 1-block size) is completed. after that, when a transfer is requested, the dmac obtains the bus to transfer 1-unit data and then re leases the bus on completi on of the transfer. this operation is continued until the transfer end condition is satisfied. when a transfer is requested to another channe l during a dma transfer, the dmac releases the bus and then transfers data for the requested channel. for details on operations when a transfer is requested to multiple channels, see s ection 9.5.8, priority of channels. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 303 of 1102 rej09b0365-0100 figure 9.13 shows an example of timing in cycl e stealing mode. the transfer conditions are as follows: ? address mode: single address mode ? sampling method of the dreq signal: low level detection cpu cpu cpu dmac cpu dmac dreq bus cycle bus released temporarily for the cpu figure 9.13 example of ti ming in cycle stealing mode (2) burst access mode in burst mode, once it takes the bus, the dmac continues a transfer without releasing the bus until the transfer end condition is satisfied. even if a tr ansfer is requested from another channel having priority, the transfer is not stopped once it is star ted. the dmac releases th e bus in the next cycle after the transfer for the channel in burst mode is completed. this is similarly to operation in cycle stealing mode. however, setting the ibccs bit in ibcr of the bus controller makes the dmac release the bus to pass the bus to another bus master. in block transfer mode, the burst mode setting is ignored (operation is the same as that in burst mode during one block of transfers). the dmac is always operated in cycle stealing mode. clearing the dte bit in dmdr stops a dma transfer . a transfer requested before the dte bit is cleared to 0 by the dmac is execu ted. when an interrupt by a tran sfer size error, a repeat size end, or an extended repeat area overflow occurs, the dte bit is cl eared to 0 and the transfer ends. figure 9.14 shows an example of timing in burst mode. cpu cpu cpu cpu dmac dmac dmac bus cycle no cpu cycle generated figure 9.14 example of timing in burst mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 304 of 1102 rej09b0365-0100 9.5.5 extended repeat area function the source and destination address sides can be speci fied as the extended repeat area. the contents of the address register repeat ad dresses within the area specified as the extended repeat area. for example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every tim e the contents reach the end address of the buffer (overflow on the ring buffer address). this operation can automatically be performed using the extended repeat area function of the dmac. the extended repeat areas can be specified inde pendently to the source a ddress register (dsar) and destination address register (ddar). the extended repeat area on the source address is specified by bits sara4 to sara0 in dacr. the extended repeat area on the destination ad dress is specified by bits dara4 to dara0 in dacr. the extended repeat area sizes for ea ch side can be specified independently. a dma transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the cpu when the contents of the address regist er reach the end address of the extended repeat area. when an overflow on the extended repeat area set in dsar occurs while the sarie bit in dacr is set to 1, the esif bit in dmdr is set to 1 and the dte bit in dmdr is cleared to 0 to stop the transfer. at this time, if the esie bit in dmdr is set to 1, an interrupt by an extended repeat area overflow is requested to the cpu. when the darie bit in dacr is set to 1, an overflow on the extended repeat area set in ddar occurs, meaning that the destination side is a target. during the interrupt handling, setting the dte bit in dmdr resumes the transfer. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 305 of 1102 rej09b0365-0100 figure 9.15 shows an example of the extended repeat area operation. external memory when the area represented by the lower three bits of dsar (eight bytes) is specified as the extended repeat area (sara4 to sara0 = b'00011) repeat an interrupt request by extended repeat area overflow can be generated. area specified by dsar h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 ... ... figure 9.15 example of extended repeat area operation when an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. when a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. when an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 306 of 1102 rej09b0365-0100 figure 9.16 shows examples when the extended repeat area function is used in block transfer mode. external memory area specified by dsar 1st block transfer 2nd block transfer h'23fffe h'23ffff h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240008 h'240009 h'240000 h'240001 h'240002 h'240003 h'240004 h'240005 h'240006 h'240007 h'240000 h'240001 h'240002 h'240003 h'240004 h'240000 h'240001 h'240005 h'240006 h'240007 interrupt request generated block transfer continued when the are represented by the lower three bits (eight bytes) of dsar are specified as the extended repeat area (sara4 to sara0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in dtcr = 5). ... ... figure 9.16 example of extended repeat area function in block transfer mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 307 of 1102 rej09b0365-0100 9.5.6 address update function using offset the source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. when the offset addition is select ed, the offset specified by the offset register (dofr) is added to the address every time the dm ac transfers the data access size of data. this function realizes a data transfer where ad dresses are allocated to separated areas. figure 9.17 shows the address update method. 0 + offset 1, 2, or 4 address not updated data access size added to or subtracted from address (addresses are continuous) offset is added to address (addresses are not continuous) (a) address fixed (b) increment or decrement by 1, 2, or 4 (c) offset addition external memory external memory external memory figure 9.17 address update method in item (a), address fixed, the transfer source or destination address is not updated indicating the same address. in item (b), increment or decrem ent by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. byte, word, or longword can be specified as the data access size. the value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. th is operation realizes the data transfer placed in consecutive areas. in item (c), offset addition, th e address update does not depend on the data access size. the offset specified by dofr is added to the address every time the dmac transfers data of the data access size. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 308 of 1102 rej09b0365-0100 the address is calculated by the offset set in dofr and the contents of dsar and ddar. although the dmac calculates only addition, an offs et subtraction can be realized by setting the negative value in dofr. in this case, the negative value must be 2's complement. (1) basic transfer using offset figure 9.18 shows a basic operation of a transfer using the offset addition. data 1 offset address a1 transfer address a2 = address a1 + offset address b1 address b2 = address b1 + 4 address b3 = address b2 + 4 address b4 = address b3 + 4 address b5 = address b4 + 4 address a3 = address a2 + offset address a4 = address a3 + offset address a5 = address a4 + offset offset offset offset transfer source: offset addition transfer destination: increment by 4 (longword) data 1 data 2 data 3 data 4 data 5 : : : : data 2 data 3 data 4 data 5 figure 9.18 operation of offset addition in figure 9.18, the offset addition is selected as the transfer sour ce address update and increment or decrement by 1, 2, or 4 is sel ected as the transfer destination address. the addr ess update means that data at the address which is away from the previous transfer source address by the offset is read from. the data read from the address away from the previo us address is written to the consecutive area in the destination side. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 309 of 1102 rej09b0365-0100 (2) xy conversion using offset figure 9.19 shows the xy conversion using the offset addition in repeat transfer mode. data 1 data 2 data 3 data 4 data 5 data 11 data 12 data 16 data 16 data 15 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 5 data 9 data 13 data 2 data 11 data 15 data 12 data 8 data 4 data 7 data 3 data 14 data 10 data 6 1st transfer 1st transfer 2nd transfer 2nd transfer 3rd transfer 3rd transfer 4th transfer 1st transfer 2nd transfer 3rd transfer 4th transfer data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 2 data 3 data 4 data 15 data 5 data 11 data 12 data 16 data 14 data 13 data 10 data 9 data 8 data 7 data 6 data 1 data 5 data 9 data 13 data 12 data 2 data 11 data 15 data 16 data 8 data 4 data 7 data 3 data 14 data 10 data 6 transfer transfer interrupt request generated interrupt request generated address initialized interrupt request generated address initialized transfer source addresses changed by cpu transfer source addresses changed by cpu offset offset offset figure 9.19 xy conversion op eration using offset addition in repeat transfer mode in figure 9.19, the source address side is specif ied to the repeat area by dacr and the offset addition is selected. the offset value is set to 4 data access size (when the data access size is longword, h'00000010 is set in dofr, as an example). the repeat size is set to 4 data access size (when the data access size is long word, the repeat size is set to 4 4 = 16 bytes, as an example). the increment or decrement by 1, 2, or 4 is specified as the transfer de stination address. a repeat size end interrupt is requested when the repeat size of transfers is completed. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 310 of 1102 rej09b0365-0100 when a transfer starts, the transfer source address is added to the offset every time data is transferred. the transfer data is written to the de stination continuous addresses. when data 4 is transferred meaning that the rep eat size of transfers is complete d, the transfer source address returns to the transfer start addr ess (address of data 1 on the tran sfer source) and a repeat size end interrupt is requested. while this interrupt stops the transfer temp orarily, the contents of dsar are written to the address of data 5 by the cpu (whe n the data access size is longword, write the data 1 address + 4). when the dte bit in dmdr is set to 1, the transfer is resumed from the state when the transfer is stopped. accordin gly, operations are repeated an d the transfer source data is transposed to the destin ation area (xy conversion). figure 9.20 shows a flowchart of the xy conversion. : user operation : dmac operation start set address and transfer count set repeat transfer mode set dte bit to 1 receives transfer request transfers data decrements transfer count and repeat size enable repeat escape interrupt set transfer source address + 4 initializes transfer source address generates repeat size end interrupt request transfer count = 0? repeat size = 0? end no no ye s ye s (longword transfer) figure 9.20 xy conversion flowchart using offset addition in repeat transfer mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 311 of 1102 rej09b0365-0100 (3) offset subtraction when setting the negative value in dofr, the offset value must be 2's complement. the 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) example: 2's complement of h'0001ffff = h'fffe0000 + h'00000001 = h'fffe0001 the value of 2's complement can be obtained by the neg.l instruction. 9.5.7 register during dma transfer the dmac registers are updated by a dma transfer . the value to be updated differs according to the other settings and transfer state. the registers to be updated are dsar, ddar, dtcr, bits bkszh and bksz in dbsr, and the dte, act, errf, esif, and dtif bits in dmdr. (1) dma source address register when the transfer source address set in dsar is accessed, the contents of dsar are output and then are updated to the next address. the increment or decrement can be specified by bits sat1 and sat0 in dacr. when sat1 and sat0 = b'00, the address is fixed. when sat1 and sat0 = b'01, the address is added with the offset. when sat1 and sat0 = b'10, the address is incremented. when sat1 and sat0 = b'11, the address is decremented. the size of incremen t or decrement depends on the data access size. the data access size is specified by bits dtsz 1 and dtsz0 in dmdr. when dtsz1 and dtsz0 = b'00, the data access size is byte and the addres s is incremented or d ecremented by 1. when dtsz1 and dtsz0 = b'01, the data access size is word and the addre ss is incremented or decremented by 2. when dtsz1 and dtsz0 = b'10, the data access size is longword and the address is incremented or decremented by 4. even if the acce ss data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. while data of one word or one longword is being read, the size of increment or decrement is changi ng according to the actual data access size, for example, +1 or +2 for byte or word data. after one word or one longword of data is read, the address when the read cycle is started is incremented or decrem ented by the value according to bits sat1 and sat0. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 312 of 1102 rej09b0365-0100 in block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the sour ce address side, the sour ce address retu rns to the transfer start address and is not affected by the address update. when the extended repeat area is specified to the source address side, operation follows the setting. the upper address bits are fixed an d is not affected by the address update. while data is being transferred, dsar must be accessed in longwords. if the upper word and lower word are read separately, incorrect data may be read from since the contents of dsar during the transfer may be updated regardless of the access by the cpu. moreover, dsar for the channel being transferred must not be written to. (2) dma destination address register when the transfer destination ad dress set in ddar is accessed, the contents of ddar are output and then are updated to the next address. the increment or decrement can be specified by bits dat1 and dat0 in dacr. when dat1 and dat0 = b'00, the address is fixed. when da t1 and dat0 = b'01, the address is added with the offset. when dat1 and dat0 = b'10, the ad dress is incremented. when dat1 and dat0 = b'11, the address is decremented. the incrementing or decrementing size de pends on the data access size. the data access size is specified by bits dtsz 1 and dtsz0 in dmdr. when dtsz1 and dtsz0 = b'00, the data access size is byte and the addres s is incremented or d ecremented by 1. when dtsz1 and dtsz0 = b'01, the data access size is word and the addre ss is incremented or decremented by 2. when dtsz1 and dtsz0 = b'10, the data access size is longword and the address is incremente d or decremented by 4. even if the ac cess data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. while one word or one longword of data is being written, the incremen ting or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. af ter the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value accordi ng to bits sat1 and sat0. in block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start ad dress and is not affected by the address update. when the extended repeat area is specified to the destination address side, operation follows the setting. the upper address bits are fixed an d is not affected by the address update. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 313 of 1102 rej09b0365-0100 while data is being transferred, ddar must be accessed in longwords. if the upper word and lower word are read separately, incorrect data may be read from since the contents of ddar during the transfer may be updated regardless of the access by the cpu. moreover, ddar for the channel being transferred must not be written to. (3) dma transfer count register (dtcr) a dma transfer decrements the contents of dtcr by the transferred bytes. when byte data is transferred, dtcr is decremented by 1. when word data is tran sferred, dtcr is decremented by 2. when longword data is transferred, dtcr is decremented by 4. however, when dtcr = 0, the contents of dtcr are not changed since the number of transfers is not counted. while data is being transferred, all the bits of dtcr may be changed. dtcr must be accessed in longwords. if the upper word and lower word are read separately, incorrect data may be read from since the contents of dtcr duri ng the transfer may be update d regardless of the access by the cpu. moreover, dtcr for the channel being transferred must not be written to. when a conflict occurs between the address upda te by dma transfer and write access by the cpu, the cpu has priority. when a conflict occurs between change from 1, 2, or 4 to 0 in dtcr and write access by the cpu (other than 0), the cpu ha s priority in writing to dtcr. however, the transfer is stopped. (4) dma block size register (dbsr) dbsr is enabled in block or repeat transfer mode. bits 31 to 16 in dbsr function as bkszh and bits 15 to 0 in dbsr function as bksz. the bkszh bits (16 bits) store the block size and repeat size and its value is not changed. the bksz bits (16 bits) function as a counter for the block size and repeat size and its value is decremented ever y transfer by 1. when the bksz value is to change from 1 to 0 by a dma transfer, 0 is not stored but the bkszh value is loaded into the bksz bits. since the upper 16 b its of dbsr are not updated, db sr can be accessed in words. dbsr for the channel being transferred must not be written to. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 314 of 1102 rej09b0365-0100 (5) dte bit in dmdr although the dte b it in dmdr enables or disables data transfer by the cp u write access, it is automatically cleared to 0 according to the dma transfer state by the dmac. the conditions for clearing the dte bit by the dmac are as follows: ? when the total size of transfers is completed ? when a transfer is completed by a transfer size error interrupt ? when a transfer is completed by a repeat size end interrupt ? when a transfer is completed by an extended repeat area overflow interrupt ? when a transfer is stopped by an nmi interrupt ? when a transfer is stopped by and address error ? reset state ? hardware standby mode ? when a transfer is stopped by writing 0 to the dte bit writing to the registers for the channels when th e corresponding dte bit is set to 1 is prohibited (except for the dte bit). when changing the regi ster settings after writing 0 to the dte bit, confirm that the dte bit has been cleared to 0. figure 9.21 show the procedure for changing the register settings for the channel being transferred. read dte bit write 0 to dte bit change register settings dte = 0? [1] [2] [3] [4] no yes changing register settings of channel during operation end of changing register settings [1] write 0 to the dte bit in dmdr. [2] read the dte bit. [3] confirm that dte = 0. dte = 1 indicates that dma is transferring. [4] write the desired values to the registers. figure 9.21 procedure for changing register setting fo r channel being transferred section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 315 of 1102 rej09b0365-0100 (6) act bit in dmdr the act bit in dmdr indicates whether the dmac is in the idle or activ e state. when dte = 0 or dte = 1 and the dmac is waiting for a transfer request, the act bit is 0. otherwise (the dmac is in the active state), the act bit is 1. when individual transfers are stopped by writing 0 and the transfer is not comple ted, the act bit retains 1. in block transfer mode, even if individual transf ers are stopped by writing 0 to the dte bit, the 1- block size of transfers is not stopped. the act bit retains 1 from writing 0 to the dte bit to completion of a 1-bl ock size transfer. in burst mode, up to three times of dma transf er are performed from the cycle in which the dte bit is written to 0. the act bit retains 1 from writing 0 to the dte bit to completion of dma transfer. (7) errf bit in dmdr when an address error or an nmi interrupt o ccur, the dmac clears the dte bits for all the channels to stop a transfer. in addition, it sets the errf bit in dmdr_0 to 1 to indicate that an address error or an nmi interrupt has occurred regardless of whether or not the dmac is in operation. (8) esif bit in dmdr when an interrupt by an transfer size error, a re peat size end, or an extended repeat area overflow is requested, the esif bit in dmdr is set to 1. when both the esif and esie bits are set to 1, a transfer escape interrupt is re quested to the cpu or dtc. the esif bit is set to 1 when the act bit in dmdr is cleared to 0 to stop a transfer af ter the bus cycle of the interrupt source is completed. the esif bit is automatically cleared to 0 and a transfer request is clear ed if the transfer is resumed by setting the dte bit to 1 during interrupt handling. for details on interrupts, see section 9.8, interrupt sources. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 316 of 1102 rej09b0365-0100 (9) dtif bit in dmdr the dtif bit in dmdr is set to 1 after the total tr ansfer size of transfers is completed. when both the dtif and dtie bits in dmdr are set to 1, a transfer end interrupt by the transfer counter is requested to the cpu or dtc. the dtif bit is set to 1 when the act bit in dmdr is cleared to 0 to stop a transfer after the bus cycle is completed. the dtif bit is automatically cleared to 0 and a transfer request is clear ed if the transfer is resumed by setting the dte bit to 1 during interrupt handling. for details on interrupts, see section 9.8, interrupt sources. 9.5.8 priority of channels the channels of the dmac are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. table 9.6 shows the priority levels among the dmac channels. table 9.6 priority among dmac channels channel priority channel 0 high channel 1 channel 2 channel 3 low the channel having highest priority other than the channel being transferred is selected when a transfer is requested from other ch annels. the selected channel starts the transfer after the channel being transferred releases the bus. at this time, when a bus master other than the dmac requests the bus, the cycle for the bus master is inserted. in a burst transfer or a block tr ansfer, channels are not switched. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 317 of 1102 rej09b0365-0100 figure 9.22 shows a transfer example when multip le transfer requests from channels 0 to 2. channel 0 channel 1 bus released bus released channel 2 channel 0 transfer channel 1 transfer channel 2 transfer channel 0 channel 1 channel 2 wait wait request cleared request cleared request cleared request retained request retained request retained selected selected not selected address bus channel 0 channel 1 channel 2 b dmac operation figure 9.22 example of timing for channel priority section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 318 of 1102 rej09b0365-0100 9.5.9 dma basic bus cycle figure 9.23 shows an examples of signal timing of a basic bus cycle. in figure 9.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. when the bus mastership is passed from the dmac to the cpu, data is read from the source address and it is written to the destination address. the bus is not released between th e read and write cycles by other bus requests. dmac bus cycles follows the bus controller settings. cpu cycle dmac cycle (one word transfer) cpu cycle address bus b t 1 t 2 t 1 t 2 t 3 t 1 t 2 t 3 source address destination address rd lhwr llwr high figure 9.23 example of bus timing of dma transfer section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 319 of 1102 rej09b0365-0100 9.5.10 bus cycles in dual address mode (1) normal transfer mode (cycle stealing mode) in cycle stealing mode, the bus is released ever y time one transfer size of data (one byte, one word, or one longword) is completed. one bus cy cle or more by the cpu or dtc are executed in the bus released cycles. in figure 9.24, the tend signal output is enabled and data is transferred in words from the external 16-bit 2-state acces s space to the external 16-bit 2-state access spa ce in normal transfer mode by cycle stealing. dma read cycle dma write cycle address bus dma read cycle dma write cycle dma read cycle dma write cycle b rd lhwr , llwr tend bus released bus released bus released bus released last transfer cycle figure 9.24 example of transfer in no rmal transfer mode by cycle stealing in figures 9.25 and 9.26, the tend signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the 16-bit 2-state access sp ace in normal transfer mode by cycle stealing. in figure 9.25, the transfer source (dsar) is not aligned with a longword boundary and the transfer destination (ddar) is aligned with a longword boundary. in figure 9.26, the transfer source (dsar) is aligned with a longword boundary and the transfer destination (ddar) is not aligned with a longword boundary. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 320 of 1102 rej09b0365-0100 address bus dma word write cycle dma byte read cycle dma byte read cycle dma word read cycle dma word write cycle dma word write cycle dma byte read cycle dma byte read cycle dma word read cycle dma word write cycle b rd llwr lhwr tend bus released bus released bus released last transfer cycle 4m + 1 4m + 2 4m + 4 4n + 4 4n + 6 4n 4n +2 4m + 5 4m + 6 4m + 8 m and n are integers. figure 9.25 example of transfer in no rmal transfer mode by cycle stealing (transfer source dsar = odd add ress and source address increment) dma word read cycle dma byte write cycle dma word read cycle address bus dma byte write cycle dma byte write cycle dma word write cycle dma word read cycle dma byte write cycle dma word read cycle dma word write cycle b rd llwr lhwr tend bus released bus released bus released last transfer cycle 4m 4m + 2 4n + 5 4n + 2 4n + 4 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 m and n are integers. figure 9.26 example of transfer in no rmal transfer mode by cycle stealing (transfer destination ddar = odd address and dest ination address decrement) section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 321 of 1102 rej09b0365-0100 (2) normal transfer mode (burst mode) in burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. when a burst transfer st arts, a transfer request from a channe l having priority is suspended until the burst transfer is completed. in figure 9.27, the tend signal output is enabled and data is transferred in words from the external 16-bit 2-state acces s space to the external 16-bit 2-state access spa ce in normal transfer mode by burst access. dma read cycle dma read cycle dma write cycle address bus dma write cycle dma read cycle dma write cycle b rd lhwr , llwr tend bus released bus released last transfer cycle burst transfer figure 9.27 example of transfer in normal transfer mode by burst access section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 322 of 1102 rej09b0365-0100 (3) block transfer mode in block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. in figure 9.28, the tend signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access spa ce in block transfer mode. dma read cycle dma read cycle dma write cycle address bus dma write cycle dma read cycle dma read cycle dma write cycle dma write cycle b rd lhwr , llwr tend bus released bus released bus released last block transfer cycle block transfer figure 9.28 example of transfer in block transfer mode section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 323 of 1102 rej09b0365-0100 (4) activation timing by dreq falling edge figure 9.29 shows an example of norm al transfer mode activated by the dreq signal falling edge. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared and starts detecting a high level of the dreq signal for falling edge detection. if a high level of the dreq signal has been detected until completion of the dma write cycle, receiving the next transfer request resumes and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request duration of transfer request disabled duration of transfer request disabled min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started and sampling the dreq signal at the rising edge of the b signal is started to detect a high level of the dreq signal. [4][7] when a high level of the dreq signal has been detected, transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) figure 9.29 example of transfer in normal transfer mode activated by dreq falling edge section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 324 of 1102 rej09b0365-0100 figure 9.30 shows an example of block transfer mode activated by the dreq signal falling edge. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared and starts detecting a high level of the dreq signal for falling edge detection. if a high level of the dreq signal has been detected until completion of the dma write cycle, receiving the next transfer request resumes and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request duration of transfer request disabled duration of transfer request disabled min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started and sampling the dreq signal at the rising edge of the b signal is started to detect a high level of the dreq signal. [4][7] when a high level of the dreq signal has been detected, transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) 1-block transfer 1-block transfer figure 9.30 example of transfer in block transfer mode activated by dreq falling edge section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 325 of 1102 rej09b0365-0100 (5) activation timing by dreq low level figure 9.31 shows an example of norm al transfer mode activated by the dreq signal low level. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the write cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. wait wait wait min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) request request duration of transfer request disabled duration of transfer request disabled figure 9.31 example of transfer in normal transfer mode activated by dreq low level section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 326 of 1102 rej09b0365-0100 figure 9.32 shows an example of block transfer mode activated by the dreq signal low level. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the write cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. wait wait wait min. of 3 cycles min. of 3 cycles transfer source transfer destination transfer destination transfer source read write read write bus released bus released bus released dma read cycle dma write cycle dma read cycle dma write cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) 1-block transfer 1-block transfer request request duration of transfer request disabled duration of transfer request disabled figure 9.32 example of transfer in block transfer mode activated by dreq low level section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 327 of 1102 rej09b0365-0100 (6) activation timing by dreq low level with nrd = 1 when the nrd bit in dmdr is set to 1, the tim ing of receiving the next transfer request is delayed for one cycle. figure 9.33 shows an example of norm al transfer mode activated by the dreq signal low level with nrd = 1. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the write cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. duration of transfer request disabled transfer source transfer destination transfer destination transfer source bus released bus released bus released dma read cycle dma read cycle dma read cycle dma read cycle b dreq address bus channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed one cycle after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) request request min. of 3 cycles min. of 3 cycles duration of transfer request disabled which is extended by nrd duration of transfer request disabled which is extended by nrd duration of transfer request disabled figure 9.33 example of transfer in normal transfer mode activated by dreq low level with nrd = 1 section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 328 of 1102 rej09b0365-0100 9.5.11 bus cycles in single address mode (1) single address mode (read and cycle stealing) in single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is re leased temporarily. one bu s cycle or more by the cpu or dtc are executed in the bus released cycles. in figure 9.34, the tend signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). bus released bus released bus released dma read cycle dma read cycle dma read cycle dma read cycle b address bus bus released bus released last transfer cycle rd tend dack figure 9.34 example of transfer in single address mode (byte read) section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 329 of 1102 rej09b0365-0100 (2) single address mode (write and cycle stealing) in single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is re leased temporarily. one bu s cycle or more by the cpu or dtc are executed in the bus released cycles. in figure 9.35, the tend signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). bus released bus released dma write cycle b address bus bus released bus released last transfer cycle tend dack dma write cycle dma write cycle dma write cycle llwr bus released figure 9.35 example of transfer in single address mode (byte write) section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 330 of 1102 rej09b0365-0100 (3) activation timing by dreq falling edge figure 9.36 shows an example of si ngle address mode activated by the dreq signal falling edge. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared and starts detecting a high level of the dreq signal for falling edge detection. if a high level of the dreq signal has been detected until comple tion of the single cycle, receiving the next transfer request resumes and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request min. of 3 cycles min. of 3 cycles transfer source/ transfer destination single bus released bus released bus released dma single cycle dma single cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started and sampling the dreq signal at the rising edge of the b signal is started to detect a high level of the dreq signal. [4][7] when a high level of the dreq signal has been detected, transfer enable is resumed after completion of the write cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) transfer source/ transfer destination single dack duration of transfer request disabled duration of transfer request disabled figure 9.36 example of transfer in single address mode activated by dreq falling edge section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 331 of 1102 rej09b0365-0100 (4) activation timing by dreq low level figure 9.37 shows an example of norm al transfer mode activated by the dreq signal low level. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer re quest resumes after completion of the single cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. request wait wait wait request min. of 3 cycles min. of 3 cycles transfer source/ transfer destination single bus released bus released bus released dma single cycle dma single cycle b dreq address bus dma operation channel [1] [2] [3] [4] [5] [6] [7] transfer request enable resumed transfer request enable resumed [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed after completion of the single cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) transfer source/ transfer destination single dack duration of transfer request disabled duration of transfer request disabled figure 9.37 example of transfer in single address mode activated by dreq low level section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 332 of 1102 rej09b0365-0100 (5) activation timing by dreq low level with nrd = 1 when the nrd bit in dmdr is set to 1, the ti ming of receiving the next transfer request is delayed for one cycle. figure 9.38 shows an example of si ngle address mode activated by the dreq signal low level with nrd = 1. the dreq signal is sampled every cycle fro m the next rising edge of the b signal immediately after the dte bit write cycle. when a low level of the dreq signal is detected while a transfer request by the dreq signal is enabled, a transfer request is held in the dm ac. when the dmac is activated, the transfer request is cleared. receiving the next transfer request resumes after one cycle of the transfer request duration inserted by nrd = 1 on completion of the single cycle and then a low level of the dreq signal is detected. this operation is repeated until the transfer is completed. min. of 3 cycles min. of 3 cycles dma single cycle dma single cycle b dreq address bus channel [1] [2] [3] [4] [5] [6] [7] [1] after dma transfer request is enabled, a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. [2][5] the dmac is activated and the transfer request is cleared. [3][6] a dma cycle is started. [4][7] transfer request enable is resumed one cycle after completion of the single cycle. (a low level of the dreq signal is detected at the rising edge of the b signal and a transfer request is held. this is the same as [1].) transfer source/ transfer destination bus released bus released transfer request enable resumed transfer request enable resumed transfer source/ transfer destination request request duration of transfer request disabled duration of transfer request disabled duration of transfer request disabled which is extended by nrd duration of transfer request disabled which is extended by nrd bus released figure 9.38 example of transfer in single address mode activated by dreq low level with nrd = 1 section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 333 of 1102 rej09b0365-0100 9.6 dma transfer end operations on completion of a transfer differ according to the transf er end condition. dma transfer completion is indicated that the dte an d act bits in dmdr are changed from 1 to 0. (1) transfer end by dtcr change from 1, 2, or 4, to 0 when dtcr is changed from 1, 2, or 4 to 0, a dma transfer for the channel is completed. the dte bit in dmdr is cleared to 0 and the dtif bit in dmdr is set to 1. at this time, when the dtie bit in dmdr is set to 1, a transfer end interrupt by the transfer counter is requested. when the dtcr value is 0 before the transf er, the transfer is not stopped. (2) transfer end by tran sfer size error interrupt when the following conditions are satisfied while the tseie bit in dmdr is set to 1, a transfer size error occurs and a dma transfer is terminated. at this time, the dte bit in dmr is cleared to 0 and the esif bit in dmdr is set to 1. ? in normal transfer mode and repeat transfer mo de, when the next transfer is requested while a transfer is disabled du e to the dtcr value less than the data access size ? in block transfer mode, when the next transfer is requested while a transfer is disabled due to the dtcr value less than the block size when the tseie bit in dmdr is cleared to 0, da ta is transferred until the dtcr value reaches 0. a transfer size error is not ge nerated. operation in each transfer mode is shown below. ? in normal transfer mode and repeat transfer mode, when the dtcr value is less than the data access size, data is transferred in bytes ? in block transfer mode, when the dtcr value is less than the block size, the specified size of data in dtcr is transferred instead of transferring the block size of data. the transfer is performed in bytes. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 334 of 1102 rej09b0365-0100 (3) transfer end by repeat size end interrupt in repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the rptie bit in da cr is set to 1, a repeat size en d interrupt is requested. when the interrupt is requested to complete dma transf er, the dte bit in dmdr is cleared to 0 and the esif bit in dmdr is set to 1. under this condition, setting the dte bit to 1 resumes the transfer. in block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. (4) transfer end by interrupt on extended repeat area overflow when an overflow on the extended repeat area oc curs while the extended repeat area is specified and the sarie or darie bit in dacr is set to 1, an interrupt by an extended repeat area overflow is requested. when the interrupt is re quested, the dma transfer is terminated, the dte bit in dmdr is cleared to 0, and the esif bit in dmdr is set to 1. in dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. in block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1- block transfer, the remaining data is transferred. the tr ansfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) transfer end by clearing dte bit in dmdr when the dte bit in dmdr is cleared to 0 by th e cpu, a transfer is completed after the current dma cycle and a dma cycle in which the tr ansfer request is accep ted are completed. in block transfer mode, a dma transfer is completed after 1-block data is transferred. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 335 of 1102 rej09b0365-0100 (6) transfer end by nmi interrupt when an nmi interrupt is requested, the dte bits for all the channels are cleared to 0 and the errf bit in dmdr_0 is set to 1. when an nmi interrupt is requested during a dma transfer, the transfer is forced to st op. to perform dma transfer after an nmi interrupt is requested, clear the errf bit to 0 and then set the dte bits for the channels to 1. the transfer end timings after an nmi in terrupt is requested are shown below. (a) normal transfer mode and repeat transfer mode in dual address mode, a dma tran sfer is completed after completion of the write cycle for one transfer unit. in single address mode, a dma tr ansfer is completed after comp letion of the bus cycle for one transfer unit. (b) block transfer mode a dma transfer is forced to stop. since a 1-block size of transfers is not completed, operation is not guaranteed. in dual address mode, the write cy cle corresponding to the read cycl e is performed. this is similar to (a) in normal transfer mode. (7) transfer end by address error when an address error occurs, the dte bits for a ll the channels are cleared to 0 and the errf bit in dmdr_0 is set to 1. when an address error occurs during a dma tran sfer, the transfer is forced to stop. to perform a dma transfer after an address error occurs, clear the errf bit to 0 and then set the dte bits for the channels. the transfer end timing after an address error is the same as that after an nmi interrupt. (8) transfer end by hardwa re standby mode or reset the dmac is initialized by a reset and a transition to the hardware standby mode. a dma transfer is not guaranteed. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 336 of 1102 rej09b0365-0100 9.7 relationship among dmac and other bus masters 9.7.1 cpu priority control function over dmac the cpu priority control function over dmac can be used according to the cpu priority control register (cpupcr) setting. for details, see section 6.7, cpu priority control function over dtc and dmac. the priority level of the dmac is specified by bits dmap2 to dmap0 and can be specified for each channel. the priority level of the cpu is specified by bits cpup2 to cpup0. the value of bits cpup2 to cpup0 is updated according to th e exception handling priority. if the cpu priority control is enabled by the cp upce bit in cpupcr, when the cpu has priority over the dmac, a transfer request for the correspond ing channel is masked and the transfer is not activated. when another channel has priority over or the same as the cpu, a transfer request is received regardless of the priority between ch annels and the transfer is activated. the transfer request masked by the cpu priority control function is suspended. when the transfer channel is given priority over the cpu by changing priority levels of the cpu or channel, the transfer request is received and the transfer is resumed. writing 0 to the dte bit clears the suspended transfer request. when the cpupce bit is cleared to 0, it is regarded as the lowest priority. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 337 of 1102 rej09b0365-0100 9.7.2 bus arbitration among dmac and other bus masters when dma transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. the dmac can release the bus temporar ily to pass the bus to other bus masters. the consecutive dma transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. the read and write cycles of a dma transfer are not separated. refreshing, external bus release, and on-chip bus master (cpu or dtc) cycles are no t inserted between the read and write cycles of a dma transfer. in block transfer mode and an auto request tr ansfer by burst access, bus cycles of the dma transfer are consecutively performed. for this duration, since the dmac has priority over the cpu and dtc, accesses to the external space is suspended (the ibccs bi t in the bus control register 2 (bcr2) is cleared to 0). when the bus is passed to another channel or an au to request transfer by cy cle stealing, bus cycles of the dmac and on-chip bus mast er are performed alternatively. when the arbitration function among the dmac and on-chip bus masters is enabled by setting the ibccs bit in bcr2, the bus is used alternatively except the bus cycles which are not separated. for details, see section 8, bus controller (bsc). a conflict may occur between external space acce ss of the dmac and an external bus release cycle. even if a burst or bloc k transfer is performed by the dmac, the transfer is stopped temporarily and a cycle of external bus release is inserted by the bsc acc ording to the external bus priority (when the cpu extern al access and the dtc external access do not have priority over a dmac transfer, the transf ers are not operated until th e dmac releases the bus). in dual address mode, the dmac releases the ex ternal bus after the exte rnal space write cycle. since the read and write cy cles are not separated, the bus is not released. an internal space (on-chip me mory and internal i/o register s) access of the dmac and an external bus release cycle may be performed at the same time. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 338 of 1102 rej09b0365-0100 9.8 interrupt sources the dmac interrupt sources are a transfer end in terrupt by the transfer counter and a transfer escape end interrupt which is generated when a tran sfer is terminated befo re the transfer counter reaches 0. table 9.7 shows in terrupt sources and priority. table 9.7 interrupt so urces and priority abbr. interrupt sources priority dmtend0 transfer end interrupt by channel 0 transfer counter high dmtend1 transfer end interrupt by channel 1 transfer counter dmtend2 transfer end interrupt by channel 2 transfer counter dmtend3 transfer end interrupt by channel 3 transfer counter dmeend0 interrupt by channel 0 transfer size error interrupt by channel 0 repeat size end interrupt by channel 0 extended repeat area overflow on source address interrupt by channel 0 extended repeat area overflow on destination address dmeend1 interrupt by channel 1 transfer size error interrupt by channel 1 repeat size end interrupt by channel 1 extended repeat area overflow on source address interrupt by channel 1 extended repeat area overflow on destination address dmeend2 interrupt by channel 2 transfer size error interrupt by channel 2 repeat size end interrupt by channel 2 extended repeat area overflow on source address interrupt by channel 2 extended repeat area overflow on destination address dmeend3 interrupt by channel 3 transfer size error interrupt by channel 3 repeat size end interrupt by channel 3 extended repeat area overflow on source address interrupt by channel 3 extended repeat area overflow on destination address low each interrupt is enabled or disabled by the dtie and esie bits in dmdr for the corresponding channel. a dmtend interrupt is generated by the combination of the dtif and dtie bits in dmdr. a dmeend interrupt is generated by the combination of the esif and esie bits in dmdr. the dmeend interrupt sources are not distinguished. the priority among channels are decided by the interrupt controller and it is shown in table 9.7. for details, see section 6, interrupt controller. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 339 of 1102 rej09b0365-0100 each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. a transfer end interrupt by the transfer counter, a transf er size error interrupt, a repeat size end interrupt, an interrupt by an extended rep eat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the dtie bit in dmdr, the tseie bit in dmdr , the rptie bit in dacr, sarie bit in dacr, and the darie bit in dacr, respectively. a transfer end interrupt by the transfer counter is generated when the dtif bit in dmdr is set to 1. the dtif bit is set to 1 when dtcr becomes 0 by a transfer while the dtie bit in dmdr is set to 1. an interrupt other than the transf er end interrupt by the transfer counter is generated when the esif bit in dmdr is set to 1. the esif bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. a transfer size error interrupt is generated when the next transfer cannot be performed because the dtcr value is less than the data access size, mean ing that the data access size of transfers cannot be performed. in block transfer mode, the block size is compared with the dtcr value for transfer error decision. a repeat size end interrupt is generated when the ne xt transfer is requested after completion of the repeat size of transfers in repeat transfer mode. even when the rep eat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. at this time, when a transfer end interrupt by the transfer co unter is generated, the esif bit is set to 1. an interrupt by an extended re peat area overflow on the sour ce and destination addresses is generated when the address exceeds the extended re peat area (overflow). at this time, when a transfer end interrupt by the transfer counter, the esif bit is set to 1. figure 9.39 is a block diagram of interrupts and interrupt flags. to clear an interrupt, clear the dtif or esif bit in dmdr to 0 in the interrupt handling routine or continue the transfer by setting the dte bit in dmdr after setting the register. figure 9.40 shows procedure to resume the transfer by cleari ng a interrupt. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 340 of 1102 rej09b0365-0100 tsie bit dmac is activated in transfer size error state rptie bit dmac is activated after bksz bits are changed from 1 to 0 sarie bit extended repeat area overflow occurs in source address darie bit extended repeat area overflow occurs in destination address dtie bit dtif bit transfer end interrupt [setting condition] when dtcr becomes 0 and transfer ends setting condition is satisfied esie bit esif bit transfer escape end interrupt figure 9.39 interrupt and interrupt sources transfer end interrupt handling routine consecutive transfer processing registers are specified dte bit is set to 1 interrupt handling routine ends (rte instruction executed) transfer resume processing end transfer resumed after interrupt handling routine dtif and esif bits are cleared to 0 interrupt handling routine ends dte bit is set to 1 registers are specified transfer resume processing end [1] [2] [3] [4] [5] [6] [7] [1] specify the values in the registers such as transfer counter and address register. [2] set the dte bit in dmdr to 1 to resume dma operation. setting the dte bit to 1 automatically clears the dtif or esif bit in dmdr to 0 and an interrupt source is cleared. [3] end the interrupt handling routine by the rte instruction. [4] read that the dtif or the esif bit in dmdr = 1 and then write 0 to the bit. [5] complete the interrupt handling routine and clear the interrupt mask. [6] specify the values in the registers such as transfer counter and address register. [7] set the dte bit to 1 to resume dma operation. figure 9.40 procedure exam ple of resuming transfer by clearing interrupt source section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 341 of 1102 rej09b0365-0100 9.9 usage notes 1. dmac register access during operation except for clearing the dte bit in dmdr, th e settings for channels being transferred (including waiting state) must not be changed. the register settings must be changed during the transfer proh ibited state. 2. settings of module stop function the dmac operation can be enabled or disabled by the module stop control register. the dmac is enabled by the initial value. setting bit mstpa13 in mstpcra stops the clock supplied to the dmac and the dmac enters the module stop state. however, when a transfer for a channel is enabled or when an interrupt is being requested, bit mstpa13 cannot be set to 1. clear the dte bit to 0, clear the dtif or dtie bit in dmdr to 0, and then set bit mstpa13. when the clock is stopped, the dmac regist ers cannot be accessed. however, the following register settings are valid in the module stop stat e. disable them before entering the module stop state, if necessary. ? tende bit in dmdr is 1 (the tend signal output enabled) ? dacke bit in dmdr is 1 (the dack signal output enabled) 3. activation by dreq falling edge the dreq falling edge detection is synchronized with the dmac internal operation. a. activation request waiting state: waiting for detecting the dreq low level. a transition to 2. is made. b. transfer waiting state: waiting for a dm ac transfer. a transi tion to 3. is made. c. transfer prohibited state: waiting for detecting the dreq high level. a transition to 1. is made. after a dmac transfer enabled, a tran sition to 1. is made. therefore, the dreq signal is sampled by low level detection at the first activation after a dmac transfer enabled. 4. acceptation of activation source at the beginning of an activation source reception, a low level is detected regardless of the setting of dreq falling edge or low level detection. therefore, if the dreq signal is driven low before setting dmdr, the low level is received as a transfer request. when the dmac is activated, clear the dreq signal of the previous transfer. section 9 dma controller (dmac) rev. 1.00 sep. 13, 2007 page 342 of 1102 rej09b0365-0100 section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 343 of 1102 rej09b0365-0100 section 10 data transfer controller (dtc) this lsi includes a data transfer controller (dtc). the dtc can be activated to transfer data by an interrupt request. 10.1 features ? transfer possible over any number of channels: multiple data transfer enabled for on e activation source (chain transfer) chain transfer specifiable after data transfer (when the counter is 0) ? three transfer modes normal/repeat/block tran sfer modes selectable transfer source and destination addresses ca n be selected from increment/decrement/fixed ? short address mode or full address mode selectable ? short address mode transfer information is located on a 3-longword boundary the transfer source and destination addresses can be specified by 24 bits to select a 16- mbyte address space directly ? full address mode transfer information is located on a 4-longword boundary the transfer source and destination addresses can be specified by 32 bits to select a 4- gbyte address space directly ? size of data for data transfer can be specified as byte, word, or longword the bus cycle is divided if an odd address is specified for a word or longword transfer. the bus cycle is divided if address 4n + 2 is specified for a longword transfer. ? a cpu interrupt can be requested for the interrupt that activated the dtc a cpu interrupt can be requested af ter one data transfer completion a cpu interrupt can be requested after the specified data transfer completion ? read skip of th e transfer information specifiable ? writeback skip executed for the fixed transfer source and destination addresses ? module stop state specifiable section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 344 of 1102 rej09b0365-0100 figure 10.1 shows a block diagram of the dtc. th e dtc transfer informati on can be allocated to the data area*. when the transf er information is allocated to the on-chip ram, a 32-bit bus connects the dtc to the on-chip ram, enabling 32-bit/1-state reading and writing of the dtc transfer information. note: * when the transfer inform ation is stored in the on-chip ram, the rame bit in syscr must be set to 1. bus interface bus controller dtccr interrupt controller ack req dtcvbr dtc dtc internal bus peripheral bus internal bus (32 bits) external bus cpu interrupt request interrupt source clear request 8 register control activation control interrupt control on-chip rom on-chip ram mra mrb sar dar cra crb on-chip peripheral module external memory external device (memory mapped) dtc activation request vector number mra, mrb: sar: dar: cra, crb: dtcera to dtcerh: dtccr: dtcvbr: dtc mode registers a, b dtc source address register dtc destination address register dtc transfer count registers a, b dtc enable registers a to h dtc control register dtc vector base register [legend] dtcera to dtcerh figure 10.1 block diagram of dtc section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 345 of 1102 rej09b0365-0100 10.2 register descriptions dtc has the following registers. ? dtc mode register a (mra) ? dtc mode register b (mrb) ? dtc source address register (sar) ? dtc destination address register (dar) ? dtc transfer count register a (cra) ? dtc transfer count register b (crb) these six registers mra, mrb, sar, dar, cra , and crb cannot be directly accessed by the cpu. the contents of these registers are stored in the data area as transf er information. when a dtc activation request occurs, the dtc reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer informati on, and transfers data. after the data transfer, it write s a set of updated transfer info rmation back to the data area. ? dtc enable registers a to f (dtcera to dtcerf) ? dtc control register (dtccr) ? dtc vector base register (dtcvbr) section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 346 of 1102 rej09b0365-0100 10.2.1 dtc mode register a (mra) mra selects dtc operating mode. mra cann ot be accessed directly by the cpu. bit bit name initial value r/w 7 md1 undefined ? 6 md0 undefined ? 5 sz1 undefined ? 4 sz0 undefined ? 3 sm1 undefined ? 2 sm0 undefined ? 1 ? undefined ? 0 ? undefined ? bit bit name initial value r/w description 7 6 md1 md0 undefined undefined ? ? dtc mode 1 and 0 specify dtc transfer mode. 00: normal mode 01: repeat mode 10: block transfer mode 11: setting prohibited 5 4 sz1 sz0 undefined undefined ? ? dtc data transfer size 1 and 0 specify the size of data to be transferred. 00: byte-size transfer 01: word-size transfer 10: longword-size transfer 11: setting prohibited 3 2 sm1 sm0 undefined undefined ? ? source address mode 1 and 0 specify an sar operation after a data transfer. 0x: sar is fixed (sar writeback is skipped) 10: sar is incremented after a transfer (by 1 when sz1 and sz0 = b'00; by 2 when sz1 and sz0 = b'01; by 4 when sz1 and sz0 = b'10) 11: sar is decremented after a transfer (by 1 when sz1 and sz0 = b'00; by 2 when sz1 and sz0 = b'01; by 4 when sz1 and sz0 = b'10) 1, 0 ? undefined ? reserved the write value should always be 0. [legend] x: don't care section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 347 of 1102 rej09b0365-0100 10.2.2 dtc mode register b (mrb) mrb selects dtc operating mode. mrb cann ot be accessed directly by the cpu. bit bit name initial value r/w 7 chne undefined ? 6 chns undefined ? 5 disel undefined ? 4 dts undefined ? 3 dm1 undefined ? 2 dm0 undefined ? 1 ? undefined ? 0 ? undefined ? bit bit name initial value r/w description 7 chne undefined ? dtc chain transfer enable specifies the chain transfer . for details, see section 10.5.7, chain transfer. the chain transfer condition is selected by the chns bit. 0: disables the chain transfer 1: enables the chain transfer 6 chns undefined ? dtc chain transfer select specifies the chain transfer condition. if the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or dtcer is not cleared. 0: chain transfer every time 1: chain transfer only when transfer counter = 0 5 disel undefined ? dtc interrupt select when this bit is set to 1, a cpu interrupt request is generated every time after a data transfer ends. when this bit is set to 0, a cpu interrupt request is only generated when the specifi ed number of data transfer ends. 4 dts undefined ? dtc transfer mode select specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: specifies the destination as repeat or block area 1: specifies the source as repeat or block area section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 348 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 dm1 dm0 undefined undefined ? ? destination address mode 1 and 0 specify a dar operation after a data transfer. 0x: dar is fixed (dar writeback is skipped) 10: dar is incremented after a transfer (by 1 when sz1 and sz0 = b'00; by 2 when sz1 and sz0 = b'01; by 4 when sz1 and sz0 = b'10) 11: sar is decremented after a transfer (by 1 when sz1 and sz0 = b'00; by 2 when sz1 and sz0 = b'01; by 4 when sz1 and sz0 = b'10) 1, 0 ? undefined ? reserved the write value should always be 0. [legend] x: don't care 10.2.3 dtc source address register (sar) sar is a 32-bit register that designates the source address of data to be transferred by the dtc. in full address mode, 32 bits of sar are valid. in short address mode, the lower 24 bits of sar is valid and bits 31 to 24 are ignored. at this time, the upper eight bits are fi lled with the value of bit 23. if a word or longword access is performed while an odd address is speci fied in sar or if a longword access is performed while address 4n + 2 is specified in sar, th e bus cycle is divided into multiple cycles to transfer data. for deta ils, see section 10.5.1, bus cycle division. sar cannot be accessed dire ctly from the cpu. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 349 of 1102 rej09b0365-0100 10.2.4 dtc destination address register (dar) dar is a 32-bit register that designates the destination address of data to be transferred by the dtc. in full address mode, 32 bits of dar are valid. in short address mode, the lower 24 bits of dar is valid and bits 31 to 24 are ignored. at this time, the upper eight bits are fi lled with the value of bit 23. if a word or longword access is performed while an odd address is speci fied in dar or if a longword access is performed while address 4n + 2 is specified in dar, th e bus cycle is divided into multiple cycles to transfer data. for de tails, see section 10.5.1, bus cycle division. dar cannot be accessed directly from the cpu. 10.2.5 dtc transfer count register a (cra) cra is a 16-bit register that desi gnates the number of times data is to be transferred by the dtc. in normal transfer mode, cra functions as a 16-bit transfer counter (1 to 65,536). it is decremented by 1 every time data is transferred, and bit dtcen (n = 15 to 0) corresponding to the activation source is cleared and th en an interrupt is requested to the cpu when the count reaches h'0000. the transfer count is 1 when cra = h'0001, 65,535 when cra = h'ffff, and 65,536 when cra = h'0000. in repeat transfer mode, cra is divided into two parts: the upper eight bits (crah) and the lower eight bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent to cral when the count reaches h'00. the transfer count is 1 when crah = cral = h'01, 255 when crah = cral = h'ff, and 256 when crah = cral = h'00. in block transfer mode, cra is divided into two parts: the upper eight bits (crah) and the lower eight bits (cral). crah holds the block size while cral functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). cral is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of crah are sent to cral when the count reaches h'00. the block si ze is 1 byte (word or longwor d) when crah = cral =h'01, 255 bytes (words or longwords) when crah = cral = h'ff, and 256 bytes (words or longwords) when crah = cral =h'00. cra cannot be accessed directly from the cpu. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 350 of 1102 rej09b0365-0100 10.2.6 dtc transfer count register b (crb) crb is a 16-bit register that designates the number of times data is to be tr ansferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and bit dtcen (n = 15 to 0) correspondin g to the activation source is cleared and then an interrupt is requested to the cpu when the count reaches h'0000. the transfer count is 1 when crb = h'0001, 65,535 when crb = h'ffff, and 65,536 when crb = h'0000. crb is not available in normal and repeat modes and cannot be accessed directly by the cpu. 10.2.7 dtc enable registers a to h (dtcera to dtcerh) dtcer, which is comprised of eight registers, dt cera to dtcerh, is a register that specifies dtc activation interrupt sources. the corresponden ce between interrupt sources and dtce bits is shown in table 10.1. use bit manipulation instructions such as bset and bclr to read or write a dtce bit. if all interrupts are masked, multiple ac tivation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. bit bit name initial value r/w 15 dtce15 0 r/w 14 dtce14 0 r/w 13 dtce13 0 r/w 12 dtce12 0 r/w 11 dtce11 0 r/w 10 dtce10 0 r/w 9 dtce9 0 r/w 8 dtce8 0 r/w bit bit name initial value r/w 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w 0 dtce0 0 r/w section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 351 of 1102 rej09b0365-0100 bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dtce15 dtce14 dtce13 dtce12 dtce11 dtce10 dtce9 dtce8 dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dtc activation enable 15 to 0 setting this bit to 1 specifies a relevant interrupt source to a dtc activation source. [clearing conditions] ? when writing 0 to the bit to be cleared after reading 1 ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended these bits are not cleared when the disel bit is 0 and the specified number of transfers have not ended 10.2.8 dtc control register (dtccr) dtccr specifies transfer information read skip. bit bit name initial value r/w note: * only 0 can be written to clear the flag. 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 rrs 0 r/w 3 rchne 0 r/w 2 ? 0 r 1 ? 0 r 0 err 0 r/(w) * bit bit name initial value r/w description 7 to 5 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 352 of 1102 rej09b0365-0100 bit bit name initial value r/w description 4 rrs 0 r/w dtc transfer information read skip enable controls the vector address read and transfer information read. a dtc vector number is always compared with the vector number for the previous activation. if the vector numbers match and this bit is set to 1, the dtc data tr ansfer is started without reading a vector address and transfer information. if the previous dtc activation is a chain transfer, the vector address read and transfer information read are always performed. 0: transfer read skip is not performed. 1: transfer read skip is performed when the vector numbers match. 3 rchne 0 r/w chain transfer enable after dtc repeat transfer enables/disables the chain transfer while transfer counter (cral) is 0 in repeat transfer mode. in repeat transfer mode, the crah value is written to cral when cral is 0. accordingly, chain transfer may not occur when cral is 0. if this bit is set to 1, the chain transfer is enabled when crah is written to cral. 0: disables the chain transfer after repeat transfer 1: enables the chain transf er after repeat transfer 2, 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 err 0 r/(w) * transfer stop flag indicates that an address error or an nmi interrupt occurs. if an address error or an nmi interrupt occurs, the dtc stops. 0: no interrupt occurs 1: an interrupt occurs [clearing condition] ? when writing 0 after reading 1 note: * only 0 can be written to clear this flag. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 353 of 1102 rej09b0365-0100 10.2.9 dtc vector base register (dtcvbr) dtcvbr is a 32-bit register that specifies the base address for v ector table address calculation. bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. the initial value of dtcvbr is h'00000000. bit bit name initial value r/w 31 0 r 30 0 r 29 0 r 28 0 r 27 0 r/w 26 0 r/w 25 0 r/w 24 0 r/w 23 0 r/w 22 0 r/w 21 0 r/w 20 0 r/w 19 0 r/w 18 0 r/w 17 0 r/w 16 0 r/w bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r 10.3 activation sources the dtc is activated by an interrupt request. th e interrupt source is sel ected by dtcer. a dtc activation source can be selected by setting the corresponding bit in dtcer; the cpu interrupt source can be selected by clearing the corresponding bit in dtcer. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding dtce r bit is cleared. 10.4 location of transfer inform ation and dtc vector table locate the transfer information in the data area. th e start address of transfer information should be located at the address that is a multiple of four (4n). otherwise, the lower two bits are ignored during access ([1:0] = b'00.) tran sfer information can be located in either short address mode (three longwords) or full address mode (four longwords). the dtcmd bit in syscr specifies either short address mode (dtcmd = 1) or full address mode (dtcmd = 0). for details, see section 3.2.2, system control register (syscr). tr ansfer informatio n located in the data area is shown in figure 10.2 the dtc reads the start address of transfer informatio n from the vector ta ble according to the activation source, and then reads the transfer info rmation from the start addr ess. figure 10.3 shows correspondences between th e dtc vector address and transfer information. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 354 of 1102 rej09b0365-0100 start address 4 bytes 1 0 mra sar mrb dar cra crb mra sar mrb dar cra crb mra mrb reserved (0 write) mra mrb reserved (0 write) sar dar cra crb cra crb sar dar 3 2 transfer information in short address mode chain transfer transfer information for one transfer (3 longwords) transfer information for the 2nd transfer in chain transfer (3 longwords) lower addresses lower addresses transfer information in full address mode transfer information for one transfer (4 longwords) transfer information for the 2nd transfer in chain transfer (4 longwords) start address 4 bytes 1 03 2 chain transfer figure 10.2 transfer in formation on data area transfer information (1) start address transfer information (2) start address transfer information (n) start address vector table upper: dtcvbr lower: h'400 + vector number 4 dtc vector address +4 +4n transfer information (1) 4 bytes transfer information (2) transfer information (n) : : : : : : figure 10.3 correspondence between dtc vector address and transfer information section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 355 of 1102 rej09b0365-0100 table 10.1 shows correspondence between the dtc activation source and vector address. table 10.1 interrupt sou rces, dtc vector addresses, and corresponding dtces origin of activation source activation source vector number dtc vector address offset dtce * priority external pin irq0 64 h'500 dtcea15 high irq1 65 h'504 dtcea14 irq2 66 h'508 dtcea13 irq3 67 h'50c dtcea12 irq4 68 h'510 dtcea11 irq5 69 h'514 dtcea10 irq6 70 h'518 dtcea9 irq7 71 h'51c dtcea8 irq8 72 h'520 dtcea7 irq9 73 h'524 dtcea6 irq10 74 h'528 dtcea5 irq11 75 h'52c dtcea4 irq12 76 h'0530 dtcea3 irq13 77 h'0534 dtcea2 irq14 78 h'0538 dtcea1 irq15 79 h'053c dtcea0 a/d_0 adi0 (a/d_0 conversion end) 86 h'558 dtceb15 tpu_0 tgi0a 88 h'560 dtceb13 tgi0b 89 h'564 dtceb12 tgi0c 90 h'568 dtceb11 tgi0d 91 h'56c dtceb10 tpu_1 tgi1a 93 h'574 dtceb9 tgi1b 94 h'578 dtceb8 tpu_2 tgi2a 97 h'584 dtceb7 tgi2b 98 h'588 dtceb6 tpu_3 tgi3a 101 h'594 dtceb5 tgi3b 102 h'598 dtceb4 tgi3c 103 h'59c dtceb3 tgi3d 104 h'5a0 dtceb2 low section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 356 of 1102 rej09b0365-0100 origin of activation source activation source vector number dtc vector address offset dtce * priority tgi4a 106 h'5a8 dtceb1 high tpu_4 tgi4b 107 h'5ac dtceb0 tgi5a 110 h'5b8 dtcec15 tpu_5 tgi5b 111 h'5bc dtcec14 tmr_0 cmi0a 116 h'5d0 dtcec13 cmi0b 117 h'5d4 dtcec12 tmr_1 cmi1a 119 h'5dc dtcec11 cmi1b 120 h'5e0 dtcec10 tmr_2 cmi2a 122 h'5e8 dtcec9 cmi2b 123 h'5ec dtcec8 tmr_3 cmi3a 125 h'5f4 dtcec7 cmi3b 126 h'5f8 dtcec6 dmac dmtend0 128 h'600 dtcec5 dmtend1 129 h'604 dtcec4 dmtend2 130 h'608 dtcec3 dmtend3 131 h'60c dtcec2 dmac dmeend0 136 h'620 dtced13 dmeend1 137 h'624 dtced12 dmeend2 138 h'628 dtced11 dmeend3 139 h'62c dtced10 sci_0 rxi0 145 h'644 dtced5 txi0 146 h'648 dtced4 sci_1 rxi1 149 h'654 dtced3 txi1 150 h'658 dtced2 sci_2 rxi2 153 h'664 dtced1 txi2 154 h'668 dtced0 sci_3 rxi3 157 h'674 dtced15 txi3 158 h'678 dtced14 sci_4 rxi4 161 h'684 dtcee13 txi4 162 h'688 dtcee12 low section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 357 of 1102 rej09b0365-0100 origin of activation source activation source vector number dtc vector address offset dtce * priority tgi6a 164 h'690 dtcee11 high tgi6b 165 h'694 dtcee10 tgi6c 166 h'698 dtcee9 tpu_6 tgi6d 167 h'69c dtcee8 tgi7a 169 h'6a4 dtcee7 tpu_7 tgi7b 170 h'6a8 dtcee6 tgi8a 173 h'6b4 dtcee5 tpu_8 tgi8b 174 h'6b8 dtcee4 tgi9a 177 h'6c4 dtcee3 tgi9b 178 h'6c8 dtcee2 tgi9c 179 h'6cc dtcee1 tpu_9 tgi9d 180 h'6d0 dtcee0 tgi10a 182 h'6d8 dtcef15 tgi10b 183 h'6dc dtcef14 tpu_10 tgi10v 186 h'6e8 dtcef11 tgi11a 188 h'6f 0 dtcef10 tpu_11 tgi11b 189 h'6f4 dtcef9 low note: * the dtce bits with no corresponding interru pt are reserved, and the write value should always be 0. to leave software standby mode or all-module-clock-stop mode with an interrupt, write 0 to the corresponding dtce bit. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 358 of 1102 rej09b0365-0100 10.5 operation the dtc stores transfer information in the data area. when activated, the dtc reads transfer information that is stored in the data area an d transfers data on the basis of that transfer information. after the data transfer, it writes upda ted transfer information back to the data area. since transfer information is in the data area, it is possible to transfer data over any required number of channels. there are three transfer modes: normal, repeat, and block. the dtc specifies the source ad dress and destination address in sar and dar, respectively. after a transfer, sar and dar are incremented, decremented, or fixed independently. table 10.2 shows the dtc transfer modes. table 10.2 dtc transfer modes transfer mode size of data transferred at one transfer request memory address increment or decrement transfer count normal 1 byte/word/longword increment ed/decremented by 1, 2, or 4, or fixed 1 to 65536 repeat * 1 1 byte/word/longword incremented /decremented by 1, 2, or 4, or fixed 1 to 256 * 3 block * 2 block size specified by crah (1 to 256 bytes/words/longwords) incremented/decremented by 1, 2, or 4, or fixed 1 to 65536 notes: 1. either source or destinat ion is specified to repeat area. 2. either source or destinati on is specified to block area. 3. after transfer of the specified transfer co unt, initial state is recovered to continue the operation. setting the chne bit in mrb to 1 makes it possi ble to perform a number of transfers with a single activation (chain transfer). setting the chns bit in mrb to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. figure 10.4 shows a flowchart of dtc operation, and table 10.3 summarizes the chain transfer conditions (combinations for performing the second and third tran sfers are omitted). section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 359 of 1102 rej09b0365-0100 start match & rrs = 1 not match | rrs = 0 next transfer read transfer information transfer data update transfer information update the start address of transfer information write transfer information chne = 1 transfer counter = 0 or disel = 1 clear activation source flag end chns = 0 transfer counter = 0 disel = 1 clear dtcer/request an interrupt to the cpu no no no no no yes yes yes yes yes vector number comparison read dtc vector figure 10.4 flowchart of dtc operation section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 360 of 1102 rej09b0365-0100 table 10.3 chain transfer conditions 1st transfer 2nd transfer chne chns disel transfer counter * 1 chne chns disel transfer counter * 1 dtc transfer 0 ? 0 not 0 ? ? ? ? ends at 1st transfer 0 ? 0 0 * 2 ? ? ? ? ends at 1st transfer 0 ? 1 ? ? ? ? interrupt request to cpu 0 ? 0 not 0 ends at 2nd transfer 0 ? 0 0 * 2 ends at 2nd transfer 1 0 ? ? 0 ? 1 ? interrupt request to cpu 1 1 0 not 0 ? ? ? ends at 1st transfer 0 ? 0 not 0 ends at 2nd transfer 0 ? 0 0 * 2 ends at 2nd transfer 1 1 ? 0 * 2 0 ? 1 interrupt request to cpu 1 1 1 not 0 ? ? ? ? ends at 1st transfer interrupt request to cpu notes: 1. cra in normal mode transfer, cral in repeat transfer mode, or crb in block transfer mode 2. when the contents of the crah is wr itten to the cral in repeat transfer mode 10.5.1 bus cycle division when the transfer data size is wo rd and the sar and dar values are not a multiple of 2, the bus cycle is divided and the transfer data is read fr om or written to in bytes. similarly, when the transfer data size is lo ngword and the sar and da r values are not a multip le of 4, the bus cycle is divided and the transfer data is read from or written to in words. table 10.4 shows the relationship among, sar, dar, transfer data size, bus cycle divisions, and access data size. figure 10.5 shows th e bus cycle division example. table 10.4 number of bus cy cle divisions and access size specified data size sar and dar values byte (b) word (w) longword (lw) address 4n 1 (b) 1 (w) 1 (lw) address 2n + 1 1 (b) 2 (b-b) 3 (b-w-b) address 4n + 2 1 (b) 1 (w) 2 (w-w) section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 361 of 1102 rej09b0365-0100 clock address dtc activation request dtc request bbw r w clock address dtc activation request dtc request ww l r w clock address dtc activation request dtc request bbl w r w [example 1: when an odd address and even address are specified in sar and dar, respectively, and when the data size of transfe r is specified as word] [example 2: when an odd address and address 4n are specified in sar and dar, respectively, and when the data size of transfer is specified as longword] [example 3: when address 4n + 2 and address 4n are specified in sar and dar, respectively, and when the data size of transfer is specified as longword] vector read transfer information read data transfer transfer information write vector read transfer information read data transfer transfer information write vector read transfer information read data transfer transfer information write figure 10.5 bus cycle division example section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 362 of 1102 rej09b0365-0100 10.5.2 transfer informat ion read skip function by setting the rrs bit of dtccr, the vector addre ss read and transfer information read can be skipped. the current dtc vector number is always compared with the vector number of previous activation. if the vector number s match when rrs = 1, a dtc data transfer is performed without reading the vector address and tran sfer information. if the previous activation is a chain transfer, the vector address read and transf er information read are always performed. figure 10.6 shows the transfer information read skip timing. to modify the vector table and tr ansfer information, temporarily cl ear the rrs bit to 0, modify the vector table and transfer information, and then set the rrs bit to 1 again. when the rrs bit is cleared to 0, the stored vector number is dele ted, and the updated vect or table and transfer information are read at the next activation. clock vector read note: transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while rrs = 1. (1) (2) transfer information read data transfer transfer information write address dtc activation request dtc request transfer information read skip r w data transfer transfer information write r w figure 10.6 transfer info rmation read skip timing section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 363 of 1102 rej09b0365-0100 10.5.3 transfer information writeback skip function by specifying bit sm1 in mra and bit dm1 in mrb to the fixed address mode, a part of transfer information will not be written back. this function is performed regardless of short or full address mode. table 10.5 shows the transfer information writeback skip condition and writeback skipped registers. note that the cra and crb are always written back regardless of the short or full address mode. in addition in full address mode, the writeback of the mra and mrb are always skipped. table 10.5 transfer information writebac k skip condition and writeback skipped registers sm1 dm1 sar dar 0 0 skipped skipped 0 1 skipped written back 1 0 written back skipped 1 1 written back written back 10.5.4 normal transfer mode in normal transfer mode, one operation transfers one byte, one word, or one longword of data. from 1 to 65,536 transfers can be specified. the transfer source and destination addresses can be specified as incremented, decremented, or fixed. when the specified number of transfers ends, an interrupt can be requested to the cpu. table 10.6 lists the register function in normal transfer mode. figure 10.7 shows the memory map in normal transfer mode. table 10.6 register function in normal transfer mode register function written back value sar source address incremented/decremented/fixed * dar destination address incremented/decremented/fixed * cra transfer count a cra ? 1 crb transfer count b not updated note: * transfer information writeback is skipped. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 364 of 1102 rej09b0365-0100 sar transfer source data area dar transfer transfer destination data area figure 10.7 memory map in normal transfer mode 10.5.5 repeat transfer mode in repeat transfer mode, one operation transfers one byte, one word, or one longword of data. by the dts bit in mrb, either the source or destinat ion can be specified as a repeat area. from 1 to 256 transfers can be specified. when the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. the other address register is then increm ented, decremented, or left fixed. in repeat transfer mode, the transfer counter (cral) is updated to the value specified in crah when cral becomes h'00. thus the transfer counter value does not reach h'00, and therefore a cpu interrupt cannot be requested when disel = 0. table 10.7 lists the register function in repeat transfer mode. figure 10.8 shows the memory map in repeat transfer mode. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 365 of 1102 rej09b0365-0100 table 10.7 register function in repeat transfer mode written back value register function cral is not 1 cral is 1 sar source address incremented/decremented/fixed * dts =0: incremented/ decremented/fixed * dts = 1: sar initial value dar destination address incremented/decremented/fixed * dts = 0: dar initial value dts =1: incremented/ decremented/fixed * crah transfer count storage crah crah cral transfer count a cral ? 1 crah crb transfer count b not updated not updated note: * transfer information writeback is skipped. sar transfer source data area (specified as repeat area) dar transfer transfer destination data area figure 10.8 memory map in repeat transfer mode (when transfer source is specified as repeat area) section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 366 of 1102 rej09b0365-0100 10.5.6 block transfer mode in block transfer mode, one opera tion transfers one block of data. either the transfer source or the transfer destination is de signated as a block area by the dts bit in mrb. the block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). when the transfer of one block ends, the block size counter (cral) and address register (sar when dts = 1 or dar when dts = 0) specified as the block area is restored to the initial state. th e other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfer s can be specified. when the specified number of transfers ends, an interrupt is requested to the cpu. table 10.8 lists the register function in block transfer mode. figure 10.9 shows the memory map in block transfer mode. table 10.8 register function in block transfer mode register function written back value sar source address dts =0: incremented/decremented/fixed * dts = 1: sar initial value dar destination address dts = 0: dar initial value dts =1: incremented/decremented/fixed * crah block size storage crah cral block size counter crah crb block transfer counter crb ? 1 note: * transfer information writeback is skipped. transfer source data area transfer destination data area (specified as block area) block area dar sar : : transfer 1st block nth block figure 10.9 memory map in block transfer mode (when transfer destination is specified as block area) section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 367 of 1102 rej09b0365-0100 10.5.7 chain transfer setting the chne bit in mrb to 1 enables a number of data transfers to be performed consecutively in response to a si ngle transfer request. setting the chne and chns bits in mrb set to 1 enables a chain transfer only when the tr ansfer counter reaches 0. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 10.10 shows the chain transfer operation. in the case of transfer with chne set to 1, an in terrupt request to the cpu is not generated at the end of the specified number of tr ansfers or by setting th e disel bit to 1, and the interrupt source flag for the activation source and dtcer are not affected. in repeat transfer mode, setting the rchne bit in dtccr and the chne and chns bits in mrb to 1 enables a chain transfer af ter transfer with tr ansfer counter = 1 has been completed. transfer information chne = 1 transfer information chne = 0 transfer information stored in user area data area transfer source data (1) transfer destination data (1) transfer source data (2) transfer destination data (2) transfer information start address vector table dtc vector address figure 10.10 operation of chain transfer section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 368 of 1102 rej09b0365-0100 10.5.8 operation timing figures 10.11 to 10.14 show the dtc operation timings. clock address dtc activation request dtc request r w vector read transfer information read data transfer transfer information write figure 10.11 dtc operation timing (example of short address mode in normal transfer mode or repeat transfer mode) clock address dtc activation request dtc request rwr w vector read transfer information read data transfer transfer information write figure 10.12 dtc operation timing (example of short address mode in bloc k transfer mode with block size of 2) section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 369 of 1102 rej09b0365-0100 clock address dtc activation request dtc request rw r w vector read transfer information read data transfer transfer information write transfer information read data transfer transfer information write figure 10.13 dtc operation timing (example of short address mode in chain transfer) clock address dtc activation request dtc request r w vector read transfer information read data transfer transfer information write figure 10.14 dtc operation timing (example of full address mode in normal transfer mode or repeat transfer mode) section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 370 of 1102 rej09b0365-0100 10.5.9 number of dtc execution cycles table 10.9 shows the execution status for a singl e dtc data transfer, an d table 10.10 shows the number of cycles required for each execution. table 10.9 dtc execution status mode vector read i transfer information read j transfer information write l data read l data write m internal operation n normal 1 0 * 1 4 * 2 3 * 3 0 * 1 3 * 2.3 2 * 4 1 * 5 3 * 6 2 * 7 1 3 * 6 2 * 7 1 1 0 * 1 repeat 1 0 * 1 4 * 2 3 * 3 0 * 1 3 * 2.3 2 * 4 1 * 5 3 * 6 2 * 7 1 3 * 6 2 * 7 1 1 0 * 1 block transfer 1 0 * 1 4 * 2 3 * 3 0 * 1 3 * 2.3 2 * 4 1 * 5 3?p * 6 2p * 7 1p 3p * 6 2p * 7 1p 1 0 * 1 [legend] p: block size (crah and cral value) note: 1. when transfer information read is skipped 2. in full address mode operation 3. in short address mode operation 4. when the sar or dar is in fixed mode 5. when the sar and dar are in fixed mode 6. when a longword is transferred while an odd address is specified in the address register 7. when a word is transferred while an odd addr ess is specified in the address register or when a longword is transferred while address 4n + 2 is specified section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 371 of 1102 rej09b0365-0100 table 10.10 number of cycles requ ired for each execution state object to be accessed on-chip ram on-chip rom on-chip i/o registers external devices bus width 32 32 8 16 32 8 16 access cycles 1 1 2 2 2 2 3 2 3 vector read s i 1 1 ? ? ? 8 12 + 4m 4 6 + 2m transfer information read s j 1 1 ? ? ? 8 12 + 4m 4 6 + 2m execution status transfer information write s k 1 1 ? ? ? 8 12 + 4m 4 6 + 2m byte data read s l 1 1 2 2 2 2 3 + m 2 3 + m word data read s l 1 1 4 2 2 4 4 + 2m 2 3 + m longword data read s l 1 1 8 4 2 8 12 + 4m 4 6 + 2m byte data write s m 1 1 2 2 2 2 3 + m 2 3 + m word data write s m 1 1 4 2 2 4 4 + 2m 2 3 + m longword data write s m 1 1 8 4 2 8 12 + 4m 4 6 + 2m internal operation s n 1 [legend] m: number of wait cycles 0 to 7 (for det ails, see section 8, bus controller (bsc).) the number of execu tion cycles is calculated from the formula below. note that means the sum of all transfers activ ated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution cycles = i ? s i + (j ? s j + k ? s k + l ? s l + m ? s m ) + n ? s n 10.5.10 dtc bus release timing the dtc requests the bus mastership to the bus arbiter when an activation request occurs. the dtc releases the bus after a vector read, transf er information read, a single data transfer, or transfer information writeback. the dtc does not release the bus during transfer information read, single data transfer, or transfer information writeback. 10.5.11 dtc priority level control to the cpu the priority of the dtc activation sources over th e cpu can be controlled by the cpu priority level specified by bits cpup2 to cpup0 in cpupcr and the dtc priority level specified by bits dtcp2 to dtcp0. for details, see section 6, interrupt controller. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 372 of 1102 rej09b0365-0100 10.6 dtc activation by interrupt the procedure for using the dtc with interrupt activation is shown in figure 10.15. clearing the rrs bit in dtccr to 0 clears the read skip flag of transfer information. read skip is not performed when the dtc is activated after clearing the rrs bit. when updating transfer information, the rrs bit must be cleared. set the mra, mrb, sar, dar, cra, and crb transfer information in the data area. for details on setting transfer information, see section 10.2, register descriptions. for details on location of transfer information, see section 10.4, location of transfer information and dtc vector table. set the start address of the transfer information in the dtc vector table. for details on setting dtc vector table, see section 10.4, location of transfer information and dtc vector table. setting the rrs bit to 1 performs a read skip of second time or later transfer information when the dtc is activated consecu- tively by the same interrupt source. setting the rrs bit to 1 is always allowed. however, the value set during transfer will be valid from the next transfer. set the bit in dtcer corresponding to the dtc activation interrupt source to 1. for the correspondence of interrupts and dtcer, refer to table 10.1. the bit in dtcer may be set to 1 on the second or later transfer. in this case, setting the bit is not needed. set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. for details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. after the end of one data transfer, the dtc clears the activation source flag or clears the corresponding bit in dtcer and requests an interrupt to the cpu. the operation after transfer depends on the transfer information. for details, see section 10.2, register descriptions and figure 10.4. dtc activation by interrupt clear rrs bit in dtccr to 0 set transfer information (mra, mrb, sar, dar, cra, crb) set starts address of transfer information in dtc vector table set rrs bit in dtccr to 1 set corresponding bit in dtcer to 1 set enable bit of interrupt request for activation source to 1 interrupt request generated dtc activated corresponding bit in dtcer cleared or cpu interrupt requested transfer end [1] [2] [3] [4] [5] [6] [7] [1] [2] [3] [4] [5] [6] [7] determine clearing method of activation source clear activation source clear corresponding bit in dtcer figure 10.15 dtc with interrupt activation section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 373 of 1102 rej09b0365-0100 10.7 examples of use of the dtc 10.7.1 normal transfer mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. 1. set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal transfer mode (md1 = md0 = 0), and byte size (sz1 = sz0 = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the rdr address of the sci in sar, the start address of the ram area where the data will be received in dar, and 128 (h' 0080) in cra. crb can be set to any value. 2. set the start address of the transfer informatio n for an rxi interrupt at the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the sci to the appropriate receive mode. se t the rie bit in scr to 1 to enable the receive end (rxi) interrupt. since the generation of a receive er ror during the sci reception operation will disable subsequent recep tion, the cpu should be en abled to accept receive error interrupts. 5. each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activ ated. the receive data is transferred from rdr to ram by the dtc. dar is incremented an d cra is decremented. the rdrf flag is automatically cleared to 0. 6. when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interr upt request is sent to the cpu. termination processing should be performed in the interrupt handling routine. 10.7.2 chain transfer an example of dtc chain transfer is shown in which pulse output is performed using the ppg. chain transfer can be used to perform pulse output data transfer and ppg output trigger cycle updating. repeat mode transfer to the ppg's ndr is performed in the first half of the chain transfer, and normal mode transfer to the tpu's tgr in the second half. this is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the ch ain transfer (transfer when chne = 0). section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 374 of 1102 rej09b0365-0100 1. perform settings for transfer to the ppg' s ndr. set mra to sour ce address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), repeat mode (md1 = 0, md0 = 1), and word size (sz1 = 0, sz0 = 1). set th e source side as a repeat area (dts = 1). set mrb to chain transfer mode (chne = 1, chns = 0, disel = 0). set the data table start address in sar, the ndrh address in dar, and the da ta table size in crah and cral. crb can be set to any value. 2. perform settings for transfer to the tpu's tgr. set mra to source address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), normal mode (md1 = md0 = 0), and word size (sz1 = 0, sz0 = 1). set th e data table start address in sar, the tgra address in dar, and the data table size in cra. crb can be set to any value. 3. locate the tpu transfer information consec utively after the ndr transfer information. 4. set the start address of the ndr transfer information to the dtc vector address. 5. set the bit corresponding to the tgia interrupt in dtcer to 1. 6. set tgra as an output compare register (output disabled) with tior, and enable the tgia interrupt with tier. 7. set the initial output value in podr, and the next output value in ndr. set bits in ddr and nder for which output is to be performed to 1. using pcr, select the tpu compare match to be used as the output trigger. 8. set the cst bit in tstr to 1, and start the tcnt count operation. 9. each time a tgra compare match occurs, the ne xt output value is transferred to ndr and the set value of the next output trigger period is transferred to tgra. the activation source tgfa flag is cleared. 10. when the specified number of transfers are completed (the tpu transfer cra value is 0), the tgfa flag is held at 1, the dtce bit is cleared to 0, and a tgia interrupt request is sent to the cpu. termination processing should be performed in the interrupt handling routine. 10.7.3 chain transfer when counter = 0 by executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. an example is shown in which a 128-kbyte input buffer is configured. the input buffer is assumed to have been set to start at lower address h'00 00. figure 10.16 shows the chain transfer when the counter value is 0. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 375 of 1102 rej09b0365-0100 1. for the first transfer, set the normal transfer mode for input da ta. set the fixed transfer source address, cra = h'0000 (65,536 times), chne = 1, chns = 1, and disel = 0. 2. prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in rom, etc.). for exam ple, if the input buff er is configured at addresses h'200000 to h'21ffff, prepare h'21 and h'20. 3. for the second transfer, set rep eat transfer mode (with the source side as the repeat area) for re- setting the transfer destination address for the fi rst data transfer. use th e upper eight bits of dar in the first transfer information area as th e transfer destination. set chne = disel = 0. if the above input buffer is specified as h'200000 to h'21ffff, set the transfer counter to 2. 4. execute the first data transfer 65536 times by means of interrupts. when the transfer counter for the first data transfer reaches 0, the second da ta transfer is started. set the upper eight bits of the transfer source address for the first data transfer to h'21. the lower 16 bits of the transfer destination addr ess of the first data transfer an d the transfer c ounter are h'0000. 5. next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. when the tran sfer counter for the first data transfer reaches 0, the second data transfer is started. set th e upper eight bits of the transfer source address for the first data transfer to h'20. the lower 16 bi ts of the transfer destination ad dress of the first data transfer and the transfer co unter are h'0000. 6. steps 4 and 5 are repeated endlessly. as repeat mode is specified for the second data transfer, no interrupt request is sent to the cpu. 1st data transfer information 2nd data transfer information transfer information located on the on-chip memory chain transfer (counter = 0) input circuit input buffer upper 8 bits of dar figure 10.16 chain transfer when counter = 0 section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 376 of 1102 rej09b0365-0100 10.8 interrupt sources an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is genera ted. these interrupts to the cpu are subject to cpu mask level and priority level control in the interrupt controller. 10.9 usage notes 10.9.1 module stop state setting operation of the dtc can be disabled or enabled using the module stop control register. the initial setting is for operation of the dtc to be en abled. register access is disabled by setting the module stop state. the module st op state cannot be set while the dtc is activated. for details, refer to section 24, power-down modes. 10.9.2 on-chip ram transfer information can be located in on-chip ra m. in this case, the ra me bit in syscr must not be cleared to 0. 10.9.3 dmac transfer end interrupt when the dtc is activated by a dmac transfer end interrupt, the dte bit of dmdr is not controlled by the dtc but its value is modified with the write data rega rdless of the transfer counter value and disel bit setting. accordingl y, even if the dtc transfer counter value becomes 0, no interrupt request may be sent to the cpu in some cases. 10.9.4 dtce bit setting for dtce bit setting, use bit manipulation instruc tions such as bset and bclr. if all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 377 of 1102 rej09b0365-0100 10.9.5 chain transfer when chain transfer is used, clearing of the activation source or dtcer is performed when the last of the chain of data transfers is ex ecuted. at this time, sci and a/d converter interrupt/activation sources , are cleared when the dt c reads or writes to the relevant register. therefore, when the dtc is activated by an interr upt or activation source, if a read/write of the relevant register is not included in the last chai ned data transfer, the interrupt or activation source will be retained. 10.9.6 transfer information start address, source address, and destination address the transfer information start addres s to be specified in the vector table should be address 4n. if an address other than address 4n is specified, the lower 2 bits of th e address are regarded as 0s. the source and destination addres ses specified in sar and dar, re spectively, will be transferred in the divided bus cycles depending on the address and data size. 10.9.7 transfer information modification when ibccs = 1 and the dmac is used, clear the ibccs bit to 0 and then set to 1 again before modifying the dtc transfer information in the cpu exception handling routine initiated by a dtc transfer end interrupt. 10.9.8 endian format the dtc supports big and little endian formats. the endian formats used when transfer information is written to and when transfer information is read from by the dtc must be the same. section 10 data transfer controller (dtc) rev. 1.00 sep. 13, 2007 page 378 of 1102 rej09b0365-0100 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 379 of 1102 rej09b0365-0100 section 11 i/o ports table 11.1 summarizes the port functions. the pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, a port register (port) used to read the pin states, and an input buffer control register (icr) that controls input buffer on/off. ports 4, and 5 do not have a dr or a ddr register. ports d to f and h to k have internal input pull-up moss and a pull-up mos control register (pcr) that controls the on/off state of the input pull-up moss. ports 2 and f include an open-drain control register (odr) that controls on/off of the output buffer pmoss. port n supports 5-v input and functions as an nmos open-drain output pin. all of the i/o ports can drive a single ttl load w ith a capacitive component of up to 30 pf and drive darlington transistors when functioning as output ports. pins on ports 2, 3, j, and k have schmitt-trigger inputs. schmitt-trigger input is enabled for pins of other ports when they are used as irq, tpu, tmr, or iic2 inputs. table 11.1 po rt functions function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function port 1 7 p17/scl0 irq7 -a/ tclkd-b/ adtrg1 -a ? irq7 -a, tclkd-b, scl0 ? ? 6 p16/sda0/ sck3 irq6 -a/ tclkc-b dack1 -a irq6 -a, tclkc-b, sda0 general i/o port function multiplexed with interrupt input, sci i/o, dmac i/o, a/d converter input, tpu input, and iic2 i/o 5 p15/scl1 irq5 -a/ tclkb-b/ rxd3 tend1 -a irq5 -a, tclkb-b, scl1 4 p14/sda1 dreq1 -a/ irq4 -a/ tclka-b txd3 irq4 -a, tclka-b, sda1 3 p13 adtrg0 -a/ irq3 -a ? irq3 -a section 11 i/o ports rev. 1.00 sep. 13, 2007 page 380 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function port 1 2 p12/sck2 irq2 -a dack0 -a irq2 -a ? ? 1 p11 rxd2/ irq1 -a tend0 -a irq1 -a general i/o port function multiplexed with interrupt input, sci i/o, dmac i/o, a/d converter input, tpu input, and iic2 i/o 0 p10 dreq0 -a/ irq0 -a txd2 irq0 -a port 2 7 p27/ tiocb5 tioca5/ irq15 -a po7 all input functions ? o 6 p26/ tioca5 irq14 -a po6/tmo1/ txd1 all input functions general i/o port function multiplexed with interrupt input, ppg output, tpu i/o, tmr i/o, and sci i/o 5 p25/ tioca4 tmci1/ rxd1/ irq13 -a po5 p25, tioca4, tmci1, irq13 -a 4 p24/ tiocb4/ sck1 tioca4/ tmri1/ irq12 -a po4 p24, tiocb4, tioca4, tmri1, irq12 -a 3 p23/ tiocd3 irq11 -a/ tiocc3 po3 all input functions 2 p22/ tiocc3 irq10 -a po2/tmo0/ txd0 all input functions 1 p21/ tioca3 tmci0/ rxd0/ irq9 -a po1 p21, tioca3, tmci0, i rq9 -a 0 p20/ tiocb3/ sck0 tioca3/ tmri0/ irq8 -a po0 p20, tiocb3, tioca3, tmri0, irq8 -a section 11 i/o ports rev. 1.00 sep. 13, 2007 page 381 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function port 3 7 p37/ tiocb2 tioca2/ tclkd-a po15 all input functions ? ? 6 p36/ tioca2 ? po14 all input functions general i/o port function multiplexed with ppg output, dmac i/o, and tpu i/o 5 p35/ tiocb1 tioca1/ tclkc-a po13/ dack1 -b all input functions 4 p34/ tioca1 ? po12/ tend1 -b all input functions 3 p33/ tiocd0 tiocc0/ tclkb-a/ dreq1 -b po11 all input functions 2 p32/ tiocc0 tclka-a po10/ dack0 -b all input functions 1 p31/ tiocb0 tioca0 po9/ tend0 -b all input functions 0 p30/ tioca0 dreq0 -b po8 all input functions port 4 ? p47/an11 ? ? ? ? ? p46/an10 ? general i/o port function multiplexed with a/d converter input ? p45/an9 ? ? p44/an8 ? ? ? ? ? ? ? ? ? ? ? ? ? section 11 i/o ports rev. 1.00 sep. 13, 2007 page 382 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function port 5 7 ? p57/an7/ irq7 -b da1 irq7 -b ? ? 6 ? p56/an6/ irq6 -b da0 irq6 -b 5 ? p55/an5/ irq5 -b ? irq5 -b general input port function multiplexed with interrupt input, a/d converter input, and d/a converter output 4 ? p54/an4/ irq4 -b ? irq4 -b 3 ? p53/an3/ irq3 -b ? irq3 -b 2 ? p52/an2/ irq2 -b ? irq2 -b 1 ? p51/an1/ irq1 -b ? irq1 -b 0 ? p50/an0/ irq0 -b ? irq0 -b port 6 7 p67 irq15 -b ? irq15 -b ? ? 6 p66 ? ? ? 5 p65/sck6 tck/ irq13 -b tmo3/ dack3 irq13 -b, tck 4 p64 tmci3/tdi/ irq12 -b/ rxd6 tend3 tmci3/ irq12 -b, tdi 3 p63 tmri3/ dreq3 / irq11 -b/ tms txd6 tmri3, irq11 -b, tms 2 p62/sck4 irq10 -b/ trst tmo2/ dack2 irq10 -b, trst 1 p61 tmci2/ rxd4/ irq9 -b tend2 tmci2, irq9 -b general i/o port function multiplexed with tmr i/o, sci i/o, dmac i/o, h-udi input, and interrupt input 0 p60 tmri2/ dreq2 / irq8 -b txd4 tmri2, irq8 -b section 11 i/o ports rev. 1.00 sep. 13, 2007 page 383 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function port a 7 ? pa7 b ? ? ? 6 pa6 ? as / ah / bs -b 5 pa5 ? rd 4 pa4 ? lhwr / lub 3 pa3 ? llwr / llb 2 pa2 breq / wait-a ? 1 pa1 ? back / (rd/ wr -a) general i/o port function multiplexed with system clock output and bus control i/o 0 pa0 ? breqo / bs -a port b 7 pb7 ? cs7 -d ? ? ? 6 pb6 adtrg0 -b cs6 -d (rd/ wr -b) 5 pb5 ? cs5 -d 4 pb4 ? cs4 -b 3 pb3 ? cs3 -a/ cs7 -a 2 pb2 ? cs2 -a/ cs6 -a 1 pb1 ? cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b general i/o port function multiplexed with bus control output 0 pb0 ? cs0 / cs4 -a/ cs5 -b section 11 i/o ports rev. 1.00 sep. 13, 2007 page 384 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function port c 7 ? ? ? ? ? ? 6 ? ? ? 5 pc5 ? ? 4 pc4 adtrg2 ? 3 pc3 ? ? 2 pc2 ? ? 1 pc1 ? cs4 -c/ cs5 -c/ cs6 -c/ cs7 -c general i/o port function multiplexed with bus control i/o and a/d converter input 0 pc0 wait-b/ adtrg1 -b cs3 -b 7 pd7 ? a7 ? o ? port d * 3 6 pd6 ? a6 5 pd5 ? a5 general i/o port function multiplexed with address output 4 pd4 ? a4 3 pd3 ? a3 2 pd2 ? a2 1 pd1 ? a1 0 pd0 ? a0 7 pe7 ? a15 ? o ? port e * 3 6 pe6 ? a14 5 pe5 ? a13 general i/o port function multiplexed with address output 4 pe4 ? a12 3 pe3 ? a11 2 pe2 ? a10 1 pe1 ? a9 0 pe0 ? a8 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 385 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 pf7/sck5 ? a23 ? o o 6 pf6 rxd5/irrxd a22 5 pf5 ? a21/ txd5/ irtxd/ 4 pf4 ? a20 3 pf3 ? a19 2 pf2 ? a18 1 pf1 ? a17 port f general i/o port function multiplexed with address output and sci i/o 0 pf0 ? a16 7 ph7/d7 * 2 ? ? ? o ? port h 6 ph6/d6 * 2 ? ? 5 ph5/d5 * 2 ? ? general i/o port function multiplexed with bi-directional data bus 4 ph4/d4 * 2 ? ? 3 ph3/d3 * 2 ? ? 2 ph2/d2 * 2 ? ? 1 ph1/d1 * 2 ? ? 0 ph0/d0 * 2 ? ? 7 pi7/d15 * 2 ? ? ? o ? port i 6 pi6/d14 * 2 ? ? 5 pi5/d13 * 2 ? ? general i/o port function multiplexed with bi-directional data bus 4 pi4/d12 * 2 ? ? 3 pi3/d11 * 2 ? ? 2 pi2/d10 * 2 ? ? 1 pi1/d9 * 2 ? ? 0 pi0/d8 * 2 ? ? section 11 i/o ports rev. 1.00 sep. 13, 2007 page 386 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 pj7/ tiocb8 tioca8/ tclkh po23 all input functions o ? 6 pj6/ tioca8 ? po22 all input functions 5 pj5/ tiocb7 tioca7/ tclkg po21 all input functions 4 pj4/ tioca7 ? po20 all input functions 3 pj3/ tiocd6 tiocc6/ tclkf po19 all input functions 2 pj2/ tiocc6 tclke po18 all input functions 1 pj1/ tiocb6 tioca6 po17 all input functions port j * 4 general i/o port function multiplexed with ppg and tpu i/o 0 pj0/ tioca6 ? po16 all input functions 7 pk7/ tiocb11 tioca11 po31 all input functions o ? port k * 4 6 pk6/ tioca11 ? po30 all input functions 5 pk5/ tiocb10 tioca10 po29 all input functions general i/o port function multiplexed with ppg and tpu i/o 4 pk4/ tioca10 ? po28 all input functions 3 pk3/ tiocd9 tiocc9 po27 all input functions 2 pk2/ tiocc9 ? po26 all input functions 1 pk1/ tiocb9 tioca9 po25 all input functions 0 pk0/ tioca9 ? po24 all input functions section 11 i/o ports rev. 1.00 sep. 13, 2007 page 387 of 1102 rej09b0365-0100 function port description bit i/o input output schmitt- trigger input * 1 input pull-up mos function open- drain output function 7 ? ? ? ? ? o port n * 5 6 ? ? ? 5 ? ? ? 4 ? ? ? 3 pn3/scl3 ? ? scl3 2 pn2/sda3 ? ? sda3 1 pn1/scl2 ? ? scl2 general i/o port function multiplexed with iic2 i/o 0 pn0/sda2 ? ? sda2 notes: 1. pins without schmitt-trigger input buffer have cmos input buffer. 2. addresses are also output when accessing to the address/data multiplexed i/o space. 3. ports d and e are disabled when pcjke = 1. 4. ports j and k are disabled when pcjke = 0. 5. output on the pins of port n is always nmos open-drain output. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 388 of 1102 rej09b0365-0100 11.1 register descriptions table 11.2 lists each port registers. table 11.2 register configuration in each port registers port number of pins ddr dr port icr pcr odr port 1 8 o o o o ? ? port 2 8 o o o o ? o port 3 8 o o o o ? ? port 4 4 ? ? o o ? ? port 5 8 ? ? o o ? ? port 6 8 o o o o ? ? port a 8 o o o o ? ? port b 8 o o o o ? ? port c * 1 6 o o o o ? ? port d * 2 8 o o o o o ? port e * 2 8 o o o o o ? port f 8 o o o o o o port h 8 o o o o o ? port i 8 o o o o o ? port j * 3 8 o o o o o ? port k * 3 8 o o o o o ? port n 4 o o o o ? ? [legend] o: register exists ? : no register exists note: 1. write the initial value to any of bits in port c registers. 2. do not access port d or e registers when pcjke = 1. 3. do not access port j or k registers when pcjke = 0. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 389 of 1102 rej09b0365-0100 11.1.1 data direction register (pnddr) (n = 1, 2, 3, 6, a, to f, h to k, and n) ddr is an 8-bit write-only register that specifies the port input or output fo r each bit. a read from the ddr is invalid and ddr is alwa ys read as an undefined value. when the general i/o port function is selected, the corresponding pin functions as an output port by setting the corresponding ddr bit to 1; the corresponding pin functions as an input port by clearing the corresponding ddr bit to 0. the initial ddr values are shown in table 11.3. bit bit name initial value r/w notes: the lower six bits of port c registers are effective while the upper two bits are reserved. do not access port j or port k registers when pcjke = 0. do not access port d or port e registers when pcjke = 1. 7 pn7ddr 0 w 6 pn6ddr 0 w 5 pn5ddr 0 w 4 pn4ddr 0 w 3 pn3ddr 0 w 2 pn2ddr 0 w 1 pn1ddr 0 w 0 pn0ddr 0 w table 11.3 startup mode and initial value startup mode port external extended mode single-chip mode port a h'80 h'00 other ports h'00 h'00 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 390 of 1102 rej09b0365-0100 11.1.2 data register (pndr) (n = 1, 2, 3, 6, a, to f, h to k, and n) dr is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. the initial value of dr is h'00. notes: the lower six bits of port c registers are effective while the upper two bits are reserved. do not access port j or port k registers when pcjke = 0. do not access port d or port e registers when pcjke = 1. bit bit name initial value r/w 7 pn7dr 0 r/w 6 pn6dr 0 r/w 5 pn5dr 0 r/w 4 pn4dr 0 r/w 3 pn3dr 0 r/w 2 pn2dr 0 r/w 1 pn1dr 0 r/w 0 pn0dr 0 r/w 11.1.3 port register (portn) (n = 1 to 6, a to f, h to k, and n) port is an 8-bit read-only register that reflects the port pin state. a write to port is invalid. when port is read, the dr bits that correspond to th e respective ddr bits set to 1 are read and the status of each pin whose corr esponding ddr bit is cleared to 0 is also read regardless of the icr value. the initial value of port is undefined and is determined based on the port pin state. notes: the higher four bits of port 4 registers are effective while the lower four bits are reserved. the lower four bits of port n registers are effective while the upper four bits are reserved. the lower six bits of port c registers are effective while the upper two bits are reserved. do not access port j or port k registers when pcjke = 0. do not access port d or port e registers when pcjke = 1. bit bit name initial value r/w 7 pn7 undefined r 6 pn6 undefined r 5 pn5 undefined r 4 pn4 undefined r 3 pn3 undefined r 2 pn2 undefined r 1 pn1 undefined r 0 pn0 undefined r section 11 i/o ports rev. 1.00 sep. 13, 2007 page 391 of 1102 rej09b0365-0100 11.1.4 input buffer control re gister (pnicr) (n = 1 to 6, a to f, h to k, and n) icr is an 8-bit readable/writable register that controls the port input buffers. for bits in icr set to 1, the input buffers of the corresponding pins are valid. for bits in icr cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. when the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. the initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. when port is read, the pin state is always read regardless of the icr value. when the icr value is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral module. if icr is modified, an internal edge may occur depending on the pin state. accordingly, icr should be modified when the corresponding input pins are not used. for example, an irq input, modify icr while the corresponding interrupt is disabled, clear the irqf flag in isr of the interrupt controller to 0, and then enable the corr esponding interrupt. if an edge occurs after the icr setting, the edge should be cancelled. the initial value of icr is h'00. notes: the higher four bits of port 4 registers are effective while the lower four bits are reserved. the lower four bits of port n registers are effective while the upper four bits are reserved. the lower six bits of port c registers are effective while the upper two bits are reserved. do not access port j or port k registers when pcjke = 0. do not access port d or port e registers when pcjke = 1. bit bit name initial value r/w 7 pn7icr 0 r/w 6 pn6icr 0 r/w 5 pn5icr 0 r/w 4 pn4icr 0 r/w 3 pn3icr 0 r/w 2 pn2icr 0 r/w 1 pn1icr 0 r/w 0 pn0icr 0 r/w section 11 i/o ports rev. 1.00 sep. 13, 2007 page 392 of 1102 rej09b0365-0100 11.1.5 pull-up mos control register (pnpcr) (n = d to f and h to k) pcr is an 8-bit readable/writable register that controls on/off of the port input pull-up mos. if a bit in pcr is set to 1 while the pin is in input state, the input pull-up mos corresponding to the bit in pcr is turned on. table 11.4 shows the input pull-up mos status. the initial value of pcr is h'00. bit bit name initial value r/w 7 pn7pcr 0 r/w 6 pn6pcr 0 r/w 5 pn5pcr 0 r/w 4 pn4pcr 0 r/w 3 pn3pcr 0 r/w 2 pn2pcr 0 r/w 1 pn1pcr 0 r/w 0 pn0pcr 0 r/w table 11.4 input pull-up mos state port pin state reset hardware standby mode software standby mode other operation port d address output off off off off port output off off off off port input off off on/off on/off port e address output off off off off port output off off off off port input off off on/off on/off port f address output off off off off peripheral module ou tput off off off off port output off off off off port input off off on/off on/off port h data input/output off off off off port output off off off off port input off off on/off on/off port i data input/output off off off off port output off off off off port input off off on/off on/off port j peripheral module output off off off off port output off off off off port input off off on/off on/off section 11 i/o ports rev. 1.00 sep. 13, 2007 page 393 of 1102 rej09b0365-0100 port pin state reset hardware standby mode software standby mode other operation port k peripheral module output off off off off port output off off off off port input off off on/off on/off [legend] off: the input pull-up mos is always off. on/off: if pcr is set to 1, the input pull-up mos is on; if pcr is cleared to 0, the input pull-up mos is off. 11.1.6 open-drain control register (pnodr) (n = 2 and f) odr is an 8-bit readable/writable register th at selects the open-dra in output function. if a bit in odr is set to 1, the pin corresponding to that bit in odr functions as an nmos open- drain output. if a bit in odr is cleared to 0, the pin corresponding to that bit in odr functions as a cmos output. the initial value of odr is h'00. bit bit name initial value r/w 7 pn7odr 0 r/w 6 pn6odr 0 r/w 5 pn5odr 0 r/w 4 pn4odr 0 r/w 3 pn3odr 0 r/w 2 pn2odr 0 r/w 1 pn1odr 0 r/w 0 pn0odr 0 r/w 11.2 output buffer control this section describes the ou tput priority of each pin. the name of each peripheral module pin is followed by "_oe". this (for example: tioca4_oe) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). table 11.5 lists each port output signal's vali d setting. for details on the corresponding output signals, see the register description of each peripheral module. if the name of each peripheral module pin is followed by a or b, the pin function can be modified by the port function control register (pfcr). for details, see section 11.3, port function controller. for a pin whose initial value changes according to the activation mode, "initial value e" indicates the initial value when the lsi is started up in external extended mode and "initial value s" indicates the initial value when the lsi is started in single-chip mode. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 394 of 1102 rej09b0365-0100 11.2.1 port 1 (1) p17/ irq7 -a/tclkd-b/scl0/ adtrg1 -a the pin function is switched as shown below according to the combination of the iic2 register setting and p17ddr bit setting. setting iic2 i/o port module name pin function scl0_oe p17ddr iic2 scl0 input/output 1 ? i/o port p17 output 0 1 p17 input (initial setting) 0 0 (2) p16/ dack1 -a/ irq6 -a/tclkc-b/sda0/sck3 the pin function is switched as shown below according to the combination of the dmac, sci, and iic2 register setting and p16ddr bit setting. setting dmac sci iic2 i/o port module name pin function dack1a _oe sck3_oe sda0_oe p16ddr dmac dack1 -a output 1 ? ? ? sci sck3 output 0 1 ? ? iic2 sda0 input/output 0 0 1 ? i/o port p16 output 0 0 0 1 p16 input (initial setting) 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 395 of 1102 rej09b0365-0100 (3) p15/rxd3/ tend1 -a/ irq5 -a/tclkb-b/scl1 the pin function is switched as shown below according to the combination of the dmac and iic2 register setting and p15ddr bit setting. setting dmac iic2 i/o port module name pin function tend1a _oe scl1_oe p15ddr dmac tend1 -a output 1 ? ? iic2 scl1 input/output 0 1 ? i/o port p15 output 0 0 1 p15 input (initial setting) 0 0 0 (4) p14/txd3/ dreq1 -a/ irq4 -a/tclka-b/sda1 the pin function is switched as shown below according to the combination of the sci and iic2 register setting and p14ddr bit setting. setting sci iic2 i/o port module name pin function txd3_oe sda1_oe p14ddr sci txd3 output 1 ? ? iic2 sda1 input/output 0 1 ? i/o port p14 output 0 0 1 p14 input (initial setting) 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 396 of 1102 rej09b0365-0100 (5) p13/ adtrg0 -a/ irq3 -a the pin function is switched as shown below according to the p13ddr bit setting. setting i/o port module name pin function p13ddr i/o port p13 output 1 p13 input (initial setting) 0 (6) p12/sck2/ dack0 -a/ irq2 -a the pin function is switched as shown below according to the combination of the dmac and sci register settings and p12ddr bit setting. setting dmac sci i/o port module name pin function dack0a _oe sck2_oe p12ddr dmac dack0 -a output 1 ? ? sci sck2 output 0 1 ? i/o port p12 output 0 0 1 p12 input (initial setting) 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 397 of 1102 rej09b0365-0100 (7) p11/rxd2/ tend0 -a/ irq1 -a the pin function is switched as shown below according to the combination of the dmac register setting and p11ddr bit setting. setting dmac i/o port module name pin function tend0a _oe p11ddr dmac tend0 -a output 1 ? i/o port p11 output 0 1 p11 input (initial setting) 0 0 (8) p10/txd2/ dreq0 -a/ irq0 -a: the pin function is switched as shown below according to the combination of the sci register setting and p10ddr bit setting. setting sci i/o port module name pin function txd2_oe p10ddr sci txd2 output 1 ? p10 output 0 1 i/o port p10 input (initial setting) 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 398 of 1102 rej09b0365-0100 11.2.2 port 2 (1) p27/po7/tioca5/tiocb5/ irq15 -a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p27ddr bit setting. setting tpu ppg i/o port module name pin function tiocb5_oe po7_oe p27ddr tpu tiocb5 output 1 ? ? ppg po7 output 0 1 ? p27 output 0 0 1 i/o port p27 input (initial setting) 0 0 0 (2) p26/po6/tioca5/tmo1/txd1/ irq14 -a the pin function is switched as shown below acc ording to the combination of the tpu, tmr, sci, and ppg register settings and p26ddr bit setting. setting tpu tmr sci ppg i/o port module name pin function tioca5_oe tmo1_oe txd1_oe po6_oe p26ddr tpu tioca5 output 1 ? ? ? ? tmr tmo1 output 0 1 ? ? ? sci txd1 output 0 0 1 ? ? ppg po6 output 0 0 0 1 ? p26 output 0 0 0 0 1 i/o port p26 input (initial setting) 0 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 399 of 1102 rej09b0365-0100 (3) p25/po5/tioca4/tmci1/rxd1/ irq13 -a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p25ddr bit setting. setting tpu ppg i/o port module name pin function tioca4_oe po5_oe p25ddr tpu tioca4 output 1 ? ? ppg po5 output 0 1 ? p25 output 0 0 1 i/o port p25 input (initial setting) 0 0 0 (4) p24/po4/tioca4/tiocb4/tmri1/sck1/ irq12 -a the pin function is switched as shown below according to the combination of the tpu, sci, and ppg register settings and p24ddr bit setting. setting tpu sci ppg i/o port module name pin function tio cb4_oe sck1_oe po4_oe p24ddr tpu tiocb4 output 1 ? ? ? sci sck1 output 0 1 ? ? ppg po4 output 0 0 1 ? p24 output 0 0 0 1 i/o port p24 input (initial setting) 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 400 of 1102 rej09b0365-0100 (5) p23/po3/tiocc3/tiocd3/ irq11 -a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p23ddr bit setting. setting tpu ppg i/o port module name pin function tiocd3_oe po3_oe p23ddr tpu tiocd3 output 1 ? ? ppg po3 output 0 1 ? p23 output 0 0 1 i/o port p23 input (initial setting) 0 0 0 (6) p22 /po2/tiocc3/tmo0/txd0/ irq10 -a the pin function is switched as shown below according to the combination of the tpu, tmr, sci, and ppg register settings and p22ddr bit setting. setting tpu tmr sci ppg i/o port module name pin function tiocc3_oe tmo0_oe txd0_oe po2_oe p22ddr tpu tiocc3 output 1 ? ? ? ? tmr tmo0 output 0 1 ? ? ? sci txd0 output 0 0 1 ? ? ppg po2 output 0 0 0 1 ? p22 output 0 0 0 0 1 i/o port p22 input (initial setting) 0 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 401 of 1102 rej09b0365-0100 (7) p21/po1/tioca3/tmci0/rxd0/ irq9 -a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p21ddr bit setting. setting tpu ppg i/o port module name pin function tioca3_oe po1_oe p21ddr tpu tioca3 output 1 ? ? ppg po1 output 0 1 ? p21 output 0 0 1 i/o port p21 input (initial setting) 0 0 0 (8) p20/po0/tioca3/tiocb3/tmri0/sck0/ irq8 -a the pin function is switched as shown below according to the combination of the tpu, sci, and ppg register settings and p20ddr bit setting. setting tpu sci ppg i/o port module name pin function t iocb3_oe sck0_oe po0_oe p20ddr tpu tiocb3 output 1 ? ? ? sci sck0 output 0 1 ? ? ppg po0 output 0 0 1 ? p20 output 0 0 0 1 i/o port p20 input (initial setting) 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 402 of 1102 rej09b0365-0100 11.2.3 port 3 (1) p37/po15/tioca2/tiocb2/tclkd-a the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p37ddr bit setting. setting tpu ppg i/o port module name pin function tiocb2_oe po15_oe p37ddr tpu tiocb2 output 1 ? ? ppg po15 output 0 1 ? p37 output 0 0 1 i/o port p37 input (initial setting) 0 0 0 (2) p36/po14/tioca2 the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p36ddr bit setting. setting tpu ppg i/o port module name pin function tioca2_oe po14_oe p36ddr tpu tioca2 output 1 ? ? ppg po14 output 0 1 ? p36 output 0 0 1 i/o port p36 input (initial setting) 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 403 of 1102 rej09b0365-0100 (3) p35/po13/tioca1/tiocb1/tclkc-a/ dack1 -b the pin function is switched as shown below according to the combination of the dmac, tpu, and ppg register settings and p35ddr bit setting. setting dmac tpu ppg i/o port module name pin function dack1b _oe tiocb1_oe po13_oe p35ddr dmac dack1 -b output 1 ? ? ? tpu tiocb1 output 0 1 ? ? ppg po13 output 0 0 1 ? p35 output 0 0 0 1 i/o port p35 input (initial setting) 0 0 0 0 (4) p34/po12/tioca1/ tend1 -b the pin function is switched as shown below according to the combination of the dmac, tpu, and ppg register settings and p34ddr bit setting. setting dmac tpu ppg i/o port module name pin function tend1b _oe tioca1_oe po12_oe p34ddr dmac tend1 -b output 1 ? ? ? tpu tioca1 output 0 1 ? ? ppg po12 output 0 0 1 ? p34 output 0 0 0 1 i/o port p34 input (initial setting) 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 404 of 1102 rej09b0365-0100 (5) p33/po11/tiocc0/tiocd0/tclkb-a/ dreq1 -b the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p33ddr bit setting. setting tpu ppg i/o port module name pin function tiocd0_oe po11_oe p33ddr tpu tiocd0 output 1 ? ? ppg po11 output 0 1 ? p33 output 0 0 1 i/o port p33 input (initial setting) 0 0 0 (6) p32/po10/tiocc0/tclka-a/ dack0 -b the pin function is switched as shown below according to the combination of the dmac, tpu, and ppg register settings and p32ddr bit setting. setting dmac tpu ppg i/o port module name pin function dack 0b_oe tiocc0_oe po10_oe p32ddr dmac dack0 -b output 1 ? ? ? tpu tiocc0 output 0 1 ? ? ppg po10 output 0 0 1 ? p32 output 0 0 0 1 i/o port p32 input (initial setting) 0 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 405 of 1102 rej09b0365-0100 (7) p31/po9/tioca0/tiocb0/ tend0 -b the pin function is switched as shown below according to the combination of the dmac, tpu, and ppg register settings and p31ddr bit setting. setting dmac tpu ppg i/o port module name pin function tend0b _oe tiocb0_oe po9_oe p31ddr dmac tend0 -b output 1 ? ? ? tpu tiocb0 output 0 1 ? ? ppg po9 output 0 0 1 ? p31 output 0 0 0 1 i/o port p31 input (initial setting) 0 0 0 0 (8) p30/po8/tioca0/ dreq0 -b the pin function is switched as shown below according to the combination of the tpu and ppg register settings and p33ddr bit setting. setting tpu ppg i/o port module name pin function tioca0_oe po8_oe p30ddr tpu tioca0 output 1 ? ? ppg po8 output 0 1 ? p30 output 0 0 1 i/o port p30 input (initial setting) 0 0 0 11.2.4 port 5 (1) p57/an7/da1/ irq7 -b module name pin function d/a converter da1 output section 11 i/o ports rev. 1.00 sep. 13, 2007 page 406 of 1102 rej09b0365-0100 (2) p56/an6/da0/ irq6 -b module name pin function d/a converter da0 output 11.2.5 port 6 (1) p67/ irq15 -b. p66 the pin function is switched as shown below according to the p6nddr setting. setting i/o port module name pin function p6nddr i/o port p6n output 1 p6n input (initial setting) 0 [legend] n: 7, 6 (2) p65/tmo3/ dack3 /tck/sck6/ irq13 -b the pin function is switched as shown below according to the combination of operation mode, the dmac, tmr, and sci register settings and p65ddr bit setting. setting sci dmac tmr i/o port module name pin function mcu operating mode sck6 _oe dack3 _oe tmo3_oe p65ddr sci sck6 output 1 ? ? ? dmac dack3 output 0 1 ? ? tmr tmo3 output 0 0 1 ? p65 output 0 0 0 1 i/o port p65 input (initial setting) modes other than the boundary scan enabled mode * 0 0 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 407 of 1102 rej09b0365-0100 (3) p64/tmci3/ tend3 /tdi/rxd6/ irq12 -b the pin function is switched as shown below according to the combination of operation mode, the dmac register setting and p64ddr bit setting. setting dmac i/o port module name pin function mcu operating mode tend3 _oe p64ddr dmac tend3 output 1 ? i/o port p64 output 0 1 p64 input (initial setting) modes other than the boundary scan enabled mode * 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. (4) p63/tmri3/ dreq3 / irq11 -b/txd6/tms the pin function is switched as shown below according to the combination of operation mode, the sci register setting and p63ddr bit setting. setting sci i/o port module name pin function mcu operating mode txd6_oe p63ddr sci txd6 output 1 ? i/o port p63 output 0 1 p63 input (initial setting) modes other than the boundary scan enabled mode * 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 408 of 1102 rej09b0365-0100 (5) p62/tmo2/sck4/ dack2 / irq10 -b/ trst the pin function is switched as shown below according to the combination of the dmac, tmr, and sci register settings and p62ddr bit setting. setting dmac tmr sci i/o port module name pin function mcu operating mode dack2 _oe tmo2_oe sck4_oe p62ddr dmac dack2 output 1 ? ? ? tmr tmo2 output 0 1 ? ? sci sck4 output 0 0 1 ? p62 output 0 0 0 1 i/o port p62 input (initial setting) modes other than the boundary scan enabled mode * 0 0 0 0 note: * these pins are boundary scan dedicated input pins during boundary scan enabled mode. (6) p61/tmci2/rxd4/ tend2 / irq9 -b the pin function is switched as shown below according to the combination of the dmac register setting and p61ddr bit setting. setting dmac i/o port module name pin function tend2 _oe p61ddr dmac tend2 output 1 ? i/o port p61 output 0 1 p61 input (initial setting) 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 409 of 1102 rej09b0365-0100 (7) p60/tmri2/txd4/ dreq2 / irq8 -b the pin function is switched as shown below according to the combination of the sci register setting and p60ddr bit setting. setting sci i/o port module name pin function txd4_oe p60ddr sci txd4 output 1 ? p60 output 0 1 i/o port p60 input (initial setting) 0 0 11.2.6 port a (1) pa7/b the pin function is switched as shown below according to the pa7ddr bit setting. setting i/o port module name pin function pa7ddr i/o port b output (initial setting e) 1 pa7 input (initial setting s) 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode section 11 i/o ports rev. 1.00 sep. 13, 2007 page 410 of 1102 rej09b0365-0100 (2) pa6/ as / ah / bs -b the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and the pa6ddr bit settings. setting bus controller i/o port module name pin function ah _oe bsb _oe as _oe pa6ddr ah output * 1 ? ? ? bs -b output * 0 1 ? ? bus controller as output * (initial setting e) 0 0 1 ? pa6 output 0 0 0 1 i/o port pa6 input (initial setting s) 0 0 0 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode note: * valid in external extended mode (expe = 1) (3) pa5/ rd the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the pa5ddr bit settings. setting mcu operating mode i/o port module name pin function expe pa5ddr bus controller rd output * (initial setting e) 1 ? pa5 output 0 1 i/o port pa5 input (initial setting s) 0 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 411 of 1102 rej09b0365-0100 (4) pa4/ lhwr / lub the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and the pa4ddr bit settings. setting bus controller i/o port module name pin function lub _oe * 2 lhwr _oe * 2 pa4ddr lub output * 1 1 ? ? bus controller lhwr output * 1 (initial setting e) ? 1 ? pa4 output 0 0 1 i/o port pa4 input (initial setting s) 0 0 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode notes: 1. valid in external extended mode (expe = 1) 2. when the byte control sram space is ac cessed while the byte control sram space is specified or while lhwr _oe = 1, this pin functions as the lub output; otherwise, the lhwr output. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 412 of 1102 rej09b0365-0100 (5) pa3/ llwr / llb the pin function is switched as shown below acc ording to the combination of operating mode, expe bit, bus controller register, and the pa3ddr bit settings. setting bus controller i/o port module name pin function llb _oe * 2 llwr _oe * 2 pa3ddr llb output * 1 1 ? ? bus controller llwr output * 1 (initial setting e) ? 1 ? pa3 output 0 0 1 i/o port pa3 input (initial setting s) 0 0 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode notes: 1. valid in external extended mode (expe = 1) 2. if the byte control sram space is accessed, this pin functions as the llb output; otherwise, the llwr . (6) pa2/ breq /wait-a the pin function is switched as shown below according to the combination of the bus controller register setting and the pa2ddr bit setting. setting bus controller i/o port module name pin function bcr_brle bcr_waite pa2ddr breq input 1 ? ? bus controller wait-a input 0 1 ? pa2 output 0 0 1 i/o port pa2 input (initial setting) 0 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 413 of 1102 rej09b0365-0100 (7) pa1/ back /(rd/ wr -a) the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and the pa1ddr bit settings. setting bus controller i/o port module name pin function back _oe byte control sram selection (rd/ wr )_oe pa1ddr back output * 1 ? ? ? 0 1 ? ? bus controller rd/ wr output * 0 0 1 ? pa1 output 0 0 0 1 i/o port pa1 input (initial setting) 0 0 0 0 note: * valid in external extended mode (expe = 1) (8) pa0/ breqo / bs -a the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and the pa0ddr bit settings. setting i/o port bus controller i/o port module name pin function bsa _oe breqo _oe pa0ddr bs -a output * 1 ? ? bus controller breqo output * 0 1 ? pa0 output 0 0 1 i/o port pa0 input (initial setting) 0 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 414 of 1102 rej09b0365-0100 11.2.7 port b (1) pb7/ cs7 -d the pin function is switched as shown below according to the combination of operating mode, expe bit, port function control register (pfcr), and pb7ddr bit settings. setting bus controller i/o port module name pin function cs7d _oe pb7ddr bus controller cs7-d output * 1 ? pb7 output 0 1 i/o port pb7 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) (2) pb6/ cs6 -d/(rd/ wr -b)/ adtrg0 -b the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and pb6ddr bit settings. setting i/o port module name pin function byte control sram selection (rd/ wr )- b_oe cs6d _oe pb6ddr 1 ? ? ? rd/ wr -b output * 0 1 ? ? bus controller cs6-d output * 0 0 1 ? pb6 output 0 0 0 1 i/o port pb6 input (initial setting) 0 0 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 415 of 1102 rej09b0365-0100 (3) pb5/ cs5 -d the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and pb5ddr bit. setting i/o port module name pin function cs5d _oe pb5ddr bus controller cs5 -d output * 1 ? pb5 output 0 1 i/o port pb5 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) (4) pb4/ cs4 -b the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and pb4ddr bit settings. setting bus controller i/o port module name pin function cs4b _oe pb4ddr bus controller cs4-b output * 1 ? pb4 output 0 1 i/o port pb4 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 416 of 1102 rej09b0365-0100 (5) pb3/ cs3 -a/ cs7 -a the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and the pb3ddr bit settings. setting bus controller i/o port module name pin function cs3a _oe cs7a _oe pb3ddr cs3 -a output * 1 ? ? bus controller cs7 -a output * ? 1 ? pb3 output 0 0 1 i/o port pb3 input (initial setting) 0 0 0 note: * valid in external extended mode (expe = 1) (6) pb2/ cs2 -a/ cs6 -a the pin function is switched as shown below according to the combination of operating mode, expe bit, bus controller register, port function control register (pfcr), and the pb2ddr bit settings. setting bus controller i/o port module name pin function cs2a _oe cs6a _oe pb2ddr cs2 -a output * 1 ? ? bus controller cs6 -a output * ? 1 ? pb2 output 0 0 1 i/o port pb2 input (initial setting) 0 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 417 of 1102 rej09b0365-0100 (7) pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b the pin function is switched as shown below according to the combination of operating mode, expe bit, port function control register (pfcr), and the pb1ddr bit settings. setting i/o port module name pin function cs1 _oe cs2b _oe cs5a _oe cs6b _oe cs7b _oe pb1ddr cs1 output * 1 ? ? ? ? ? cs2 -b output * ? 1 ? ? ? ? cs5 -a output * ? ? 1 ? ? ? cs6 -b output * ? ? ? 1 ? ? bus controller cs7 -b output * ? ? ? ? 1 ? pb1 output 0 0 0 0 0 1 i/o port pb1 input (initial setting) 0 0 0 0 0 0 note: * valid in external extended mode (expe = 1) (8) pb0/ cs0 / cs4 -a/ cs5 -b the pin function is switched as shown below according to the combination of operating mode, expe bit, port function control register (pfcr), and the pb0ddr bit settings. setting i/o port module name pin function cs0 _oe cs4a _oe cs5b _oe pb0ddr cs0 output (initial setting e) 1 ? ? ? cs4 -a output ? 1 ? ? bus controller cs5 -b output ? ? 1 ? pb0 output 0 0 0 1 i/o port pb0 input (initial setting s) 0 0 0 0 [legend] initial setting e: initial setting in on- chip rom disabled external extended mode initial setting s: initial setting in other modes section 11 i/o ports rev. 1.00 sep. 13, 2007 page 418 of 1102 rej09b0365-0100 11.2.8 port c (1) pc5, pc4/ adtrg2 -a, pc3, pc2 the pin function is switched as shown below according to the pcnddr bit setting. setting i/o port module name pin function pcnddr pcn output 1 i/o port pcn input (initial setting) 0 [legend] n: 2 to 5 (2) pc1/ cs4 -c/ cs5 -c/ cs6 -c/ cs7 -c the pin function is switched as shown below according to the combination of operating mode, expe bit, port function control register (pfcr), and pc1ddr bit settings. setting i/o port module name pin function cs4c _oe cs5c _oe cs6c _oe cs7c _oe pc1ddr cs4 -c output * 1 ? ? ? ? cs5 -c output * ? 1 ? ? ? cs6 -c output * ? ? 1 ? ? bus controller cs7 -c output * ? ? ? 1 ? pc1 output 0 0 0 0 1 i/o port pc1 input (initial setting) 0 0 0 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 419 of 1102 rej09b0365-0100 (3) pc0/ cs3 -b/wait-b/ adtrg1 -b the pin function is switched as shown below according to the combination of operating mode, expe bit, port function control register (pfcr), and pc1ddr bit settings. setting bus controller i/o port module name pin function waite bit in bcr cs3b _oe pc0ddr wait-b input * 1 ? ? bus controller cs3 -b * 0 1 ? pc0 output 0 0 1 i/o port pc0 input (initial setting) 0 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 420 of 1102 rej09b0365-0100 11.2.9 port d the pin function of port d can be switched with that of port j according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port d can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for details, see section 11.3.11, port function control register d (pfcrd). (1) pd7/a7, pd6/a6, pd5/a5, pd4/a4, pd3/a3, pd2/a2, pd1/a1, pd0/a0 the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the pdnddr bit settings. setting i/o port module name pin function mcu operating mode pdnddr on-chip rom disabled extended mode ? bus controller address output on-chip rom enabled extended mode 1 pdn output single-chip mode * 1 i/o port pdn input (initial setting) modes other than on-chip rom disabled extended mode 0 [legend] n: 0 to 7 note: * address output is enabled by setting pdnddr = 1 in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 421 of 1102 rej09b0365-0100 11.2.10 port e the pin function of port e can be switched with that of port k according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port e can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for detail, see section 11.3.11, port function control register d (pfcrd). (1) pe7/a15, pe6/a14, pe5/a13, pe4/a12, pe3/a11, pe2/a10, pe1/a9, pe0/a8 the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the penddr bit settings. setting i/o port module name pin function mcu operating mode penddr on-chip rom disabled extended mode ? bus controller address output on-chip rom enabled extended mode 1 pen output single-chip mode * 1 i/o port pen input (initial setting) modes other than on-chip rom disabled extended mode 0 [legend] n: 0 to 7 note: * address output is enabled by setting pdnddr = 1 in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 422 of 1102 rej09b0365-0100 11.2.11 port f (1) pf7/a23/sck5 the pin function is switched as shown below according to the combination of sci register, operating mode, expe bit, port function control register (pfcr), and pf7ddr bit settings. setting sci i/o port module name pin function sck5_oe a23_oe pf7ddr sci sck5 output 1 ? ? bus controller a23 output * 0 1 ? pf7 output 0 0 1 i/o port pf7 input (initial setting) 0 0 0 note: * valid in external extended mode (expe = 1) (2) pf6/a22/rxd5/irrxd the pin function is switched as shown below according to the combination of operating mode, expe bit, port function control regist er (pfcr), and pf6ddr bit settings. setting i/o port i/o port module name pin function a22_oe pf6ddr bus controller a22 output * 1 ? pf6 output 0 1 i/o port pf6 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 423 of 1102 rej09b0365-0100 (3) pf5/a21/txd5/irtxd the pin function is switched as shown below according to the combination of sci and irda registers, operating mode, expe bit, port function control register (pfcr), and pf5ddr bit settings. setting sci irda i/o port module name pin function txd5_oe irtxd_oe a21_oe pf5ddr sci txd5 output 1 ? ? ? irda irtxd output 0 1 ? ? bus controller a21 output * 0 0 1 ? pf5 output 0 0 0 1 i/o port pf5 input (initial setting) 0 0 0 0 note: * valid in external extended mode (expe = 1) (4) pf4/a20 the pin function is switched as shown below according to the combination of operating mode, the expe bit, port function control register (pfcr), and the pf4ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a20_oe pf4ddr on-chip rom disabled extended mode bus controller a20 output ? ? bus controller a20 output * 1 ? pf4 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf4 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 424 of 1102 rej09b0365-0100 (5) pf3/a19 the pin function is switched as shown below according to the combination of operating mode, the expe bit, port function control register (pfcr), and the pf3ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a19_oe pf3ddr on-chip rom disabled extended mode bus controller a19 output ? ? bus controller a19 output * 1 ? pf3 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf3 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) (6) pf2/a18 the pin function is switched as shown below according to the combination of operating mode, the expe bit, port function control register (pfcr), and the pf2ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a18_oe pf2ddr on-chip rom disabled extended mode bus controller a18 output ? ? bus controller a18 output * 1 ? pf2 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf2 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 425 of 1102 rej09b0365-0100 (7) pf1/a17 the pin function is switched as shown below according to the combination of operating mode, the expe bit, port function control register (pfcr), and the pf1ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a17_oe pf1ddr on-chip rom disabled extended mode bus controller a17 output ? ? bus controller a17 output * 1 ? pf1 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf1 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) (8) pf0/a16 the pin function is switched as shown below according to the combination of operating mode, the expe bit, port function control register (pfcr), and the pf0ddr bit settings. setting i/o port i/o port mcu operating mode module name pin function a16_oe pf0ddr on-chip rom disabled extended mode bus controller a16 output ? ? bus controller a16 output * 1 ? pf0 output 0 1 modes other than on-chip rom disabled extended mode i/o port pf0 input (initial setting) 0 0 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 426 of 1102 rej09b0365-0100 11.2.12 port h (1) ph7/d7, ph6/d6, ph5/d5, ph4/d4, ph3/d3, ph2/d2, ph1/d1, ph0/d0 the pin function is switched as shown below according to the combination of operating mode, the expe bit, and the phnddr bit settings. setting mcu operating mode i/o port module name pin function expe phnddr bus controller data i/o * (initial setting e) 1 ? phn output 0 1 i/o port phn input (initial setting s) 0 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode n: 0 to 7 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 427 of 1102 rej09b0365-0100 11.2.13 port i (1) pi7/d15, pi6/d14, pi5/d13, pi4/d12, pi3/d11, pi2/d10, pi1/d9, pi0/d8 the pin function is switched as shown below according to the combination of operating mode, bus mode, the expe bit, and the pinddr bit settings. setting bus controller i/o port module name pin function 16-bit bus mode pinddr bus controller data i/o * (initial setting e) 1 ? pin output 0 1 i/o port pin input (initial setting s) 0 0 [legend] initial setting e: initial setting in external extended mode initial setting s: initial setting in single-chip mode n: 0 to 7 note: * valid in external extended mode (expe = 1) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 428 of 1102 rej09b0365-0100 11.2.14 port j the pin function of port j can be switched with that of port d according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port j can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for detail, see section 11.3.11, port function control register d (pfcrd). (1) pj7/tioca8/tiocb8/tclkh/po23 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and pj7ddr bit settings. setting ppg tpu i/o port module name pin function po23_oe tiocb8_oe pd7ddr ppg po23 output * 1 ? ? tpu tiocb8 output * 0 1 ? pj7 output * 0 0 1 i/o port pj7 input * 0 0 0 note: * valid when pcjke = 1 (2) pj6/tioca8/po22 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj6ddr bit settings. setting ppg tpu i/o port module name pin function po22_oe tioca8_oe pj6ddr ppg po22 output * 1 ? ? tpu tioca8 output * 0 1 ? pj6 output * 0 0 1 i/o port pj6 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 429 of 1102 rej09b0365-0100 (3) pj5/tioca7/tiocb7/tclkg/po21 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj5ddr bit settings. setting ppg tpu i/o port module name pin function po21_oe tiocb7_oe pj5ddr ppg po21 output * 1 ? ? tpu tiocb7 output * 0 1 ? pj5 output * 0 0 1 i/o port pj5 input * 0 0 0 note: * valid when pcjke = 1 (4) pj4/tioca7/po20 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj4ddr bit settings. setting ppg tpu i/o port module name pin function po20_oe tioca7_oe pj4ddr ppg po20 output * 1 ? ? tpu tioca7 output * 0 1 ? pj4 output * 0 0 1 i/o port pj4 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 430 of 1102 rej09b0365-0100 (5) pj3/po19/tiocc6/tiocd6/tclkf the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj3ddr bit settings. setting ppg tpu i/o port module name pin function po19_oe tiocd6_oe pj3ddr ppg po19 output * 1 ? ? tpu tiocd6 output * 0 1 ? pj3 output * 0 0 1 i/o port pj3 input * 0 0 0 note: * valid when pcjke = 1 (6) pj2/po18/tiocc6/tclke the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj2ddr bit settings. setting ppg tpu i/o port module name pin function po18_oe tiocc6_oe pj2ddr ppg po18 output * 1 ? ? tpu tiocc6 output * 0 1 ? pj2 output * 0 0 1 i/o port pj2 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 431 of 1102 rej09b0365-0100 (7) pj1/po17/tioca6/tiocb6 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj1ddr bit settings. setting ppg tpu i/o port module name pin function po17_oe tiocb6_oe pj1ddr ppg po17 output * 1 ? ? tpu tiocb6 output * 0 1 ? pj1 output * 0 0 1 i/o port pj1 input * 0 0 0 note: * valid when pcjke = 1 (8) pj0/po16/tioca6 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pj0ddr bit settings. setting ppg tpu i/o port module name pin function po16_oe tioca6_oe pj0ddr ppg po16 output * 1 ? ? tpu tioca6 output * 0 1 ? pj0 output * 0 0 1 i/o port pj0 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 432 of 1102 rej09b0365-0100 11.2.15 port k the pin function of port k can be switched with that of port e according to the combination of operating mode, the expe bit, and the pcjke bit settings. the pin function of port k can be switched according to the pcjke bit setting in the single-chip mode (expe = 0). however, do not change the setting of the pcjke bit in external extended mode. for detail, see section 11.3.11, port function control register d (pfcrd). (1) pk7/po31/tioca11/tiocb11 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk7ddr bit settings. setting ppg tpu i/o port module name pin function po31_oe tiocb11_oe pk7ddr ppg po31 output * 1 ? ? tpu tiocb11 output * 0 1 ? pk7 output * 0 0 1 i/o port pk7 input * 0 0 0 note: * valid when pcjke = 1 (2) pk6/po30/tioca11 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk6ddr bit settings. setting ppg tpu i/o port module name pin function po30_oe tioca11_oe pk6ddr ppg po30 output * 1 ? ? tpu tioca11 output * 0 1 ? pk6 output * 0 0 1 i/o port pk6 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 433 of 1102 rej09b0365-0100 (3) pk5/po29/tioca10/tiocb10 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk5ddr bit settings. setting ppg tpu i/o port module name pin function po29_oe tiocb10_oe pk5ddr ppg po29 output * 1 ? ? tpu tiocb10 output * 0 1 ? pk5 output * 0 0 1 i/o port pk5 input * 0 0 0 note: * valid when pcjke = 1 (4) pk4/po28/tioca10 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk4ddr bit settings. setting ppg tpu i/o port module name pin function po28_oe tioca10_oe pk4ddr ppg po28 output * 1 ? ? tpu tioca10 output * 0 1 ? pk4 output * 0 0 1 i/o port pk4 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 434 of 1102 rej09b0365-0100 (5) pk3/po27/tiocc9/tiocd9 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk3ddr bit settings. setting ppg tpu i/o port module name pin function po27_oe tiocd9_oe pk3ddr ppg po27 output * 1 ? ? tpu tiocd9 output * 0 1 ? pk3 output * 0 0 1 i/o port pk3 input * 0 0 0 note: * valid when pcjke = 1 (6) pk2/po26/tiocc9 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk2ddr bit settings. setting ppg tpu i/o port module name pin function po26_oe tiocc9_oe pk2ddr ppg po26 output * 1 ? ? tpu tiocc9 output * 0 1 ? pk2 output * 0 0 1 i/o port pk2 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 435 of 1102 rej09b0365-0100 (7) pk1/po25/tioca9/tiocb9 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk1ddr bit settings. setting ppg tpu i/o port module name pin function po25_oe tiocb9_oe pk1ddr ppg po25 output * 1 ? ? tpu tiocb9 output * 0 1 ? pk1 output * 0 0 1 i/o port pk1 input * 0 0 0 note: * valid when pcjke = 1 (8) pk0/po24/tioca9 the pin function is switched as shown below according to the combination of the ppg register, tpu register, port function control register (pfcr), and the pk0ddr bit settings. setting ppg tpu i/o port module name pin function po24_oe tioca9_oe pk0ddr ppg po24 output * 1 ? ? tpu tioca9 output * 0 1 ? pk0 output * 0 0 1 i/o port pk0 input * 0 0 0 note: * valid when pcjke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 436 of 1102 rej09b0365-0100 11.2.16 port n (1) pn3/scl3 the pin function is switched as shown below according to the combination of the iic2 register setting and the pn3ddr bit setting. setting iic2 i/o port module name pin function scl3_oe pn3ddr iic2 scl3 i/o 1 ? pn3 output (open-drain output) 0 1 i/o port pn3 input (initial setting) 0 0 (2) pn2/sda3 the pin function is switched as shown below according to the combination of the iic2 register setting and the pn2ddr bit setting. setting iic2 i/o port module name pin function sda3_oe pn2ddr iic2 sda3 i/o 1 ? pn2 output (open-drain output) 0 1 i/o port pn2 input (initial setting) 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 437 of 1102 rej09b0365-0100 (3) pn1/scl2 the pin function is switched as shown below according to the combination of the iic2 register setting and the pn1ddr bit setting. setting iic2 i/o port module name pin function scl2_oe pn1ddr iic2 scl2 i/o 1 ? pn1 output (open-drain output) 0 1 i/o port pn1 input (initial setting) 0 0 (4) pn0/sda2 the pin function is switched as shown below according to the combination of the iic2 register setting and the pn0ddr bit setting. setting iic2 i/o port module name pin function sda2_oe pn0ddr iic2 sda2 i/o 1 ? pn0 output (open drain output) 0 1 i/o port pn0 input (initial setting) 0 0 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 438 of 1102 rej09b0365-0100 table 11.5 available output sign als and settings in each port port output specification signal name output signal name signal selection register settings peripheral module settings p1 7 scl0_oe scl0 iccra.ice = 1 6 dack1a _oe dack1 pfcr7.dmas1[a,b] = 00 dacr.ams = 1, dmdr.dacke = 1 sck3_oe sck3 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke[1,0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke[1,0] = 01 or while smr.c/a = 1, scr.cke1 = 0 sda0_oe sda0 iccra.ice = 1 5 tend1a _oe tend1 pfcr7.dmas1[a,b] = 00 dmdr.tende = 1 scl1_oe scl1 iccra.ice = 1 4 txd3_oe txd3 scr.te = 1 sda1_oe sda1 iccra.ice = 1 3 ? ? ? ? 2 dack0a _oe dack0 pfcr7.dmas0[a,b] = 00 dacr.ams = 1, dmdr.dacke = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 439 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings p1 2 sck2_oe sck2 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke[1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke[1, 0] = 01 or while smr.c/a = 1, scr.cke1 = 0 1 tend0a _oe tend0 pfcr7.dmas0[a,b] = 00 dmdr.tende = 1 0 txd2_oe txd2 scr.te = 1 p2 7 tiocb5_oe tiocb5 tpu.tior5.iob3 = 0, tpu.tior5.iob[1,0] = 01/10/11 po7_oe po7 nderl.nder7 = 1 6 tioca5_oe tioca5 tpu.tior5.ioa3 = 0, tpu.tior5.ioa[1,0] = 01/10/11 tmo1_oe tmo1 tcsr.os3,2 = 01/10/11 or tcsr.os[1,0] = 01/10/11 txd1_oe txd1 scr.te = 1 po6_oe po6 nderl.nder6 = 1 5 tioca4_oe tioca4 tpu.tior4.ioa3 = 0, tpu.tior4.ioa[1,0] = 01/10/11 po5_oe po5 nderl.nder5 = 1 4 tiocb4_oe tiocb4 tpu.tior4.iob3 = 0, tpu.tior4.iob[1,0] = 01/10/11 sck1_oe sck1 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1, 0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 po4_oe po4 nderl.nder4 = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 440 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings p2 3 tiocd3_oe tiocd3 tpu.tmdr.bfb = 0, tpu.tiorl3.iod3 = 0, tpu.tiorl3.iod[1,0] = 01/10/11 po3_oe po3 nderl.nder3 = 1 2 tiocc3_oe tiocc3 tpu.tmdr.bfa = 0, tpu.tiorl3.ioc3 = 0, tpu.tiorl3.iod[1,0] = 01/10/11 tmo0_oe tmo0 tcsr.os[3,2] = 01/10/11 or tcsr.os[1,0] = 01/10/11 txd0_oe txd0 scr.te = 1 po2_oe po2 nderl.nder2 = 1 1 tioca3_oe tioca3 tpu.tiorh3.ioa3 = 0, tpu.tiorh3.ioa[1,0] = 01/10/11 po1_oe po1 nderl.nder1 = 1 0 tiocb3_oe tiocb3 tpu.tiorh3.iob3 = 0, tpu.tiorh3.iob[1,0] = 01/10/11 sck0_oe sck0 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1, 0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1, 0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 po0_oe po0 nderl.nder0 = 1 p3 7 tiocb2_oe tiocb2 tpu.tior2.iob3 = 0, tpu.tior2.iob[1,0] = 01/10/11 po15_oe po15 nderh.nder15 = 1 6 tioca2_oe tioca2 tpu.tior2.ioa3 = 0, tpu.tior2.ioa[1,0] = 01/10/11 po14_oe po14 nderh.nder14 = 1 5 dack1b _oe dack1 pfcr7.dmas1[a,b] = 01 dacr.ams = 1,dmdr.dacke = 1 tiocb1_oe tiocb1 tpu.tior1.iob3 = 0, tpu.tior1.iob[1,0] = 01/10/11 po13_oe po13 nderh.nder13 = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 441 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings p3 4 tend1b _oe tend1 pfcr7.dmas1[a,b] = 01 dmdr.tende = 1 tioca1_oe tioca1 tpu.tior1.ioa3 = 0, tpu.tior1.ioa[1,0] = 01/10/11 po12_oe po12 nderh.nder12 = 1 3 tiocd0_oe tiocd0 tpu.tmdr.bfb = 0, tpu.tiorl0.iod3 = 0, tpu.tiorl0.iod[1,0] = 01/10/11 po11_oe po11 nderh.nder11 = 1 2 dack0b _oe dack0 pfcr7.dmas0[a,b] = 01 dacr.ams = 1,dmdr.dacke = 1 tiocc0_oe tiocc0 tpu.tmdr.bfa = 0, tpu.tiorl0.ioc3 = 0, tpu.tiorl0.iod[1,0] = 01/10/11 po10_oe po10 nderh.nder10 = 1 1 tend0b _oe tend0 pfcr7.dmas0[a,b] = 01 dmdr.tende = 1 tiocb0_oe tiocb0 tpu.tiorh0.iob3 = 0, tpu.tiorh0.iob[1,0] = 01/10/11 po9_oe po9 nderh.nder9 = 1 0 tioca0_oe tioca0 tpu.tiorh0.ioa3 = 0, tpu.tioh0.ioa[1,0] = 01/10/11 po8_oe po8 nderh.nder8 = 1 p6 5 dack3 _oe dack3 pfcr7.dmas3[a,b] = 01 dacr.ams = 1, dmdr.dacke = 1 tmo3_oe tmo3 tcsr.os[3,2] = 01/10/11 or tcsr.os[1,0] = 01/10/11 sck6_oe sck6 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke[1,0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke[1,0] = 01 or while smr.c/a = 1, scr.cke1 = 0 4 tend3 _oe tend3 pfcr7.dmas3[a,b] = 01 dmdr.tende = 1 3 txd6_oe txd6 scr.te = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 442 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings p6 2 dack2 _oe dack2 pfcr7.dmas2[a,b] = 01 dacr.ams = 1, dmdr.dacke = 1 tmo2_oe tmo2 tcsr.os[3,2] = 01/10/11 or tcsr.os[1,0] = 01/10/11 sck4_oe sck4 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke [1,0] = 01 or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke [1,0] = 01 or while smr.c/a = 1, scr.cke 1 = 0 1 tend2 _oe tend2 pfcr7.dmas2[a,b] = 01 dmdr.tende = 1 0 txd4_oe txd4 scr.te = 1 pa 7 b _oe b paddr.pa7ddr = 1, sckcr.pstop1 = 0 6 ah _oe ah syscr.expe = 1, mpxcr.mpxen (n = 7 to 3) = 1 bsb _oe bs pfcr2.bss = 1 syscr.expe = 1, pfcr2.bse = 1 as _oe as syscr.expe = 1, pfcr2.asoe = 1 5 rd _oe rd syscr.expe = 1 4 lub _oe lub syscr.expe = 1, pfcr6.lhwroe = 1 or sramcr.bcseln = 1 lhwr _oe lhwr syscr.expe = 1, pfcr6.lhwroe = 1 3 llb _oe llb syscr.expe = 1, sramcr.bcseln = 1 llwr _oe llwr syscr.expe = 1 1 back _oe back syscr.expe = 1,bcr1.brle = 1 (rd/ wr )_oe rd/ wr syscr.expe = 1, pfcr2.rdwre = 1 or sramcr.bcseln = 1 0 bsa _oe bs pfcr2.bss = 0 syscr.expe = 1, pfcr2.bse = 1 breqo _oe breqo syscr.expe = 1, bcr1.brle = 1, bcr1.breqoe = 1 pb 7 cs7d _oe cs7 pfcr1.cs7s[a,b] = 11 syscr.expe = 1, pfcr.cs7e = 1 6 (rd/ wr )- b_oe rd/ wr pfcr2.rdwrs = 1 syscr.expe = 1, pfcr2.rewre = 1, or sramcr.bcseln = 1 cs6d _oe cs6 pfcr1.cs6s[a,b] = 11 syscr.expe = 1, pfcr0.cs6e = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 443 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings pb 5 cs5d _oe cs5 pfcr1.cs5s[a,b] = 11 syscr.expe = 1, pfcr0.cs5e = 1 4 cs4b _oe cs4 pfcr1.cs4s[a,b] = 01 syscr.expe = 1, pfcr0.cs4e = 1 3 cs3a _oe cs3 pfcr2.cs3s = 0 syscr.expe = 1, pfcr0.cs3e = 1 cs7a _oe cs7 pfcr1.cs7s[a,b] = 00 syscr.expe = 1, pfcr0.cs7e = 1 2 cs2a _oe cs2 pfcr2.cs2s = 0 syscr.expe = 1, pfcr0.cs2e = 1 cs6a _oe cs6 pfcr1.cs6s[a,b] = 00 syscr.expe = 1, pfcr0.cs6e = 1 1 cs1 _oe cs1 syscr.expe = 1, pfcr0.cs1e = 1 cs2b _oe cs2 pfcr2.cs2s = 1 syscr.expe = 1, pfcr0.cs2e = 1 cs5a _oe cs5 pfcr1.cs5s[a,b] = 00 syscr.expe = 1, pfcr0.cs5e = 1 cs6b _oe cs6 pfcr1.cs6s[a,b] = 01 syscr.expe = 1, pfcr0.cs6e = 1 cs7b _oe cs7 pfcr1.cs7s[a,b] = 01 syscr.expe = 1, pfcr0.cs7e = 1 0 cs0 _oe cs0 syscr.expe = 1, pfcr0.cs0e = 1 cs4a _oe cs4 pfcr1.cs4s[a,b] = 00 syscr.expe = 1, pfcr0.cs4e = 1 cs5b _oe cs5 pfcr1.cs5s[a,b] = 01 syscr.expe = 1, pfcr0.cs5e = 1 pc 1 cs4c _oe cs4 pfcr1.cs4s[a,b] = 10 syscr.expe = 1, pfcr0.cs4e = 1 cs5c _oe cs5 pfcr1.cs5s[a,b] = 10 syscr.expe = 1, pfcr0.cs5e = 1 cs6c _oe cs6 pfcr1.cs6s[a,b] = 10 syscr.expe = 1, pfcr0.cs6e = 1 cs7c _oe cs7 pfcr1.cs7s[a,b] = 10 syscr.expe = 1, pfcr0.cs7e = 1 0 cs3b _oe cs3 pfcr2.cs3s = 1 syscr.expe = 1, pfcr0.cs3e = 1 pd 7 a7_oe a7 syscr.expe = 1, pdddr.pd7ddr = 1 6 a6_oe a6 syscr.expe = 1, pdddr.pd6ddr = 1 5 a5_oe a5 syscr.expe = 1, pdddr.pd5ddr = 1 4 a4_oe a4 syscr.expe = 1, pdddr.pd4ddr = 1 3 a3_oe a3 syscr.expe = 1, pdddr.pd3ddr = 1 2 a2_oe a2 syscr.expe = 1, pdddr.pd2ddr = 1 1 a1_oe a1 syscr.expe = 1, pdddr.pd1ddr = 1 0 a0_oe a0 syscr.expe = 1, pdddr.pd0ddr = 1 pe 7 a15_oe a15 syscr.expe = 1, pdddr.pe7ddr = 1 6 a14_oe a14 syscr.expe = 1, pdddr.pe6ddr = 1 5 a13_oe a13 syscr.expe = 1, pdddr.pe5ddr = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 444 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings pe 4 a12_oe a12 syscr.expe = 1, pdddr.pe4ddr = 1 3 a11_oe a11 syscr.expe = 1, pdddr.pe3ddr = 1 2 a10_oe a10 syscr.expe = 1, pdddr.pe2ddr = 1 1 a9_oe a9 syscr.expe = 1, pdddr.pe1ddr = 1 0 a8_oe a8 syscr.expe = 1, pdddr.pe0ddr = 1 pf 7 a23a_oe a23 pfcr5.a23s = 0 syscr.expe = 1, pfcr4.a23e = 1 sck5_oe sck5 when scmr.smif = 1: scr.te = 1 or scr.re = 1 while smr.gm = 0, scr.cke[1,0] = 01or while smr.gm = 1 when scmr.smif = 0: scr.te = 1 or scr.re = 1 while smr.c/a = 0, scr.cke[1,0] = 01 or while smr.c/a = 1, scr.cke1 = 0 6 a22a_oe a22 pfcr5.a22s = 0 syscr.expe = 1, pfcr4.a22e = 1 5 a21a_oe a21 pfcr5.a21s = 0 syscr.expe = 1, pfcr4.a21e = 1 txd5_oe txd5 scr.te = 1 irtxd_oe irtxd scr.te = 1, ircr.ire = 1 4 a20_oe a20 syscr.expe = 1, pfcr4.a20e = 1 3 a19_oe a19 syscr.expe = 1, pfcr4.a19e = 1 2 a18_oe a18 syscr.expe = 1, pfcr4.a18e = 1 1 a17_oe a17 syscr.expe = 1, pfcr4.a17e = 1 0 a16_oe a16 syscr.expe = 1, pfcr4.a16e = 1 ph 7 d7_e d7 syscr.expe = 1 6 d6_e d6 syscr.expe = 1 5 d5_e d5 syscr.expe = 1 4 d4_e d4 syscr.expe = 1 3 d3_e d3 syscr.expe = 1 2 d2_e d2 syscr.expe = 1 1 d1_e d1 syscr.expe = 1 0 d0_e d0 syscr.expe = 1 pi 7 d15_e d15 syscr.expe = 1, abwcr.abw[h,l]n = 01 6 d14_e d14 syscr.expe = 1, abwcr.abw[h,l]n = 01 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 445 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings pi 5 d13_e d13 syscr.expe = 1, abwcr.abw[h,l]n = 01 4 d12_e d12 syscr.expe = 1, abwcr.abw[h,l]n = 01 3 d11_e d11 syscr.expe = 1, abwcr.abw[h,l]n = 01 2 d10_e d10 syscr.expe = 1, abwcr.abw[h,l]n = 01 1 d9_e d9 syscr.expe = 1, abwcr.abw[h,l]n = 01 0 d8_e d8 syscr.expe = 1, abwcr.abw[h,l]n = 01 pj 7 tiocb8_oe tiocb8 tpu.tior_8.iob3 = 0, tpu.tior_8.iob[1,0] = 01/10/11 po23_oe po23 nderl_1.nder23 = 1 tioca8_oe tioca8 tpu.tior_8.ioa3 = 0, tpu.tior_8.ioa[1,0] = 01/10/11 6 po22_oe po22 nderl_1.nder22 = 1 tiocb7_oe tiocb7 tpu.tior_7.iob3 = 0, tpu.tior_7.iob[1,0] = 01/10/11 5 po21_oe po21 nderl_1.nder21 = 1 tioca7_oe tioca7 tpu.tior_7.ioa3 = 0, tpu.tior_7.ioa[1,0] = 01/10/11 4 po20_oe po20 nderl_1.nder20 = 1 tiocd6_oe tiocd6 tpu.tmdr_6.bfb = 0, tpu.tiorl_6.iod3 = 0, tpu.tiorl_6.iod[1,0] = 01/10/11 3 po19_oe po19 nderl_1.nder19 = 1 tiocc6_oe tiocc6 tpu.tmdr_6.bfa = 0, tpu.tiorl_6.ioc3 = 0, tpu.tiorl_6.ioc[1,0] = 01/10/11 2 po18_oe po18 nderl_1.nder18 = 1 tiocb6_oe tiocb6 tpu.tiorh_6.iob3 = 0, tpu.tiorh_6.iob[1,0] = 01/10/11 1 po17_oe po17 nderl_1.nder17 = 1 tioca6_oe tioca6 tpu.tiorh_6.ioa3 = 0, tpu.tiorh_6.ioa[1,0] = 01/10/11 0 po16_oe po16 nderl_1.nder16 = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 446 of 1102 rej09b0365-0100 port output specification signal name output signal name signal selection register settings peripheral module settings pk tiocb11_oe tiocb11 tpu.tior_11.iob3 = 0, tpu.tior_11.iob[1,0] = 01/10/11 7 po31_oe po31 nderh_1.nder31 = 1 tioca11_oe tioca11 tpu.tior_11.ioa3 = 0, tpu.tior_11.ioa[1,0] = 01/10/11 6 po30_oe po30 nderh_1.nder30 = 1 tiocb10_oe tiocb10 tpu.tior_10.iob3 = 0, tpu.tior_10.iob[1,0] = 01/10/11 5 po29_oe po29 nderh_1.nder29 = 1 tioca10_oe tioca10 tpu.tior_10.ioa3 = 0, tpu.tior_10.ioa[1,0] = 01/10/11 4 po28_oe po28 nderh_1.nder28 = 1 tiocd9_oe tiocd9 tpu.tmdr_9.bfb = 0, tpu.tiorl_9.iod3 = 0, tpu.tiorl_9.iod[1,0] = 01/10/11 3 po27_oe po27 nderh_1.nder27 = 1 tiocc9_oe tiocc9 tpu.tmdr_9.bfa = 0, tpu.tiorl_9.ioc3 = 0, tpu.tiorl_9.ioc[1,0] = 01/10/11 2 po26_oe po26 nderh_1.nder26 = 1 tiocb9_oe tiocb9 tpu.tiorh_9.iob3 = 0, tpu.tiorh_9.iob[1,0] = 01/10/11 1 po25_oe po25 nderh_1.nder25 = 1 tioca9_oe tioca9 tpu.tiorh_9.ioa3 = 0, tpu.tiorh_9.ioa[1,0] = 01/10/11 0 po24_oe po24 nderh_1.nder24 = 1 pn 3 scl3_oe scl2 iccra.ice = 1 2 sda3_oe sda3 iccra.ice = 1 1 scl2_oe scl2 iccra.ice = 1 0 sda2_oe sda2 iccra.ice = 1 section 11 i/o ports rev. 1.00 sep. 13, 2007 page 447 of 1102 rej09b0365-0100 11.3 port function controller the port function controller controls the i/o ports. the port function controller incorp orates the following registers. ? port function control register 0 (pfcr0) ? port function control register 1 (pfcr1) ? port function control register 2 (pfcr2) ? port function control register 4 (pfcr4) ? port function control register 6 (pfcr6) ? port function control register 7 (pfcr7) ? port function control register 9 (pfcr9) ? port function control register a (pfcra) ? port function control register b (pfcrb) ? port function control register c (pfcrc) ? port function control register d (pfcrd) section 11 i/o ports rev. 1.00 sep. 13, 2007 page 448 of 1102 rej09b0365-0100 11.3.1 port function co ntrol register 0 (pfcr0) pfcr0 enables/disables the cs output. bit bit name initial value r/w note: * 1 in external extended mode; 0 in other modes. 7 cs7e 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 0 r/w 3 cs3e 0 r/w 2 cs2e 0 r/w 1 cs1e 0 r/w 0 cs0e undefined * r/w bit bit name initial value r/w description 7 cs7e 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 0 r/w 3 cs3e 0 r/w 2 cs2e 0 r/w 1 cs1e 0 r/w 0 cs0e undefined * r/w cs7 to cs0 enable these bits enable/disable the corresponding csn output. 0: pin functions as i/o port 1: pin functions as csn output pin (n = 7 to 0) note: * 1 in external extended mode, 0 in other modes. 11.3.2 port function co ntrol register 1 (pfcr1) pfcr1 selects the cs output pins. bit bit name initial value r/w 7 cs7sa 0 r/w 6 cs7sb 0 r/w 5 cs6sa 0 r/w 4 cs6sb 0 r/w 3 cs5sa 0 r/w 2 cs5sb 0 r/w 1 cs4sa 0 r/w 0 cs4sb 0 r/w section 11 i/o ports rev. 1.00 sep. 13, 2007 page 449 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 6 cs7sa * cs7sb * 0 0 r/w r/w cs7 output pin select selects the output pin for cs7 when cs7 output is enabled (cs7e = 1) 00: specifies pin pb3 as cs7 -a output 01: specifies pin pb1 as cs7 -b output 10: specifies pin pc1 as cs7 -c output 11: specifies pin pb7 as cs7 -d output 5 4 cs6sa * cs6sb * 0 0 r/w r/w cs6 output pin select selects the output pin for cs6 when cs6 output is enabled (cs6e = 1) 00: specifies pin pb2 as cs6 -a output 01: specifies pin pb1 as cs6 -b output 10: specifies pin pc1 as cs6 -c output 11: specifies pin pb6 as cs6 -d output 3 2 cs5sa * cs5sb * 0 0 r/w r/w cs5 output pin select selects the output pin for cs5 when cs5 output is enabled (cs5e = 1) 00: specifies pin pb1 as cs5 -a output 01: specifies pin pb0 as cs5 -b output 10: specifies pin pc1 as cs5 -c output 11: specifies pin pb5 as cs5 -d output 1 0 cs4sa * cs4sb * 0 0 r/w r/w cs4 output pin select selects the output pin for cs4 when cs4 output is enabled (cs4e = 1) 00: specifies pin pb0 as cs4 -a output 01: specifies pin pb4 as cs4 -b output 10: specifies pin pc1 as cs4 -c output 11: setting prohibited note: * if multiple cs outputs are specified to a single pin according to the csn output pin select bits (n = 4 to 7), multiple cs signals are output from the pin. for details, see section 8.5.3, chip select signals. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 450 of 1102 rej09b0365-0100 11.3.3 port function co ntrol register 2 (pfcr2) pfcr2 selects the cs output pin, enables/disables bus control i/o, and selects the bus control i/o pins. bit bit name initial value r/w 7 cs3s 0 r/w 6 cs2s 0 r/w 5 bss 0 r/w 4 bse 0 r/w 3 rdwrs 0 r/w 2 rdwre 0 r/w 1 asoe 1 r/w 0 waits 0 r/w bit bit name initial value r/w description 7 cs3s * 1 0 r/w cs3 output pin select selects the output pin for cs3 when cs3 output is enabled (cs3e = 1) 0: specifies pin pb3 as cs3 -a output pin 1: specifies pin pb0 as cs3 -b output pin 6 cs2s * 1 0 r/w cs2 output pin select selects the output pin for cs2 when cs2 output is enabled (cs2e = 1) 0: specifies pin pb2 as cs2 -a output pin 1: specifies pin pb1 as cs2 -b output pin 5 bss 0 r/w bs output pin select selects the bs output pin 0: specifies pin pa0 as bs -a output pin 1: specifies pin pa6 as bs -b output pin 4 bse 0 r/w bs output enable enables/disables the bs output 0: disables the bs output 1: enables the bs output 3 rdwrs * 2 0 r/w rd/ wr output pin select selects the output pin for rd/ wr 0: specifies pin pa1 as rd/ wr -a output pin 1: specifies pin pb6 as rd/ wr -b output pin section 11 i/o ports rev. 1.00 sep. 13, 2007 page 451 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 rdwre * 2 0 r/w rd/ wr output enable enables/disables the rd/ wr output 0: disables the rd/ wr output 1: enables the rd/ wr output 1 asoe 1 r/w as output enable enables/disables the as output 0: specifies pin pa6 as i/o port 1: specifies pin pa6 as as output pin 0 waits 0 r/w wait input pin select selects the input pin for the wait request signal when accessing external spaces. 0: specifies pin pa2 as wait-a input pin 1: specifies pin pc0 as wait-b input pin notes: 1. if multiple cs outputs are specified to a single pin according to the csn output pin select bit (n = 2, 3), multiple cs signals are output from the pin. for details, see section 8.5.3, chip select signals. 2. if an area is specified as a byte cont rol sdram space, the pin functions as rd/ wr output regardless of the rdwre bit value. 11.3.4 port function co ntrol register 4 (pfcr4) pfcr4 enables or disables the address output. bit bit name initial value r/w 7 a23e 0 r/w 6 a22e 0 r/w 5 a21e 0 r/w 4 a20e 0/1 * r/w 3 a19e 0/1 * r/w 2 a18e 0/1 * r/w 1 a17e 0/1 * r/w 0 a16e 0/1 * r/w bit bit name initial value r/w description 7 a23e 0 r/w address a23 enable enables/disables t he address output (a23) 0: disables the a23 output 1: enables the a23 output section 11 i/o ports rev. 1.00 sep. 13, 2007 page 452 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 a22e 0 r/w address a22 enable enables/disables t he address output (a22) 0: disables the a22 output 1: enables the a22 output 5 a21e 0 r/w address a21 enable enables/disables t he address output (a21) 0: disables the a21 output 1: enables the a21 output 4 a20e 0/1 * r/w address a20 enable enables/disables t he address output (a20) 0: disables the a20 output 1: enables the a20 output 3 a19e 0/1 * r/w address a19 enable enables/disables t he address output (a19) 0: disables the a19 output 1: enables the a19 output 2 a18e 0/1 * r/w address a18 enable enables/disables t he address output (a18) 0: disables the a18 output 1: enables the a18 output 1 a17e 0/1 * r/w address a17 enable enables/disables t he address output (a17) 0: disables the a17 output 1: enables the a17 output 0 a16e 0/1 * r/w address a16 enable enables/disables t he address output (a16) 0: disables the a16 output 1: enables the a16 output note: * the initial value changes depending on the operating mode. the initial value is 1 when the on-chip ro m is disabled, and 0 when the on-chip rom is enabled. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 453 of 1102 rej09b0365-0100 11.3.5 port function co ntrol register 6 (pfcr6) pfcr6 selects the tpu clock input pin. bit bit name initial value r/w 7 ? 1 r/w 6 lhwroe 1 r/w 5 ? 1 r/w 4 ? 0 r 3 tclks 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 adtrg0s 0 r/w bit bit name initial value r/w description 7 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 6 lhwroe 1 r/w lhwr output enable enables/disables lhwr output (valid in external extended mode). 0: specifies pin pa4 as i/o port 1: specifies pin pa4 as lhwr output pin 5 ? 1 r/w reserved this bit is always read as 1. the write value should always be 1. 4 ? 0 r reserved this is a read-only bit and cannot be modified. 3 tclks 0 r/w tpu external clock input pin select selects the tpu external clock input pins. 0: specifies pins p32, p33, p35, and p37 as external clock input pins. 1: specifies pins p14 to p17 as external clock input pins. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 454 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2, 1 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 0 adtrg0s 0 r/w adtrg0s input pin select selects the external trigger input pins of the a/d converter. 0: specifies pin p13 as adtrg0 -a input pin. 1: specifies pin pb6 as adtrg0 -b input pin. 11.3.6 port function co ntrol register 7 (pfcr7) pfcr7 selects the dmac i/o pins ( dreq , dack , and tend ). bit bit name initial value r/w 7 dmas3a 0 r/w 6 dmas3b 0 r/w 5 dmas2a 0 r/w 4 dmas2b 0 r/w 3 dmas1a 0 r/w 2 dmas1b 0 r/w 1 dmas0a 0 r/w 0 dmas0b 0 r/w section 11 i/o ports rev. 1.00 sep. 13, 2007 page 455 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 6 dmas3a dmas3b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_3. 00: setting prohibited 01: specifies pins p63 to p65 as dmac control pins 10: setting prohibited 11: setting prohibited 5 4 dmas2a dmas2b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_2. 00: setting prohibited 01: specifies pins p60 to p62 as dmac control pins 10: setting prohibited 11: setting prohibited 3 2 dmas1a dmas1b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_1. 00: specifies pins p14 to p16 as dmac control pins 01: specifies pins p33 to p35 as dmac control pins 10: setting prohibited 11: setting prohibited 1 0 dmas0a dmas0b 0 0 r/w r/w dmac control pin select selects the i/o port to control dmac_0. 00: specifies pins p10 to p12 as dmac control pins 01: specifies pins p30 to p32 as dmac control pins 10: setting prohibited 11: setting prohibited section 11 i/o ports rev. 1.00 sep. 13, 2007 page 456 of 1102 rej09b0365-0100 11.3.7 port function co ntrol register 9 (pfcr9) pfcr9 selects the multiple functions for the tpu i/o pins. bit bit name initial value r/w 7 tpums5 0 r/w 6 tpums4 0 r/w 5 tpums3a 0 r/w 4 tpums3b 0 r/w 3 tpums2 0 r/w 2 tpums1 0 r/w 1 tpums0a 0 r/w 0 tpums0b 0 r/w bit bit name initial value r/w description 7 tpums5 0 r/w tpu i/o pin multiplex function select selects tioca5 function 0: specifies pin p26 as output compare output and input capture 1: specifies p27 as input capture input and p26 as output compare 6 tpums4 0 r/w tpu i/o pin multiplex function select selects tioca4 function 0: specifies p25 as output compare output and input capture 1: specifies p24 as input capture input and p25 as output compare 5 tpums3a 0 r/w tpu i/o pin multiplex function select selects tioca3 function 0: specifies p21 as output compare output and input capture 1: specifies p20 as input capture input and p21 as output compare 4 tpums3b 0 r/w tpu i/o pin multiplex function select selects tiocc3 function 0: specifies p22 as output compare output and input capture 1: specifies p23 as input capture input and p22 as output compare section 11 i/o ports rev. 1.00 sep. 13, 2007 page 457 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 tpums2 0 r/w tpu i/o pin multiplex function select selects tioca2 function 0: specifies p36 as output compare output and input capture 1: specifies p37 as input capture input and p36 as output compare 2 tpums1 0 r/w tpu i/o pin multiplex function select selects tioca1 function 0: specifies p34 as output compare output and input capture 1: specifies p35 as input capture input and p34 as output compare 1 tpums0a 0 r/w tpu i/o pin multiplex function select selects tioca0 function 0: specifies p30 as output compare output and input capture 1: specifies p31 as input capture input and p30 as output compare 0 tpums0b 0 r/w tpu i/o pin multiplex function select selects tiocc0 function 0: specifies p32 as output compare output and input capture 1: specifies p33 as input capture input and p32 as output compare section 11 i/o ports rev. 1.00 sep. 13, 2007 page 458 of 1102 rej09b0365-0100 11.3.8 port function co ntrol register a (pfcra) pfcra selects the multiple functio ns for the tpu (unit 1) i/o pi ns. do not access this register because writing to or reading from the bits in this register is not effective when the pcjke bit in pfcrd is cleared to 0. bit bit name initial value r/w 7 tpums11 0 r/w 6 tpums10 0 r/w 5 tpums9a 0 r/w 4 tpums9b 0 r/w 3 tpums8 0 r/w 2 tpums7 0 r/w 1 tpums6a 0 r/w 0 tpums6b 0 r/w bit bit name initial value r/w description 7 tpums11 0 r/w tpu i/o pin multiplex function select selects tioca11 function 0: specifies pk6 as output compare output and input capture 1: specifies pk7 as input capture input and pk6 as output compare 6 tpums10 0 r/w tpu i/o pin multiplex function select selects tioca10 function 0: specifies pk4 as output compare output and input capture 1: specifies pk5 as input capture input and pk4 as output compare 5 tpums9a 0 r/w tpu i/o pin multiplex function select selects tioca9 function 0: specifies pk0 as output compare output and input capture 1: specifies pk1 as input capture input and pk0 as output compare 4 tpums9b 0 r/w tpu i/o pin multiplex function select selects tiocc9 function 0: specifies pk2 as output compare output and input capture 1: specifies pk3 as input capture input and pk2 as output compare section 11 i/o ports rev. 1.00 sep. 13, 2007 page 459 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 tpums8 0 r/w tpu i/o pin multiplex function select selects tioca8 function 0: specifies pj6 as output compare output and input capture 1: specifies pj7 as input capture input and pj6 as output compare 2 tpums7 0 r/w tpu i/o pin multiplex function select selects tioca7 function 0: specifies pj4 as output compare output and input capture 1: specifies pj5 as input capture input and pj4 as output compare 1 tpums6a 0 r/w tpu i/o pin multiplex function select selects tioca6 function 0: specifies pj0 as output compare output and input capture 1: specifies pj1 as input capture input and pj0 as output compare 0 tpums6b 0 r/w tpu i/o pin multiplex function select selects tiocc6 function 0: specifies pj2 as output compare output and input capture 1: specifies pj3 as input capture input and pj2 as output compare section 11 i/o ports rev. 1.00 sep. 13, 2007 page 460 of 1102 rej09b0365-0100 11.3.9 port function co ntrol register b (pfcrb) pfcrb selects the input pins for irq15 and irq13 to irq8 . bit bit name initial value r/w 7 its15 0 r/w 6 ? 0 r/w 5 its13 0 r/w 4 its12 0 r/w 3 its11 0 r/w 2 its10 0 r/w 1 its9 0 r/w 0 its8 0 r/w bit bit name initial value r/w description 7 its15 0 r/w irq15 pin select selects an input pin for irq15 . 0: selects pin p27 as irq15 -a input 1: selects pin p67 as irq15 -b input 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5 its13 0 r/w irq13 pin select selects an input pin for irq13 . 0: selects pin p25 as irq13 -a input 1: selects pin p65 as irq13 -b input 4 its12 0 r/w irq12 pin select selects an input pin for irq12 . 0: selects pin p24 as irq12 -a input 1: selects pin p64 as irq12 -b input 3 its11 0 r/w irq11 pin select selects an input pin for irq11 . 0: selects pin p23 as irq11 -a input 1: selects pin p63 as irq11 -b input 2 its10 0 r/w irq10 pin select selects an input pin for irq10 . 0: selects pin p22 as irq10 -a input 1: selects pin p62 as irq10 -b input section 11 i/o ports rev. 1.00 sep. 13, 2007 page 461 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 its9 0 r/w irq9 pin select selects an input pin for irq9 . 0: selects pin p21 as irq9 -a input 1: selects pin p61 as irq9 -b input 0 its8 0 r/w irq8 pin select selects an input pin for irq8 . 0: selects pin p20 as irq8 -a input 1: selects pin p60 as irq8 -b input 11.3.10 port function co ntrol register c (pfcrc) pfcrc selects input pins for irq7 to irq0 . bit bit name initial value r/w 7 its7 0 r/w 6 its6 0 r/w 5 its5 0 r/w 4 its4 0 r/w 3 its3 0 r/w 2 its2 0 r/w 1 its1 0 r/w 0 its0 0 r/w bit bit name initial value r/w description 7 its7 0 r/w irq7 pin select selects an input pin for irq7 . 0: selects pin p17 as irq7 -a input 1: selects pin p57 as irq7 -b input 6 its6 0 r/w irq6 pin select selects an input pin for irq6 . 0: selects pin p16 as irq6 -a input 1: selects pin p56 as irq6 -b input 5 its5 0 r/w irq5 pin select selects an input pin for irq5 . 0: selects pin p15 as irq5 -a input 1: selects pin p55 as irq5 -b input section 11 i/o ports rev. 1.00 sep. 13, 2007 page 462 of 1102 rej09b0365-0100 bit bit name initial value r/w description 4 its4 0 r/w irq4 pin select selects an input pin for irq4 . 0: selects pin p14 as irq4 -a input 1: selects pin p54 as irq4 -b input 3 its3 0 r/w irq3 pin select selects an input pin for irq3 . 0: selects pin p13 as irq3 -a input 1: selects pin p53 as irq3 -b input 2 its2 0 r/w irq2 pin select selects an input pin for irq2 . 0: selects pin p12 as irq2 -a input 1: selects pin p52 as irq2 -b input 1 its1 0 r/w irq1 pin select selects an input pin for irq1 . 0: selects pin p11 as irq1 -a input 1: selects pin p51 as irq1 -b input 0 its0 0 r/w irq0 pin select selects an input pin for irq0 . 0: selects pin p10 as irq0 -a input 1: selects pin p50 as irq0 -b input section 11 i/o ports rev. 1.00 sep. 13, 2007 page 463 of 1102 rej09b0365-0100 11.3.11 port function co ntrol register d (pfcrd) pfcrd enables or disables the port j and port k pin functions. bit bit name initial value r/w 7 pcjke 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 pcjke * 0 r/w ports j and k enable enables or disables the port j and k pin functions. 0: ports j and k are disabled. 1: port s j and k are enabled (ports d and e are disabled). 6 to 0 ? 0 r/w reserved these bits are always read as 0 and cannot be modified. the initial value should not be changed. note: * this bit is only effective in single-chip mo de. in other modes, do not change the initial value of this bit. section 11 i/o ports rev. 1.00 sep. 13, 2007 page 464 of 1102 rej09b0365-0100 11.4 usage notes 11.4.1 notes on input buffer control register (icr) setting 1. when the icr setting is changed, the lsi may malfunction due to an edge occurred internally according to the pin state. before changing the i cr setting, fix the pin state high or disable the input function corresponding to the pin by the on-chip peripheral module settings. 2. if an input is enabled by setting icr while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs. care must be taken for each module settings for unused input functions. 3. when a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. to use the pin as an output, disable the input function for the pin by setting icr. 11.4.2 notes on port function control register (pfcr) settings 1. port function controller controls the i/o port. before enabling a port function, select the input/output destination. 2. when changing input pins, this lsi may malfunction due to the internal edge generated by the pin level difference before and after the change. ? to change input pins, the following procedure must be performed. a. disable the input function by the corresponding on-chip peripheral module settings b. select another input pin by pfcr c. enable its input function by the corresponding on-chip peripheral module settings 3. if a pin function has both a select bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin func tion by the enable bit. 4. the value of the pcjke bit must be set during the initial setting immediately after a power-on. set the pcjke bit first and then set other bits in pfcr as required. 5. do not change the value of th e pcjke bit once it has been set. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 465 of 1102 rej09b0365-0100 section 12 16-bit timer pulse unit (tpu) this lsi has two on-chip 16-bit timer pulse units (tpu), unit 0 and unit 1, each comprises six channels. therefore, this ls i includes twelve channels. functions of unit 0 and unit 1 are shown in table 12.1 and table 12.2 respectively. block diagrams of unit 0 and unit 1 are shown in figure 12.1 and figure 12.2 respectively. this section explains unit 0. this explanation is common to unit 1. 12.1 features ? maximum 16-pulse input/output ? selection of eight counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match ? input capture function ? counter clear operation ? synchronous operations: ? multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare match and input capture possible ? simultaneous input/output for registers possible by counter synchronous operation ? maximum of 15-phase pwm output possible by combination with synchronous operation ? buffer operation settable for channels 0 and 3 ? phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? cascaded operation ? fast access via internal 16-bit bus ? 26 interrupt sources ? automatic transfer of register data ? programmable pulse generator (ppg) output trigger can be generated (unit 0 only) ? conversion start trigger for the a/d converter can be generated (unit 0 only) ? module stop state can be set section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 466 of 1102 rej09b0365-0100 table 12.1 tpu (u nit 0) functions item channel 0 channel 1 channe l 2 channel 3 channel 4 channel 5 count clock p /1 p /4 p /16 p /64 tclka tclkb tclkc tclkd p /1 p /4 p /16 p /64 p /256 tclka tclkb p /1 p /4 p /16 p /64 p /1024 tclka tclkb tclkc p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclka p /1 p /4 p /16 p /64 p /1024 tclka tclkc p /1 p /4 p /16 p /64 p /256 tclka tclkc tclkd general registers (tgr) tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 tgra_3 tgrb_3 tgra_4 tgrb_4 tgra_5 tgrb_5 general registers/ buffer registers tgrc_0 tgrd_0 ? ? tgrc_3 tgrd_3 ? ? i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output o o o o o o 1 output o o o o o o compare match output toggle output o o o o o o input capture function o o o o o o synchronous operation o o o o o o pwm mode o o o o o o phase counting mode ? o o ? o o buffer operation o ? ? o ? ? dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 467 of 1102 rej09b0365-0100 item channel 0 channel 1 channe l 2 channel 3 channel 4 channel 5 dmac activation tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture tgra_5 compare match or input capture a/d conversion start trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture tgra_5 compare match or input capture ppg trigger tgra_0/ tgrb_0 compare match or input capture tgra_1/ tgrb_1 compare match or input capture tgra_2/ tgrb_2 compare match or input capture tgra_3/ tgrb_3 compare match or input capture ? ? interrupt sources 5 sources compare match or input capture 0a compare match or input capture 0b compare match or input capture 0c compare match or input capture 0d overflow 4 sources compare match or input capture 1a compare match or input capture 1b overflow underflow 4 sources compare match or input capture 2a compare match or input capture 2b overflow underflow 5 sources compare match or input capture 3a compare match or input capture 3b compare match or input capture 3c compare match or input capture 3d overflow 4 sources compare match or input capture 4a compare match or input capture 4b overflow underflow 4 sources compare match or input capture 5a compare match or input capture 5b overflow underflow [legend] o : possible ? : not possible section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 468 of 1102 rej09b0365-0100 table 12.2 tpu (u nit 1) functions item channel 6 channel 7 channel 8 channel 9 channel 10 channel 11 count clock p /1 p /4 p /16 p /64 tclke tclkf tclkg tclkh p /1 p /4 p /16 p /64 p /256 tclke tclkf p /1 p /4 p /16 p /64 p /1024 tclke tclkf tclkg p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclke p /1 p /4 p /16 p /64 p /1024 tclke tclkg p /1 p /4 p /16 p /64 p /256 tclke tclkg tclkh general registers (tgr) tgra_6 tgrb_6 tgra_7 tgrb_7 tgra_8 tgrb_8 tgra_9 tgrb_9 tgra_10 tgrb_10 tgra_11 tgrb_11 general registers/ buffer registers tgrc_6 tgrd_6 ? ? tgrc_9 tgrd_9 ? ? i/o pins tioca6 tiocb6 tiocc6 tiocd6 tioca7 tiocb6 tioca8 tiocb8 tioca9 tiocb9 tiocc9 tiocd9 tioca10 tiocb10 tioca11 tiocb11 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output o o o o o o 1 output o o o o o o compare match output toggle output o o o o o o input capture function o o o o o o synchronous operation o o o o o o pwm mode o o o o o o phase counting mode ? o o ? o o buffer operation o ? ? o ? ? dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 469 of 1102 rej09b0365-0100 item channel 6 channel 7 channel 8 channel 9 channel 10 channel 11 dmac activation tgra_6 compare match or input capture tgra_7 compare match or input capture tgra_8 compare match or input capture tgra_9 compare match or input capture tgra_10 compare match or input capture tgra_11 compare match or input capture a/d conversion start trigger ? ? ? ? ? ? ppg trigger tgra_6/ tgrb_6 compare match tgra_7/ tgrb_7 compare match tgra_8/ tgrb_8 compare match tgra_9/ tgrb_9 compare match ? ? interrupt sources 5 sources compare match or input capture 6a compare match or input capture 6b compare match or input capture 6c compare match or input capture 6d overflow 4 sources compare match or input capture 7a compare match or input capture 7b overflow underflow 4 sources compare match or input capture 8a compare match or input capture 8b overflow underflow 5 sources compare match or input capture 9a compare match or input capture 9b compare match or input capture 9c compare match or input capture 9d overflow 4 sources compare match or input capture 10a compare match or input capture 10b overflow underflow 4 sources compare match or input capture 11a compare match or input capture 11b overflow underflow [legend] o : possible ? : not possible section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 470 of 1102 rej09b0365-0100 channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr input/output pins tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 clock input p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal ppg output trigger signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: [legend] tstr: timer start register tsyr: timer synchronous register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) tcnt: timer counter channel 2 common channel 5 bus interface figure 12.1 block diagram of tpu (unit 0) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 471 of 1102 rej09b0365-0100 channel 11 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 10 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 9 to 11 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 7 tmdr tsr tcr tior tier tgra tcnt tgrb channel 6 tmdr tsr tcr tiorh tier control logic for channels 6 to 8 tgra tcnt tgrb tgrd tsyrb tstrb input/output pins tioca9 tiocb9 tiocc9 tiocd9 tioca10 tiocb10 tioca11 tiocb11 clock input p /1 p /4 p /16 p /64 p /256 p /1024 p /4096 tclke tclkf tclkg tclkh input/output pins tioca6 tiocb6 tiocc6 tiocd6 tioca7 tiocb7 tioca8 tiocb8 interrupt request signals channel 9: channel 10: channel 11: interrupt request signals channel 6: channel 7: channel 8: internal data bus tiorl module data bus tgi9a tgi9b tgi9c tgi9d tci9v tgi10a tgi10b tci10v tci10u tgi11a tgi11b tci11v tci11u tgi6a tgi6b tgi6c tgi6d tci6v tgi7a tgi7b tci7v tci7u tgi8a tgi8b tci8v tci8u channel 9: channel 10: channel 11: internal clock: external clock: channel 6: channel 7: channel 8: [legend] tstrb: timer start register tsyrb: timer synchronous register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) tcnt: timer counter channel 8 common channel 9 bus interface ppg output trigger signal figure 12.2 block diagram of tpu (unit 1) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 472 of 1102 rej09b0365-0100 12.2 input/output pins table 12.3 shows tpu pin configurations. table 12.3 pin configuration unit channel symbol i/o function all tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) 0 tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 tioca0 i/o tgra_0 input capture input/output compare output/pwm output pin tiocb0 i/o tgrb_0 input capture input/output compare output/pwm output pin tiocc0 i/o tgrc_0 input capture input/output compare output/pwm output pin tiocd0 i/o tgrd_0 input capture input/output compare output/pwm output pin 1 tioca1 i/o tgra_1 input capture input/output compare output/pwm output pin tiocb1 i/o tgrb_1 input capture input/output compare output/pwm output pin 2 tioca2 i/o tgra_2 input capture input/output compare output/pwm output pin tiocb2 i/o tgrb_2 input capture input/output compare output/pwm output pin 3 tioca3 i/o tgra_3 input capture input/output compare output/pwm output pin tiocb3 i/o tgrb_3 input capture input/output compare output/pwm output pin tiocc3 i/o tgrc_3 input capture input/output compare output/pwm output pin tiocd3 i/o tgrd_3 input capture input/output compare output/pwm output pin 4 tioca4 i/o tgra_4 input capture input/output compare output/pwm output pin tiocb4 i/o tgrb_4 input capture input/output compare output/pwm output pin 5 tioca5 i/o tgra_5 input capture input/output compare output/pwm output pin tiocb5 i/o tgrb_5 input capture input/output compare output/pwm output pin section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 473 of 1102 rej09b0365-0100 unit channel symbol i/o function all tclke input external clock e input pin (channel 7 and 11 phase counting mode a phase input) tclkf input external clock f input pin (channel 7 and 11 phase counting mode b phase input) tclkg input external clock g input pin (channel 8 and 10 phase counting mode a phase input) 1 tclkh input external clock h input pin (channel 8 and 10 phase counting mode b phase input) 6 tioca6 i/o tgra_6 input capture input/output compare output/pwm output pin tiocb6 i/o tgrb_6 input capture input/output compare output/pwm output pin tiocc6 i/o tgrc_6 input capture input/output compare output/pwm output pin tiocd6 i/o tgrd_6 input capture input/output compare output/pwm output pin 7 tioca7 i/o tgra_7 input capture input/output compare output/pwm output pin tiocb7 i/o tgrb_7 input capture input/output compare output/pwm output pin 8 tioca8 i/o tgra_8 input capture input/output compare output/pwm output pin tiocb8 i/o tgrb_8 input capture input/output compare output/pwm output pin 9 tioca9 i/o tgra_9 input capture input/output compare output/pwm output pin tiocb9 i/o tgrb_9 input capture input/output compare output/pwm output pin tiocc9 i/o tgrc_9 input capture input/output compare output/pwm output pin tiocd9 i/o tgrd_9 input capture input/output compare output/pwm output pin 10 tioca10 i/o tgra_10 input capture input/output compare output/pwm output pin tiocb10 i/o tgrb_10 input capture input/output compare output/pwm output pin 11 tioca11 i/o tgra_11 input capture input/output compare output/pwm output pin tiocb11 i/o tgrb_11 input capture input/output compare output/pwm output pin section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 474 of 1102 rej09b0365-0100 12.3 register descriptions the tpu has the following registers in each channel. registers in the unit 0 and unit 1 have the same functions except for the bit 7 in tier, namely, the ttge bit in unit 0 and a reserved bit in unit 1. this section gives explanations regarding unit 0. unit 0: ? channel 0: ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register h_0 (tiorh_0) ? timer i/o control register l_0 (tiorl_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) ? channel 1: ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 475 of 1102 rej09b0365-0100 ? channel 2: ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? channel 3: ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) ? timer i/o control register h_3 (tiorh_3) ? timer i/o control register l_3 (tiorl_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? channel 4: ? timer control register_4 (tcr_4) ? timer mode register_4 (tmdr_4) ? timer i/o control register _4 (tior_4) ? timer interrupt enable register_4 (tier_4) ? timer status register_4 (tsr_4) ? timer counter_4 (tcnt_4) ? timer general register a_4 (tgra_4) ? timer general register b_4 (tgrb_4) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 476 of 1102 rej09b0365-0100 ? channel 5: ? timer control register_5 (tcr_5) ? timer mode register_5 (tmdr_5) ? timer i/o control register_5 (tior_5) ? timer interrupt enable register_5 (tier_5) ? timer status register_5 (tsr_5) ? timer counter_5 (tcnt_5) ? timer general register a_5 (tgra_5) ? timer general register b_5 (tgrb_5) ? common registers: ? timer start register (tstr) ? timer synchronous register (tsyr) unit 1: ? channel 6: ? timer control register_6 (tcr_6) ? timer mode register_6 (tmdr_6) ? timer i/o control register h_6 (tiorh_6) ? timer i/o control register l_6 (tiorl_6) ? timer interrupt enable register_6 (tier_6) ? timer status register_6 (tsr_6) ? timer counter_6 (tcnt_6) ? timer general register a_6 (tgra_6) ? timer general register b_6 (tgrb_6) ? timer general register c_6 (tgrc_6) ? timer general register d_6 (tgrd_6) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 477 of 1102 rej09b0365-0100 ? channel 7: ? timer control register_7 (tcr_7) ? timer mode register_7 (tmdr_7) ? timer i/o control register _7 (tior_7) ? timer interrupt enable register_7 (tier_7) ? timer status register_7 (tsr_7) ? timer counter_7 (tcnt_7) ? timer general register a_7 (tgra_7) ? timer general register b_7 (tgrb_7) ? channel 8: ? timer control register_8 (tcr_8) ? timer mode register_8 (tmdr_8) ? timer i/o control register_8 (tior_8) ? timer interrupt enable register_8 (tier_8) ? timer status register_8 (tsr_8) ? timer counter_8 (tcnt_8) ? timer general register a_8 (tgra_8) ? timer general register b_8 (tgrb_8) ? channel 9: ? timer control register_9 (tcr_9) ? timer mode register_9 (tmdr_9) ? timer i/o control register h_9 (tiorh_9) ? timer i/o control register l_9 (tiorl_9) ? timer interrupt enable register_9 (tier_9) ? timer status register_9 (tsr_9) ? timer counter_9 (tcnt_9) ? timer general register a_9 (tgra_9) ? timer general register b_9 (tgrb_9) ? timer general register c_9 (tgrc_9) ? timer general register d_9 (tgrd_9) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 478 of 1102 rej09b0365-0100 ? channel 10: ? timer control register_10 (tcr_10) ? timer mode register_10 (tmdr_10) ? timer i/o control register _10 (tior_10) ? timer interrupt enable register_10 (tier_10) ? timer status register_10 (tsr_10) ? timer counter_10 (tcnt_10) ? timer general register a_10 (tgra_10) ? timer general register b_10 (tgrb_10) ? channel 11: ? timer control register_11 (tcr_11) ? timer mode register_11 (tmdr_11) ? timer i/o control register_11 (tior_11) ? timer interrupt enable register_11 (tier_11) ? timer status register_11 (tsr_11) ? timer counter_11 (tcnt_11) ? timer general register a_11 (tgra_11) ? timer general register b_11 (tgrb_11) ? common registers: ? timer start register (tstrb) ? timer synchronous register (tsyrb) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 479 of 1102 rej09b0365-0100 12.3.1 timer control register (tcr) tcr controls the tcnt operation for each channel. the tpu has a total of six tcr registers, one for each channel. tcr register settings should be made only while tcnt operation is stopped. 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 2 to 0 these bits select the tcnt counter clearing source. see tables 12.4 and 12.5 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 these bits select the input clock edge. for details, see table 12.6. when the input clock is counted using both edges, the input clock period is halved (e.g. p /4 both edges = p /2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. internal clock edge selection is valid when the input clock is p /4 or slower. this setting is ignored if the input clock is p /1, or when overflow/underflow of another channel is selected. 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler 2 to 0 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables 12.7 to 12.12 for details. to select the external clock as the clock source, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, respectively. for details, see section 11, i/o ports. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 480 of 1102 rej09b0365-0100 table 12.4 cclr2 to cclr0 (channels 0 and 3) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0 0 0 tcnt clearing disabled 0 0 1 tcnt cleared by tgra compare match/input capture 0 1 0 tcnt cleared by tgrb compare match/input capture 0 1 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 0 1 tcnt cleared by tgrc compare match/input capture * 2 1 1 0 tcnt cleared by tgrd compare match/input capture * 2 0, 3 1 1 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is select ed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer re gister, tcnt is not cleared because the buffer register setting has priority, and comp are match/input capture does not occur. table 12.5 cclr2 to cclr0 (channels 1, 2, 4, and 5) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 0 0 0 tcnt clearing disabled 0 0 1 tcnt cleared by tgra compare match/input capture 0 1 0 tcnt cleared by tgrb compare match/input capture 1, 2, 4, 5 0 1 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is select ed by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 481 of 1102 rej09b0365-0100 table 12.6 input cl ock edge selection clock edge selection input clock ckeg1 ckeg0 internal clock external clock 0 0 counted at falling edge counted at rising edge 0 1 counted at rising edge counted at falling edge 1 x counted at both edges counted at both edges [legend] x: don't care table 12.7 tpsc2 to tpsc0 (channel 0) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkb pin input 1 1 0 external clock: counts on tclkc pin input 0 1 1 1 external clock: counts on tclkd pin input table 12.8 tpsc2 to tpsc0 (channel 1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkb pin input 1 1 0 internal clock: counts on p /256 1 1 1 1 counts on tcnt2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 482 of 1102 rej09b0365-0100 table 12.9 tpsc2 to tpsc0 (channel 2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkb pin input 1 1 0 external clock: counts on tclkc pin input 2 1 1 1 internal clock: counts on p /1024 note: this setting is ignored when channel 2 is in phase counting mode. table 12.10 tpsc2 to tpsc0 (channel 3) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 internal clock: counts on p /1024 1 1 0 internal clock: counts on p /256 3 1 1 1 internal clock: counts on p /4096 section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 483 of 1102 rej09b0365-0100 table 12.11 tpsc2 to tpsc0 (channel 4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkc pin input 1 1 0 internal clock: counts on p /1024 4 1 1 1 counts on tcnt5 overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. table 12.12 tpsc2 to tpsc0 (channel 5) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: counts on p /1 0 0 1 internal clock: counts on p /4 0 1 0 internal clock: counts on p /16 0 1 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 0 1 external clock: counts on tclkc pin input 1 1 0 internal clock: counts on p /256 5 1 1 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 484 of 1102 rej09b0365-0100 12.3.2 timer mode register (tmdr) tmdr sets the operating mode for each channel. the tpu has six tmdr registers, one for each channel. tmdr register settings should be made only while tcnt operation is stopped. 7 ? 1 ? 6 ? 1 ? 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 md0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to normally operate, or tgrb and tgrd are to be used toget her for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output com pare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation 4 bfa 0 r/w buffer operation a specifies whether tgra is to normally operate, or tgra and tgrc are to be used toget her for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output com pare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. 0: tgra operates normally 1: tgra and tgrc used together for buffer operation 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 3 to 0 set the timer operating mode. md3 is a reserved bit. the write value should always be 0. see table 12.13 for details. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 485 of 1102 rej09b0365-0100 table 12.13 md3 to md0 bit 3 md3 * 1 bit 2 md2 * 2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 0 0 0 1 reserved 0 0 1 0 pwm mode 1 0 0 1 1 pwm mode 2 0 1 0 0 phase counting mode 1 0 1 0 1 phase counting mode 2 0 1 1 0 phase counting mode 3 0 1 1 1 phase counting mode 4 1 x x x ? [legend] x: don't care notes: 1. md3 is a reserved bit. the write value should always be 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 486 of 1102 rej09b0365-0100 12.3.3 timer i/o cont rol register (tior) tior controls tgr. the tpu has eight tior regi sters, two each for cha nnels 0 and 3, and one each for channels 1, 2, 4, and 5. care is requir ed since tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. to designate the input capture pin in tior, th e ddr bit and icr bit for the corresponding pin should be set to 0 and 1, respetively. for details, see section 11, i/o ports. ? tiorh_0, tior_1, tior_2, tiorh_3, tior_4, tior_5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w bit bit name initial value r/w ? tiorl_0, torl_3 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w 0 ioc0 0 r/w bit bit name initial value r/w section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 487 of 1102 rej09b0365-0100 ? tiorh_0, tior_1, tior_2, tiorh_3, tior_4, tior_5 bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 0 0 0 0 r/w r/w r/w r/w i/o control b3 to b0 specify the function of tgrb. for details, see tables 12. 14, 12.16 to 12.18, 12.20 and 12.21. 3 2 1 0 ioa3 ioa2 ioa1 ioa0 0 0 0 0 r/w r/w r/w r/w i/o control a3 to a0 specify the function of tgra. for details, see tables 12. 22, 12.24 to 12.26, 12.28, and 12.29. ? tiorl_0, tiorl_3 bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 0 0 0 0 r/w r/w r/w r/w i/o control d3 to d0 specify the function of tgrd. for details, see tables 12.15, and 12.19. 3 2 1 0 ioc3 ioc2 ioc1 ioc0 0 0 0 0 r/w r/w r/w r/w i/o control c3 to c0 specify the function of tgrc. for details, see tables 12.23, and 12.27. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 488 of 1102 rej09b0365-0100 table 12.14 tiorh_0 description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tiocb0 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb0 pin input capture at rising edge 1 0 0 1 capture input source is tiocb0 pin input capture at falling edge 1 0 1 x capture input source is tiocb0 pin input capture at both edges 1 1 x x input capture register capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down * [legend] x: don't care note: when bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the tcnt_1 count clock, this setting is invalid and input capture is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 489 of 1102 rej09b0365-0100 table 12.15 tiorl_0 description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tiocd0 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocd0 pin input capture at rising edge 1 0 0 1 capture input source is tiocd0 pin input capture at falling edge 1 0 1 x capture input source is tiocd0 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down * 1 [legend] x: don't care notes: 1. when bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the tcnt_1 count clock, this setting is inva lid and input capture is not generated. 2. when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 490 of 1102 rej09b0365-0100 table 12.16 tior_1 description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tiocb1 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb1 pin input capture at rising edge 1 0 0 1 capture input source is tiocb1 pin input capture at falling edge 1 0 1 x capture input source is tiocb1 pin input capture at both edges 1 1 x x input capture register tgrc_0 compare match/input capture input capture at generat ion of tgrc_0 compare match/input capture [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 491 of 1102 rej09b0365-0100 table 12.17 tior_2 description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tiocb2 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tiocb2 pin input capture at rising edge 1 x 0 1 capture input source is tiocb2 pin input capture at falling edge 1 x 1 x input capture register capture input source is tiocb2 pin input capture at both edges [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 492 of 1102 rej09b0365-0100 table 12.18 tiorh_3 description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_3 function tiocb3 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb3 pin input capture at rising edge 1 0 0 1 capture input source is tiocb3 pin input capture at falling edge 1 0 1 x capture input source is tiocb3 pin input capture at both edges 1 1 x x input capture register capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * [legend] x: don't care note: when bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 493 of 1102 rej09b0365-0100 table 12.19 tiorl_3 description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_3 function tiocd3 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocd3 pin input capture at rising edge 1 0 0 1 capture input source is tiocd3 pin input capture at falling edge 1 0 1 x capture input source is tiocd3 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * 1 [legend] x: don't care notes: 1. when bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the tcnt_4 count clock, this setting is inva lid and input capture is not generated. 2. when the bfb bit in tmdr_3 is set to 1 and tgrd_3 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 494 of 1102 rej09b0365-0100 table 12.20 tior_4 description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_4 function tiocb4 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocb4 pin input capture at rising edge 1 0 0 1 capture input source is tiocb4 pin input capture at falling edge 1 0 1 x capture input source is tiocb4 pin input capture at both edges 1 1 x x input capture register capture input source is tgrc_3 compare match/input capture input capture at generat ion of tgrc_3 compare match/input capture [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 495 of 1102 rej09b0365-0100 table 12.21 tior_5 description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_5 function tiocb5 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tiocb5 pin input capture at rising edge 1 x 0 1 capture input source is tiocb5 pin input capture at falling edge 1 x 1 x input capture register capture input source is tiocb5 pin input capture at both edges [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 496 of 1102 rej09b0365-0100 table 12.22 tiorh_0 description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioca0 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 1 capture input source is tioca0 pin input capture at rising edge 1 0 0 0 capture input source is tioca0 pin input capture at falling edge 1 0 1 x capture input source is tioca0 pin input capture at both edges 1 1 x x input capture register capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down * [legend] x: don't care note: * when the bits tpsc2 to tpsc0 in tcr_1 are set to b'000 and p /1 is used as the count clock of tcnt_1, this setting is in valid and input capture is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 497 of 1102 rej09b0365-0100 table 12.23 tiorl_0 description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tiocc0 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocc0 pin input capture at rising edge 1 0 0 1 capture input source is tiocc0 pin input capture at falling edge 1 0 1 x capture input source is tiocc0 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down * 1 [legend] x: don't care note: 1. when the bits tpsc2 to t psc0 in tcr_1 are set to b'000 and p /1 is used as the count clock of tcnt_1, this setting is in valid and input capture is not generated. 2. when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 498 of 1102 rej09b0365-0100 table 12.24 tior_1 description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioca1 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca1 pin input capture at rising edge 1 0 0 1 capture input source is tioca1 pin input capture at falling edge 1 0 1 x capture input source is tioca1 pin input capture at both edges 1 1 x x input capture register capture input source is tgra_0 compare match/input capture input capture at generati on of channel 0/tgra_0 compare match/input capture [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 499 of 1102 rej09b0365-0100 table 12.25 tior_2 description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioca2 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 capture input source is tioca2 pin input capture at rising edge 1 x 0 1 capture input source is tioca2 pin input capture at falling edge 1 x 1 x input capture register capture input source is tioca2 pin input capture at both edges [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 500 of 1102 rej09b0365-0100 table 12.26 tiorh_3 description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_3 function tioca3 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca3 pin input capture at rising edge 1 0 0 1 capture input source is tioca3 pin input capture at falling edge 1 0 1 x capture input source is tioca3 pin input capture at both edges 1 1 x x input capture register capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * [legend] x: don't care note: * when the bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the count clock of tcnt_4, this setting is in valid and input capture is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 501 of 1102 rej09b0365-0100 table 12.27 tiorl_3 description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_3 function tiocc3 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tiocc3 pin input capture at rising edge 1 0 0 1 capture input source is tiocc3 pin input capture at falling edge 1 0 1 x capture input source is tiocc3 pin input capture at both edges 1 1 x x input capture register * 2 capture input source is channel 4/count clock input capture at tcnt _4 count-up/count-down * 1 [legend] x: don't care note: 1. when the bits tpsc2 to tpsc0 in tcr_4 are set to b'000 and p /1 is used as the count clock of tcnt_4, this setting is in valid and input capture is not generated. 2. when the bfa bit in tmdr_3 is set to 1 and tgrc_3 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 502 of 1102 rej09b0365-0100 table 12.28 tior_4 description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_4 function tioca4 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 0 0 0 capture input source is tioca4 pin input capture at rising edge 1 0 0 1 capture input source is tioca4 pin input capture at falling edge 1 0 1 x capture input source is tioca4 pin input capture at both edges 1 1 x x input capture register capture input source is tgra_3 compare match/input capture input capture at generat ion of tgra_3 compare match/input capture [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 503 of 1102 rej09b0365-0100 table 12.29 tior_5 description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_5 function tioca5 pin function 0 0 0 0 output disabled 0 0 0 1 initial output is 0 output 0 output at compare match 0 0 1 0 initial output is 0 output 1 output at compare match 0 0 1 1 initial output is 0 output toggle output at compare match 0 1 0 0 output disabled 0 1 0 1 initial output is 1 output 0 output at compare match 0 1 1 0 initial output is 1 output 1 output at compare match 0 1 1 1 output compare register initial output is 1 output toggle output at compare match 1 x 0 0 input capture source is tioca5 pin input capture at rising edge 1 x 0 1 input capture source is tioca5 pin input capture at falling edge 1 x 1 x input capture register input capture source is tioca5 pin input capture at both edges [legend] x: don't care section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 504 of 1102 rej09b0365-0100 12.3.4 timer interrupt enable register (tier) tier controls enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. bit bit name initial value r/w 7 ttge * 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 tgied 0 r/w 2 tciec 0 r/w 1 tgieb 0 r/w 0 tgiea 0 r/w note: * bit 7 in tier of unit 1 is a reserved bit. this bit is always read as 0 and the initial value should not be changed. bit bit name initial value r/w description 7 ttge * 0 r/w a/d conversion start request enable enables/disables generatio n of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcieu 0 r/w underflow interrupt enable enables/disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled 4 tciev 0 r/w overflow interrupt enable enables/disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 505 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 tgied 0 r/w tgr interrupt enable d enables/disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgid ) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled 2 tgiec 0 r/w tgr interrupt enable c enables/disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgic ) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables/disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables/disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled note: * the bit 7 in tier of unit 1 is a reserved bit this bit is always read as 0 and the initial value should not be changed. 12.3.5 timer status register (tsr) tsr indicates the status of each channel. the tpu has six tsr registers, one for each channel. bit bit name initial value r/w 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * 0 tgfa 0 r/(w) * note: * only 0 can be written to bits 5 to 0, to clear flags. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 506 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 tcfd 1 r count direction flag status flag that shows the dire ction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. 0: tcnt counts down 1: tcnt counts up 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcfu 0 r/(w) * underflow flag status flag that indicates that a tcnt underflow has occurred when channels 1, 2, 4, and 5 ar e set to phase counting mode. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] when a 0 is written to tcfu after reading tcfu = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4 tcfv 0 r/(w) * overflow flag status flag that indicates that a tcnt overflow has occurred. [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000) [clearing condition] when a 0 is written to tcfv after reading tcfv = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 507 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 tgfd 0 r/(w) * input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgid interrupt while the disel bit in mrb of dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 2 tgfc 0 r/(w) * input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgic interrupt while the disel bit in mrb of dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 508 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 tgfb 0 r/(w) * input capture/output compare flag b status flag that indicates t he occurrence of tgrb input capture or compare match. [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgib interrupt while the disel bit in mrb of dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 0 tgfa 0 r/(w) * input capture/output compare flag a status flag that indicates t he occurrence of tgra input capture or compare match. [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing conditions] ? when dtc is activated by a tgia interrupt while the disel bit in mrb of dtc is 0 ? when dmac is activated by a tgia interrupt while the dta bit in dmdr of dtc is 1 ? when 0 is written to tgfa after reading tgfa = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) note: * only 0 can be written to clear the flag. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 509 of 1102 rej09b0365-0100 12.3.6 timer counter (tcnt) tcnt is a 16-bit readable/writable counter. the tpu has six tcnt counters, one for each channel. tcnt is initialized to h'0000 by a reset or in hardware standby mode. tcnt cannot be accessed in 8-bit units. tcnt must always be accessed in 16-bit units. bit bit name initial value r/w 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 12.3.7 timer general register (tgr) tgr is a 16-bit readable/writable register with a dual function as output compare and input capture registers. the tpu has 16 tgr registers, four each for ch annels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers. the tgr register s cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. tgr and buffer re gister combinations du ring buffer operations are tgra ? tgrc and tgrb ? tgrd. bit bit name initial value r/w 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w bit bit name initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 510 of 1102 rej09b0365-0100 12.3.8 timer start register (tstr) tstr starts or stops operation for channels 0 to 5. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. 7 ? 0 ? 6 ? 0 ? 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w 0 cst0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7, 6 ? all 0 ? reserved the write value should always be 0. 5 4 3 2 1 0 cst5 cst4 cst3 cst2 cst1 cst0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w counter start 5 to 0 these bits select operat ion or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for outpu t, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_5 to tcnt_0 coun t operation is stopped 1: tcnt_5 to tcnt_0 per forms count operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 511 of 1102 rej09b0365-0100 12.3.9 timer synchronous register (tsyr) tsyr selects independent operation or synchronous operation for the tcnt counters of channels 0 to 5. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. 7 ? 0 r/w 6 ? 0 r/w 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved the write value should always be 0. 5 4 3 2 1 0 sync5 sync4 sync3 sync2 sync1 sync0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w timer synchronization 5 to 0 these bits select whether oper ation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 0: tcnt_5 to tcnt_0 oper ate independently (tcnt presetting/clearing is unrelated to other channels) 1: tcnt_5 to tcnt_0 perfo rm synchronous operation (tcnt synchronous presetting/synchronous clearing is possible) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 512 of 1102 rej09b0365-0100 12.4 operation 12.4.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, an d is also capable of free-running operation, periodic counting, and external event counting. each tgr can be used as an input captur e register or output compare register. (1) counter operation when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counte r, periodic counter, and so on. (a) example of count opera tion setting procedure figure 12.3 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 513 of 1102 rej09b0365-0100 (b) free-running count operation and periodic count operation immediately after a reset, the tpu's tcnt counte rs are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up-count operation as a free-running counter. when tcnt overflows (changes from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 12.4 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 12.4 free-running counter operation when compare match is selected as the tcnt cl earing source, the tcnt co unter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts count-up operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 514 of 1102 rej09b0365-0100 figure 12.5 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc activation figure 12.5 periodic counter operation (2) waveform output by compare match the tpu can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) example of setting procedure for waveform output by compare match figure 12.6 shows an example of the setting procedure for waveform output by a compare match. select waveform output mode output selection set output timing start count section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 515 of 1102 rej09b0365-0100 (b) examples of waveform output operation figure 12.7 shows an example of 0 output/1 output . in this example, tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level match, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1-output 0-output figure 12.7 example of 0-output/1-output operation figure 12.8 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle-output toggle-output counter cleared by tgrb compare match figure 12.8 example of toggle output operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 516 of 1102 rej09b0365-0100 (3) input capture function the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detection edge. for channels 0, 1, 3, and 4, it is also possible to specify another cha nnel's counter input clock or compare match signal as the input capture source. note: when another channel's counter input clock is used as the input capture input for channels 0 and 3, p /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if p /1 is selected. (a) example of setting procedu re for input capture operation figure 12.9 shows an example of the setting procedure for input capture operation. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [2] set the cst bit in tstr to 1 to start the count operation. figure 12.9 example of setting pr ocedure for input capture operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 517 of 1102 rej09b0365-0100 (b) example of input capture operation figure 12.10 shows an example of input capture operation. in this example, both rising and falling edges have been selected as the tioca pin input capture input edge, falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb inpu t capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 12.10 example of input capture operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 518 of 1102 rej09b0365-0100 12.4.2 synchronous operation in synchronous operation, the values in multiple tcnt counters can be rewritten simultaneously (synchronous presetting). also, multiple tcnt counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in tcr. synchronous operation enables tgr to be incr emented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. (1) example of synchronous operation setting procedure figure 12.11 shows an example of the synchronous operation setting procedure. synchronous operation selection set tcnt synchronous presetting section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 519 of 1102 rej09b0365-0100 (2) example of synchronous operation figure 12.12 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgrb_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioca0, tioca1, and tioca2. at this time, synchronous presetting and synchronous cl earing by tgrb_0 compare match are performed for channel 0 to 2 tcnt counters, and the data set in tgrb_0 is used as the pwm cycle. for details on pwm modes, see section 12.4.5, pwm modes. tcnt_0 to tcnt_2 values h'0000 tioca_0 tioca_1 tgrb_0 synchronous clearing by tgrb_0 compare match tgra_2 tgra_1 tgrb_2 tgra_0 tgrb_1 tioca_2 time figure 12.12 example of synchronous operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 520 of 1102 rej09b0365-0100 12.4.3 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc an d tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or a compare match register. table 12.30 shows the register combinations used in buffer operation. table 12.30 register combinat ions in buffer operation channel timer general re gister buffer register tgra_0 tgrc_0 0 tgrb_0 tgrd_0 tgra_3 tgrc_3 3 tgrb_3 tgrd_3 ? when tgr is an output compare register when a compare match occurs, the value in the bu ffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 12.13. buffer register timer general register tcnt comparator compare match signal figure 12.13 compare match buffer operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 521 of 1102 rej09b0365-0100 ? when tgr is an inpu t capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in tgr is transferre d to the buffer register. this operation is illustrated in figure 12.14. buffer register timer general register tcnt input capture signal figure 12.14 input capture buffer operation (1) example of buffer operation setting procedure figure 12.15 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 522 of 1102 rej09b0365-0100 (2) examples of buffer operation (a) when tgr is an output compare register figure 12.16 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been se t, when compare match a occurs, the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details on pwm modes, see section 12.4.5, pwm modes. tcnt value tgrb_0 h'0000 tgrc_0 tgra_0 h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgra_0 h'0450 h'0200 transfer time figure 12.16 example of buffer operation (1) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 523 of 1102 rej09b0365-0100 (b) when tgr is an input capture register figure 12.17 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 12.17 example of buffer operation (2) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 524 of 1102 rej09b0365-0100 12.4.4 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of tcnt_2 (tcnt_5) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 12.31 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 12.31 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt_1 tcnt_2 channels 4 and 5 tcnt_4 tcnt_5 (1) example of cascaded op eration setting procedure figure 12.18 shows an example of the setting procedure for cascaded operation. cascaded operation set cascading start count section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 525 of 1102 rej09b0365-0100 (2) examples of cascaded operation figure 12.19 illustrates the operation when counting upon tcnt_2 overflow/underflow has been set for tcnt_1, tgra_1 and tgra_2 have been designated as input capture registers, and the tioc pin rising edge has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgra _1, and the lower 16 bits to tgra_2. tcnt_2 clock tcnt_2 h'ffff h'0000 h'0001 tioca1, tioca2 tgra_1 h'03a2 tgra_2 h'0000 tcnt_1 clock tcnt_1 h'03a1 h'03a2 figure 12.19 example of cascaded operation (1) figure 12.20 illustrates the operation when counting upon tcnt_2 overflow/underflow has been set for tcnt_1, and phase counting mode has been designated for channel 2. tcnt_1 is incremented by tcnt_2 overflow and decremented by tcnt_2 underflow. tclkc tcnt_2 fffd tcnt_1 0001 tclkd fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 12.20 example of cascaded operation (2) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 526 of 1102 rej09b0365-0100 12.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each tgr. settings of tgr registers can output a pwm waveform in the range of 0% to 100% duty cycle. designating tgr compare match as the counter clear ing source enables the cycl e to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. 1. pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the outputs specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior are output from the tioca and tiocc pins at compare matches a and c, respectively. the outputs specified by bits iob3 to iob0 and iod3 to iod0 in tior are output at compare matches b and d, respectively. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value do es not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. 2. pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty cycle registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronou s register compare match, the output value of each pin is the initial value set in tior. if the set values of th e cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 12.32. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 527 of 1102 rej09b0365-0100 table 12.32 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 tgra_0 tioca0 tgrb_0 tioca0 tiocb0 tgrc_0 tiocc0 0 tgrd_0 tiocc0 tiocd0 tgra_1 tioca1 1 tgrb_1 tioca1 tiocb1 tgra_2 tioca2 2 tgrb_2 tioca2 tiocb2 tgra_3 tioca3 tgrb_3 tioca3 tiocb3 tgrc_3 tiocc3 3 tgrd_3 tiocc3 tiocd3 tgra_4 tioca4 4 tgrb_4 tioca4 tiocb4 tgra_5 tioca5 5 tgrb_5 tioca5 tiocb5 note: in pwm mode 2, pwm output is not possible fo r the tgr register in which the cycle is set. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 528 of 1102 rej09b0365-0100 (1) example of pwm mode setting procedure figure 12.21 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 529 of 1102 rej09b0365-0100 tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 12.22 example of pwm mode operation (1) figure 12.23 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgrb_1 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_0 to tgrd_0, tgra_1), to output a 5-phase pwm waveform. in this case, the value set in tgrb_1 is used as the cycle, and the values set in the other tgrs as the duty cycle. tcnt value tgrb_1 h'0000 tioca0 counter cleared by tgrb_1 compare match time tgra_1 tgrd_0 tgrc_0 tgrb_0 tgra_0 tiocb0 tiocc0 tiocd0 tioca1 figure 12.23 example of pwm mode operation (2) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 530 of 1102 rej09b0365-0100 figure 12.24 shows examples of pwm waveform output with 0% duty cycle and 100% duty cycle in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb changed tgrb changed tgrb changed tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb changed tgrb changed tgrb changed output does not change when compare matches in cycle register and duty register occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb changed tgrb changed tgrb changed output does not change when compare matches in cycle register and duty register occur simultaneously 0% duty figure 12.24 example of pwm mode operation (3) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 531 of 1102 rej09b0365-0100 12.4.6 phase counting mode in phase counting mode, the phase difference betw een two external clock inputs is detected and tcnt is incremented/decremented acco rdingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. this can be used for two-phase encoder pulse input. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag pr ovides an indication of whether tcnt is counting up or down. table 12.33 shows the correspondence between external clock pins and channels. table 12.33 clock input pins in phase counting mode external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 532 of 1102 rej09b0365-0100 (1) example of phase counting mode setting procedure figure 12.25 shows an example of the phase counting mode setting procedure. phase counting mode select phase counting mode start count section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 533 of 1102 rej09b0365-0100 (2) examples of phase counting mode operation in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. (a) phase counting mode 1 figure 12.26 shows an example of phase counting mode 1 operation, and table 12.34 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 12.26 example of phase counting mode 1 operation table 12.34 up/down-count condit ions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level low level low level high level up-count high level low level high level low level down-count [legend] : rising edge : falling edge section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 534 of 1102 rej09b0365-0100 (b) phase counting mode 2 figure 12.27 shows an example of phase counting mode 2 operation, and table 12.35 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 12.27 example of phase counting mode 2 operation table 12.35 up/down-count condit ions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don't care low level don't care low level don't care high level up-count high level don't care low level don't care high level don't care low level down-count [legend] : rising edge : falling edge section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 535 of 1102 rej09b0365-0100 (c) phase counting mode 3 figure 12.28 shows an example of phase counting mode 3 operation, and table 12.36 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 12.28 example of phase counting mode 3 operation table 12.36 up/down-count condit ions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don't care low level don't care low level don't care high level up-count high level down-count low level don't care high level don't care low level don't care [legend] : rising edge : falling edge section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 536 of 1102 rej09b0365-0100 (d) phase counting mode 4 figure 12.29 shows an example of phase counting mode 4 operation, and table 12.37 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 12.29 example of phase counting mode 4 operation table 12.37 up/down-count condit ions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level low level up-count low level high level don't care high level low level down-count high level low level don't care [legend] : rising edge : falling edge section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 537 of 1102 rej09b0365-0100 (3) phase counting mode application example figure 12.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgrc_0 compare match; tgra_0 and tgrc_0 are used for the compare match function and are set with the speed control cycle and position control cycle. tgrb_0 is used for input capture, with tgrb_0 and tgrd_0 operating in buffer mode. the channel 1 counter input clock is designated as the tgrb_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. tgra_1 and tgrb_1 for channel 1 are designated for input capture, channel 0 tgra_0 and tgrc_0 compare matches are selected as the in put capture source, and the up/down-counter values for the control cycles are stored. this procedure enables accurate position/speed detection to be achieved. tcnt_1 tcnt_0 channel 1 tgra_1 (speed cycle capture) tgra_0 (speed control cycle) tgrb_1 (position cycle capture) tgrc_0 (position control cycle) tgrb_0 (pulse width capture) tgrd_0 (buffer operation) channel 0 tclka tclkb edge detection circuit + - + - figure 12.30 phase counting mode application example section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 538 of 1102 rej09b0365-0100 12.5 interrupt sources there are three kinds of tpu interrupt sources: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by cl earing the status flag to 0. relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. for details, see section 6, interrupt controller. table 12.38 lists the tpu interrupt sources. table 12.38 tpu interrupts channel name interrupt source interrupt flag dtc activation dmac activation 0 tgi0a tgra_0 input capture/com pare match tgfa_0 possible possible tgi0b tgrb_0 input capture/compar e match tgfb_0 possi ble not possible tgi0c tgrc_0 input capture/compar e match tgfc_0 possible not possible tgi0d tgrd_0 input capture/compar e match tgfd_0 possible not possible tci0v tcnt_0 overflow tcfv _0 not possible not possible 1 tgi1a tgra_1 input capture/com pare match tgfa_1 possible possible tgi1b tgrb_1 input capture/compar e match tgfb_1 possi ble not possible tci1v tcnt_1 overflow tcfv _1 not possible not possible tci1u tcnt_1 underflow tcfu _1 not possible not possible 2 tgi2a tgra_2 input capture/com pare match tgfa_2 possible possible tgi2b tgrb_2 input capture/compar e match tgfb_2 possi ble not possible tci2v tcnt_2 overflow tcfv _2 not possible not possible tci2u tcnt_2 underflow tcfu _2 not possible not possible section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 539 of 1102 rej09b0365-0100 channel name interrupt source interrupt flag dtc activation dmac activation 3 tgi3a tgra_3 input capture/com pare match tgfa_3 possible possible tgi3b tgrb_3 input capture/compar e match tgfb_3 possi ble not possible tgi3c tgrc_3 input capture/compar e match tgfc_3 possible not possible tgi3d tgrd_3 input capture/compar e match tgfd_3 possible not possible tci3v tcnt_3 overflow tcfv _3 not possible not possible 4 tgi4a tgra_4 input capture/com pare match tgfa_4 possible possible tgi4b tgrb_4 input capture/compar e match tgfb_4 possi ble not possible tci4v tcnt_4 overflow tcfv _4 not possible not possible tci4u tcnt_4 underflow tcfu _4 not possible not possible 5 tgi5a tgra_5 input capture/com pare match tgfa_5 possible possible tgi5b tgrb_5 input capture/compar e match tgfb_5 possi ble not possible tci5v tcnt_5 overflow tcfv _5 not possible not possible tci5u tcnt_5 underflow tcfu _5 not possible not possible note: this table shows the initial state immediat ely after a reset. the relative channel priority levels can be changed by the interrupt controller. (1) input capture/compare match interrupt an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a chan nel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and tw o each for channels 1, 2, 4, and 5. (2) overflow interrupt an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of a tcnt ov erflow on a channel. the interr upt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. (3) underflow interrupt an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of a tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four underflow interrupt s, one each for channels 1, 2, 4, and 5. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 540 of 1102 rej09b0365-0100 12.6 dtc activation the dtc can be activated by the tgr input capture /compare match interrupt for a channel. for details, see section 10, data transfer controller (dtc). a total of 16 tpu input capture/compare match in terrupts can be used as dtc activation sources, four each for channels 0 and 3, and tw o each for channels 1, 2, 4, and 5. 12.7 dmac activation the dmac can be activated by the tgra input capture/compare match in terrupt for a channel. for details, see section 9, dma controller (dmac). in tpu, one in each channel, totally six tgra input capture/compare match interrupts can be used as dmac activation sources. 12.8 a/d converter activation concerning the unit 0 in tpu, the tgra inpu t capture/compare match for each channel can activate the a/d converter. (however, the a/ d converter cannot be activated in unit 1.) if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/c ompare match interrupts can be used as a/d converter conversion start sour ces, one for each channel. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 541 of 1102 rej09b0365-0100 12.9 operation timing 12.9.1 input/output timing (1) tcnt count timing figure 12.31 shows tcnt count timing in internal clock operation, and figure 12.32 shows tcnt count timing in external clock operation. p internal clock tcnt input clock tcnt falling edge rising edge n ? 1n + 1n + 2 n falling edge figure 12.31 count timing in internal clock operation p external clock tcnt input clock tcnt falling edge rising edge n ? 1n + 1n + 2 n falling edge figure 12.32 count timing in external clock operation section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 542 of 1102 rej09b0365-0100 (2) output compare output timing a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 12.33 shows output compare output timing. p tcnt input clock tcnt n + 1 n compare match signal tioc pin tgr n figure 12.33 output compare output timing (3) input capture signal timing figure 12.34 shows input capture signal timing. p tcnt n + 1 n tgr input capture input input capture signal n + 2 n n + 2 figure 12.34 input capture input signal timing section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 543 of 1102 rej09b0365-0100 (4) timing for counter clearing by compare match/input capture figure 12.35 shows the timing when counter clear ing by compare match o ccurrence is specified, and figure 12.36 shows the timing when counter clearing by input capture occurrence is specified. p tcnt n tgr compare match signal counter clear signal h'0000 n figure 12.35 counter clea r timing (compare match) tgr counter clear signal h'0000 p tcnt n input capture signal n figure 12.36 counter clea r timing (input capture) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 544 of 1102 rej09b0365-0100 (5) buffer operation timing figures 12.37 and 12.38 show the timings in buffer operation. p n + 1 n tgra, tgrb tgrc, tgrd n n compare match signal tcnt n figure 12.37 buffer operat ion timing (compare match) p tcnt n + 1 n input capture signal tgra, tgrb tgrc, tgrd n n + 1 n nn figure 12.38 buffer operat ion timing (input capture) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 545 of 1102 rej09b0365-0100 12.9.2 interrupt signal timing (1) tgf flag setting timing in case of compare match figure 12.39 shows the timing for setting of the tgf flag in tsr by co mpare match occurrence, and the tgi interrupt request signal timing. tgr compare match signal p tcnt input clock tcnt n + 1 n n tgf flag tgi interrupt figure 12.39 tgi interrupt timing (compare match) (2) tgf flag setting timing in case of input capture figure 12.40 shows the timing for setting of the tgf flag in tsr by input capture occurrence, and the tgi interrupt request signal timing. tgr p tcnt n input capture signal tgf flag tgi interrupt n figure 12.40 tgi interrupt timing (input capture) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 546 of 1102 rej09b0365-0100 (3) tcfv flag/tcfu flag setting timing figure 12.41 shows the timing for setting of the tcfv flag in tsr by overflow occurrence, and the tciv interrupt request signal timing. figure 12.42 shows the timing for setting of the tcfu flag in tsr by underflow occurrence, and the tciu interrupt request signal timing. h'ffff p tcnt input clock tcnt (overflow) overflow signal tcfv flag tciv interrupt h'0000 figure 12.41 tciv in terrupt setting timing h'0000 p tcnt input clock tcnt (underflow) underflow signal tcfu flag tciu interrupt h'ffff figure 12.42 tciu in terrupt setting timing section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 547 of 1102 rej09b0365-0100 (4) status flag clearing timing after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc or dmac is activated, the flag is cleared automatically. figure 12.4 3 shows the timing for status flag clearing by the cpu, and figures 12.44 and 12.45 show the timing for status flag clearing by the dtc or dmac. status flag p interrupt request signal address write t 1 t 2 tsr address tsr write cycle figure 12.43 timing for st atus flag clearing by cpu the status flag and interrupt request sign al are cleared in sy nchronization with p after the dtc or dmac transfer has started, as shown in figure 12.4 4. if conflict occurs for clearing the status flag and interrupt request signal due to activation of mu ltiple dtc or dmac transfers, it will take up to five clock cycles (p ) for clearing them, as show n in figure 12.45. the next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (p ) from the beginning of the transfer. note th at in the dtc transfer, the status flag may be cleared during outputting the destination address. section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 548 of 1102 rej09b0365-0100 p address status flag interrupt request signal source address destination address period in which the next transfer request is masked t 1 t 2 dtc/dmac read cycle dtc/dmac write cycle t 1 t 2 figure 12.44 timing for status flag clearing by dtc/dmac activation (1) p address status flag interrupt request signal source address destination address period of flag clearing period of interrupt request signal clearing period in which the next transfer request is masked dtc/dmac read cycle dtc/dmac write cycle figure 12.45 timing for status flag clearing by dtc/dmac activation (2) section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 549 of 1102 rej09b0365-0100 12.10 usage notes 12.10.1 module stop function setting operation of the tpu can be disabled or enabled using the module stop control register. the initial setting is for operation of the tpu to be halted. re gister access is enabled by clearing module stop state. for details, see sec tion 24, power-down modes. 12.10.2 input clock restrictions the input clock pulse width must be at least 1.5 st ates in the case of single-edge detection, and at least 2.5 states in the case of both-edge detec tion. the tpu will not op erate properly with a narrower pulse width. in phase counting mode, the phase difference and ove rlap between the two inpu t clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 12.46 shows the input clock conditions in phase counting mode. tclka (tclkc) tclkb (tclkd) overlap phase difference pulse width note: phase difference, overlap 1.5 states pulse width 2.5 states pulse width phase difference overlap pulse width pulse width figure 12.46 phase difference, overlap, and pulse width in phase counting mode section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 550 of 1102 rej09b0365-0100 12.10.3 caution on cycle setting when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = p (n + 1) f: p : n: counter frequency operating frequency tgr set value 12.10.4 conflict between tcnt write and clear operations if the counter clearing signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 12.47 shows the timing in this case. counter clear signal h'0000 p tcnt n address write t 1 t 2 tcnt address tcnt write cycle figure 12.47 conflict between tc nt write and clear operations section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 551 of 1102 rej09b0365-0100 12.10.5 conflict between tcnt wr ite and increment operations if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 12 .48 shows the timing in this case. p tcnt input clock tcnt n address write t 1 t 2 tcnt write cycle m tcnt write data tcnt address figure 12.48 conflict between tcnt write and increment operations 12.10.6 conflict between tg r write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is disabled. a compare match also does not occur when the same value as before is written. figure 12.49 shows the timing in this case. tgr compare match signal p tcnt n + 1 n address write t 1 t 2 m tgr address tgr write cycle n disabled tgr write data figure 12.49 conflict between tgr write and compare match section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 552 of 1102 rej09b0365-0100 12.10.7 conflict between buffer re gister write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the write data. figure 12.50 shows the timing in this case. tgr compare match signal p n address write t 1 t 2 m tgr write cycle buffer register address data written to buffer register m buffer register figure 12.50 conflict between bu ffer register write and compare match 12.10.8 conflict between tgr read and input capture if the input capture signal is generated in the t1 st ate of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 12.51 shows the timing in this case. tgr p input capture signal address tgr address read t 1 t 2 tgr read cycle xm m internal data bus figure 12.51 conflict between tgr read and input capture section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 553 of 1102 rej09b0365-0100 12.10.9 conflict between tg r write and input capture if the input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the wr ite to tgr is not performed. figure 12.52 shows the timing in this case. tcnt p input capture signal address tgr address write t 1 t 2 tgr write cycle m m tgr figure 12.52 conflict between tgr write and input capture section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 554 of 1102 rej09b0365-0100 12.10.10 conflict between buffer re gister write and input capture if the input capture signal is generated in the t2 st ate of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 12.53 shows the timing in this case. tcnt p input capture signal address buffer register address write t 1 t 2 buffer register write cycle n n tgr buffer register m m figure 12.53 conflict between bu ffer register write and input capture section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 555 of 1102 rej09b0365-0100 12.10.11 conflict between overflow/ underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 12.54 shows the operation timing when a tgr compare match is sp ecified as the clearing source, and h'ffff is set in tgr. counter clear signal h'0000 p tcnt input clock tcnt tgf flag tcfv flag h'ffff disabled figure 12.54 conflict between overflow and coun ter clearing 12.10.12 conflict between tcnt write and overflow/underflow if an overflow/underflow occurs due to incremen t/decrement in the t2 state of a tcnt write cycle, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 12.55 shows the operation timing when there is conflict between tcnt write and overflow. p tcnt h'ffff tcfv flag address write tcnt address m tcnt write data t 1 t 2 tgr write cycle figure 12.55 conflict between tcnt write and overflow section 12 16-bit timer pulse unit (tpu) rev. 1.00 sep. 13, 2007 page 556 of 1102 rej09b0365-0100 12.10.13 multiplexing of i/o pins in this lsi, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. 12.10.14 ppg1 setting when tpu1 pin is used when the tpu1 pin is used, the nder bit of the ppg1 pin multiplexed with the tpu1 pin should be cleared to halt the output. for details, see section 11, i/o ports. 12.10.15 interrupts and module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc and dmac activati on sources. interrupts should therefore be disabled before entering module stop mode. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 557 of 1102 rej09b0365-0100 section 13 programmable pulse generator (ppg) the programmable pulse generator (ppg) provides pulse outputs by using the 16-bit timer pulse unit (tpu) as a time base. the ppg pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. figures 13.1 and 13.2 show a block diagram of the ppg. 13.1 features ? 32-bit output data ? four output groups ? selectable output trigger signals ? non-overlapping mode ? can operate together with the data transfer controller (dtc) and dma controller (dmac) ? inverted output can be set ? module stop state specifiable table 13.1 list of ppg functions function ppg0 ppg1 compare match possible not possible tpu0 input capture possible not possible compare match not possible possible ppg output trigger tpu1 input capture not possible not possible non-overlapping mode possible possible dtc possible possible output data transfer dmac possible possible inverted output possible possible section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 558 of 1102 rej09b0365-0100 compare match signals po15 po14 po13 po12 po11 po10 po9 po8 po7 po6 po5 po4 po3 po2 po1 po0 [legend] pmr: pcr: nderh: nderl: ppg output mode register ppg output control register next data enable register h next data enable register l ndrh: ndrl: podrh: podrl: next data register h next data register l output data register h output data register l internal data bus pulse output pins, group 3 pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 podrh podrl ndrh ndrl control logic nderh pmr nderl pcr figure 13.1 block diagram of ppg (unit 0) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 559 of 1102 rej09b0365-0100 compare match signals po31 po30 po29 po28 po27 po26 po25 po24 po23 po22 po21 po20 po19 po18 po17 po16 [legend] pmr_1: pcr_1: nderh_1: nderl_1: ppg output mode register_1 ppg output control register_1 next data enable register h_1 next data enable register l_1 ndrh_1: ndrl_1: podrh_1: podrl_1: next data register h_1 next data register l_1 output data register h_1 output data register l_1 internal data bus pulse output pins, group 7 pulse output pins, group 6 pulse output pins, group 5 pulse output pins, group 4 podrh_1 podrl_1 ndrh_1 ndrl_1 control logic nderh_1 pmr_1 nderl_1 pcr_1 figure 13.2 block diagram of ppg (unit 1) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 560 of 1102 rej09b0365-0100 13.2 input/output pins table 13.2 shows the ppg pin configuration. table 13.2 pin configuration unit pin name i/o function po0 output po1 output po2 output po3 output group 0 pulse output po4 output po5 output po6 output po7 output group 1 pulse output po8 output po9 output po10 output po11 output group 2 pulse output po12 output po13 output po14 output 0 po15 output group 3 pulse output section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 561 of 1102 rej09b0365-0100 unit pin name i/o function po16 output po17 output po18 output po18 output group 4 pulse output po20 output po21 output po22 output po23 output group 5 pulse output po24 output po25 output po26 output po27 output group 6 pulse output po28 output po29 output po30 output 1 po31 output group 7 pulse output section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 562 of 1102 rej09b0365-0100 13.3 register descriptions the ppg has the following registers. unit 0: ? next data enable register h (nderh) ? next data enable register l (nderl) ? output data register h (podrh) ? output data register l (podrl) ? next data register h (ndrh) ? next data register l (ndrl) ? ppg output control register (pcr) ? ppg output mode register (pmr) unit 1: ? next data enable register h_1 (nderh_1) ? next data enable register l_1 (nderl_1) ? output data register h_1 (podrh_1) ? output data register l_1 (podrl_1) ? next data register h_1 (ndrh_1) ? next data register l_1 (ndrl_1) ? ppg output control register_1 (pcr_1) ? ppg output mode register_1 (pmr_1) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 563 of 1102 rej09b0365-0100 13.3.1 next data enable registers h, l (nderh, nderl) nderh and nderl enable/disable pulse output on a bit-by-bit basis. ? nderh 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w 0 nder8 0 r/w bit bit name initial value r/w ? nderl 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w 0 nder0 0 r/w bit bit name initial value r/w section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 564 of 1102 rej09b0365-0100 ? nderh bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 15 to 8 when a bit is set to 1, the value in the corresponding ndrh bit is transferred to the podrh bit by the selected output trigger. values are not transferred from ndrh to podrh for cleared bits. ? nderl bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 7 to 0 when a bit is set to 1, the value in the corresponding ndrl bit is transferred to the podrl bit by the selected output trigger. values are not transferred from ndrl to podrl for cleared bits. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 565 of 1102 rej09b0365-0100 ? nderh_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder31 nder30 nder29 nder28 nder27 nder26 nder25 nder24 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 31 to 24 when a bit is set to 1, the value in the corresponding ndrh_1 bit is transferred to the podrh_1 bit by the selected output trigger. values are not transferred from ndrh_1 to podrh_1 for cleared bits. ? nderl_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder23 nder22 nder21 nder20 nder19 nder18 nder17 nder16 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 23 to 16 when a bit is set to 1, the value in the corresponding ndrl_1 bit is transferred to the podrl_1 bit by the selected output trigger. values are not transferred from ndrl_1 to podrl_1 for cleared bits. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 566 of 1102 rej09b0365-0100 13.3.2 output data regist ers h, l (podrh, podrl) podrh and podrl store output data for use in pulse output. a bit that has been set for pulse output by nder is read-only and cannot be modified. ? podrh 7 pod15 0 r/w 6 pod14 0 r/w 5 pod13 0 r/w 4 pod12 0 r/w 3 pod11 0 r/w 2 pod10 0 r/w 1 pod9 0 r/w 0 pod8 0 r/w bit bit name initial value r/w ? podrl 7 pod7 0 r/w 6 pod6 0 r/w 5 pod5 0 r/w 4 pod4 0 r/w 3 pod3 0 r/w 2 pod2 0 r/w 1 pod1 0 r/w 0 pod0 0 r/w bit bit name initial value r/w ? podrh bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 15 to 8 for bits which have been set to pulse output by nderh, the output trigger transfers ndrh values to this register during ppg operation. while nderh is set to 1, the cpu cannot write to this register. while nderh is cleared, the initial output value of the pulse can be set. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 567 of 1102 rej09b0365-0100 ? podrl bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 7 to 0 for bits which have been set to pulse output by nderl, the output trigger transfers ndrl values to this register during ppg operation. while nderl is set to 1, the cpu cannot write to this register. while nderl is cleared, the initial output value of the pulse can be set. ? podrh_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod31 pod30 pod29 pod28 pod27 pod26 pod25 pod24 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 31 to 24 for bits which have been set to pulse output by nderh_1, the output trigger transfers ndrh_1 values to this register during ppg operation. while nderh_1 is set to 1, the cpu cannot write to this register. while nderh_1 is cleared, the initial output value of the pulse can be set. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 568 of 1102 rej09b0365-0100 ? podrl_1 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod23 pod22 pod21 pod20 pod19 pod18 pod17 pod16 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 23 to 16 for bits which have been set to pulse output by nderl_1, the output trigger transfers ndrl_1 values to this register during ppg operation. while nderl_1 is set to 1, the cpu cannot write to this register. while nderl_1 is cleared, the initial output value of the pulse can be set. 13.3.3 next data registers h, l (ndrh, ndrl) ndrh and ndrl store the next data for pulse output. the ndr addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. ? ndrh bit bit name initial value r/w 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w ? ndrl bit bit name initial value r/w 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 569 of 1102 rej09b0365-0100 ? ndrh if pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 15 to 8 the register contents ar e transferred to the corresponding podrh bits by t he output trigger specified with pcr. if pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr15 ndr14 ndr13 ndr12 0 0 0 0 r/w r/w r/w r/w next data register 15 to 12 the register contents ar e transferred to the corresponding podrh bits by t he output trigger specified with pcr. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr11 ndr10 ndr9 ndr8 0 0 0 0 r/w r/w r/w r/w next data register 11 to 8 the register contents ar e transferred to the corresponding podrh bits by t he output trigger specified with pcr. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 570 of 1102 rej09b0365-0100 ? ndrl if pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 7 to 0 the register contents ar e transferred to the corresponding podrl bits by the output trigger specified with pcr. if pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr7 ndr6 ndr5 ndr4 0 0 0 0 r/w r/w r/w r/w next data register 7 to 4 the register contents ar e transferred to the corresponding podrl bits by the output trigger specified with pcr. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr3 ndr2 ndr1 ndr0 0 0 0 0 r/w r/w r/w r/w next data register 3 to 0 the register contents ar e transferred to the corresponding podrl bits by the output trigger specified with pcr. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 571 of 1102 rej09b0365-0100 ? ndrh_1 if pulse output groups 6 and 7 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr31 ndr30 ndr29 ndr28 ndr27 ndr26 ndr25 ndr24 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 31 to 24 the register contents ar e transferred to the corresponding podrh_1 bits by the output trigger specified with pcr_1. if pulse output groups 6 and 7 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr31 ndr30 ndr29 ndr28 0 0 0 0 r/w r/w r/w r/w next data register 31 to 28 the register contents ar e transferred to the corresponding podrh_1 bits by the output trigger specified with pcr_1. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr27 ndr26 ndr25 ndr24 0 0 0 0 r/w r/w r/w r/w next data register 27 to 24 the register contents ar e transferred to the corresponding podrh_1 bits by the output trigger specified with pcr_1. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 572 of 1102 rej09b0365-0100 ? ndrl_1 if pulse output groups 4 and 5 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr23 ndr22 ndr21 ndr20 ndr19 ndr18 ndr17 ndr16 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 23 to 16 the register contents ar e transferred to the corresponding podrl_1 bits by the output trigger specified with pcr_1. if pulse output groups 4 and 5 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr23 ndr22 ndr21 ndr20 0 0 0 0 r/w r/w r/w r/w next data register 23 to 20 the register contents ar e transferred to the corresponding podrl_1 bits by the output trigger specified with pcr_1. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr19 ndr18 ndr17 ndr16 0 0 0 0 r/w r/w r/w r/w next data register 19 to 16 the register contents ar e transferred to the corresponding podrl_1 bits by the output trigger specified with pcr_1. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 573 of 1102 rej09b0365-0100 13.3.4 ppg output control register (pcr) pcr selects output trigger signals on a group-by-group basis. for details on output trigger selection, refer to section 13.3.5, ppg output mode register (pmr). 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w 0 g0cms0 1 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 g3cms1 g3cms0 1 1 r/w r/w group 3 compare match select 1 and 0 these bits select output tri gger of pulse output group 3. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 5 4 g2cms1 g2cms0 1 1 r/w r/w group 2 compare match select 1 and 0 these bits select output tri gger of pulse output group 2. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 3 2 g1cms1 g1cms0 1 1 r/w r/w group 1 compare match select 1 and 0 these bits select output tri gger of pulse output group 1. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 1 0 g0cms1 g0cms0 1 1 r/w r/w group 0 compare match select 1 and 0 these bits select output tri gger of pulse output group 0. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 574 of 1102 rej09b0365-0100 ? pcr_1 bit bit name initial value r/w description 7 6 g3cms1 g3cms0 1 1 r/w r/w group 7 compare match select 1 and 0 these bits select output tri gger of pulse output group 7. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 5 4 g2cms1 g2cms0 1 1 r/w r/w group 6 compare match select 1 and 0 these bits select output tri gger of pulse output group 6. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 3 2 g1cms1 g1cms0 1 1 r/w r/w group 5 compare match select 1 and 0 these bits select output tri gger of pulse output group 5. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 1 0 g0cms1 g0cms0 1 1 r/w r/w group 4 compare match select 1 and 0 these bits select output tri gger of pulse output group 4. 00: compare match in tpu channel 6 01: compare match in tpu channel 7 10: compare match in tpu channel 8 11: compare match in tpu channel 9 section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 575 of 1102 rej09b0365-0100 13.3.5 ppg output mo de register (pmr) pmr selects the pulse output mode of the ppg for each group. if inverted output is selected, a low-level pulse is output when podrh is 1 and a high-level pulse is output when podrh is 0. if non-overlapping operation is selected, ppg updates its output values at compare match a or b of the tpu that becomes the output trigger. for details, refer to section 13.4.4, non-overlapping pulse output. 7 g3inv 1 r/w 6 g2inv 1 r/w 5 g1inv 1 r/w 4 g0inv 1 r/w 3 g3nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w 0 g0nov 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 g3inv 1 r/w group 3 inversion selects direct output or inve rted output for pulse output group 3. 0: inverted output 1: direct output 6 g2inv 1 r/w group 2 inversion selects direct output or inve rted output for pulse output group 2. 0: inverted output 1: direct output 5 g1inv 1 r/w group 1 inversion selects direct output or inve rted output for pulse output group 1. 0: inverted output 1: direct output 4 g0inv 1 r/w group 0 inversion selects direct output or inve rted output for pulse output group 0. 0: inverted output 1: direct output section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 576 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 g3nov 0 r/w group 3 non-overlap selects normal or non-overlapping operation for pulse output group 3. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values updated at compare match a or b in the selected tpu channel) 2 g2nov 0 r/w group 2 non-overlap selects normal or non-overlapping operation for pulse output group 2. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values updated at compare match a or b in the selected tpu channel) 1 g1nov 0 r/w group 1 non-overlap selects normal or non-overlapping operation for pulse output group 1. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values updated at compare match a or b in the selected tpu channel) 0 g0nov 0 r/w group 0 non-overlap selects normal or non-overlapping operation for pulse output group 0. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values updated at compare match a or b in the selected tpu channel) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 577 of 1102 rej09b0365-0100 ? pmr_1 bit bit name initial value r/w description 7 g3inv 1 r/w group 7 inversion selects direct output or inve rted output for pulse output group 7. 0: inverted output 1: direct output 6 g2inv 1 r/w group 6 inversion selects direct output or inve rted output for pulse output group 6. 0: inverted output 1: direct output 5 g1inv 1 r/w group 5 inversion selects direct output or inve rted output for pulse output group 5. 0: inverted output 1: direct output 4 g0inv 1 r/w group 4 inversion selects direct output or inve rted output for pulse output group 4. 0: inverted output 1: direct output section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 578 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 g3nov 0 r/w group 7 non-overlap selects normal or non-overlapping operation for pulse output group 7. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) 2 g2nov 0 r/w group 6 non-overlap selects normal or non-overlapping operation for pulse output group 6. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) 1 g1nov 0 r/w group 5 non-overlap selects normal or non-overlapping operation for pulse output group 5. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) 0 g0nov 0 r/w group 4 non-overlap selects normal or non-overlapping operation for pulse output group 4. 0: normal operation (output values updated by compare match a on the selected tpu channel) 1: non-overlapping operation (output values updated by compare match a or b on the selected tpu channel) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 579 of 1102 rej09b0365-0100 13.4 operation figure 13.3 shows a schematic diagram of the ppg. ppg pulse output is enabled when the corresponding bits in nder are set to 1. an initial output value is determined by its corresponding podr initial setting. when the compare match event specified by pcr occurs, the corresponding ndr bit contents are transferred to podr to update the output values. sequential output of data of up to 16 bits is possible by writing new output data to ndr before the next compare match. output trigger signal pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd figure 13.3 schematic diagram of ppg 13.4.1 output timing if pulse output is enabled, the ndr contents ar e transferred to podr and output when the specified compare match event occurs. figure 13.4 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. tcnt n n + 1 p tgra n compare match a signal ndrh mn podrh po8 to po15 n m n figure 13.4 timing of transfer and output of ndr contents (example) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 580 of 1102 rej09b0365-0100 13.4.2 sample setup procedure for normal pulse output figures 13.5 and 13.6 show a sample procedure for setting up normal pulse output. ? sample setup procedure for ppg0 select tgr functions [1] set tgra value set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data normal ppg output no yes tpu0 setup ppg0 setup tpu0 setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior in tpu0 to make tgra an output compare register (with output disabled). [2] set the ppg output trigger cycle. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output trigger in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next figure 13.5 setup procedure fo r normal pulse output (ppg0) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 581 of 1102 rej09b0365-0100 ? sample setup procedure for ppg1 select tgr functions [1] set tgra value set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data normal ppg output no yes tpu1 setup ppg1 setup tpu1 setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior in tpu1 to make tgra an output compare register (toggle output). [2] set the ppg output trigger cycle. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output trigger in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next output values in ndr. figure 13.6 setup procedure fo r normal pulse output (ppg1) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 582 of 1102 rej09b0365-0100 13.4.3 example of normal pulse output (example of 5-phase pulse output) figure 13.7 shows an example in which pulse output is used for cyclic 5-phase pulse output. tcnt value tcnt tgra h'0000 ndrh 00 80 c0 40 60 20 30 10 18 08 88 podrh po15 po14 po13 po12 po11 time compare match c0 80 c0 80 40 60 20 30 10 18 08 88 80 c0 40 figure 13.7 normal pulse output example (5-phase pulse output) 1. set up tgra in tpu which is used as the outp ut trigger to be an output compare register. set a cycle in tgra so the counter will be cleared by compare match a. set the tgiea bit in tier to 1 to enable the compare match/input capture a (tgia) interrupt. 2. write h'f8 to nderh, and set bits g3cms1, g3cms0, g2cms1, and g2cms0 in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. write output data h'80 in ndrh. 3. the timer counter in the tpu channel starts. when compare match a occurs, the ndrh contents are transferred to podrh and output. the tgia interrupt handling routine writes the next output data (h'c0) in ndrh. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing h'40, h'60, h'20, h'30, h'10, h'18, h'08, h'88... at successive tgia interrupts. if the dtc or dmac is set for activation by the tgia interrupt, pulse output can be obtained without imposing a load on the cpu. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 583 of 1102 rej09b0365-0100 13.4.4 non-overlapping pulse output during non-overlapping operation, transfer from ndr to podr is performed as follows: ? at compare match a, the ndr bits are always transferred to podr. ? at compare match b, the ndr bits are transferre d only if their value is 0. the ndr bits are not transferred if their value is 1. figure 13.8 illustrates the non-overlapping pulse output operation. compare match a compare match b pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd figure 13.8 non-overl apping pulse output therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. the ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlapping margin). this can be accomplished by having the tgia interrupt handling routine write the next data in ndr, or by having the tgia interrupt activate the dtc or dmac. note, however, that the next data must be written before the next compare match b occurs. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 584 of 1102 rej09b0365-0100 figure 13.9 shows the timing of this operation. 0/1 output 0 output 0/1 output 0 output do not write to ndr here write to ndr here compare match a compare match b ndr podr do not write to ndr here write to ndr here write to ndr write to ndr figure 13.9 non-overlapping operation and ndr write timing section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 585 of 1102 rej09b0365-0100 13.4.5 sample setup procedure fo r non-overlapping pulse output figures 13.10 and 13.11 show a sample procedure for setting up non-overlapping pulse output. ? sample setup procedure for ppg0 select tgr functions [1] set tgr values set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data compare match a? no yes tpu0 setup ppg0 setup tpu0 setup non-overlapping pulse output set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior in tpu0 to make tgra and tgrb output compare registers (with output disabled). [2] set the pulse output trigger cycle in tgrb and the non-overlapping margin in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output trigger in pcr. [8] in pmr, select the groups that will operate in non-overlapping mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 13.10 setup procedure for no n-overlapping pulse output (ppg0) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 586 of 1102 rej09b0365-0100 ? sample setup procedure for ppg1 select tgr functions [1] set tgr values set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data compare match a? no yes tpu1 setup ppg1 setup tpu1 setup non-overlapping pulse output set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior in tpu1 to make tgra and tgrb output compare registers (toggle output). [2] set the pulse output trigger cycle in tgrb and the non-overlapping margin in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the bits in nder for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output trigger in pcr. [8] in pmr, select the groups that will operate in non-overlapping mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 13.11 setup procedure for no n-overlapping pulse output (ppg1) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 587 of 1102 rej09b0365-0100 13.4.6 example of non-overlapping pulse output (example of 4-phase complementary non-overlapping pulse output) figure 13.12 shows an example in which pulse output is used for 4-phase complementary non- overlapping pulse output. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrh po15 po14 po13 po12 po11 po10 po9 po8 time non-overlapping margin figure 13.12 non-overlappi ng pulse output example (4-phase complementary) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 588 of 1102 rej09b0365-0100 1. set up the tpu channel to be used as the output trigger channel so that tgra and tgrb are output compare registers. set the cycle in tgrb and the non-overlapping margin in tgra, and set the counter to be cleared by compare match b. set the tgiea bit in tier to 1 to enable the tgia interrupt. 2. write h'ff to nderh, and set bits g3cms1, g3cms0, g2cms1, and g2cms0 in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. set bits g3nov and g2nov in pmr to 1 to select non-overlapping pulse output. write output data h'95 to ndrh. 3. the timer counter in the tpu channel starts. when a compare match with tgrb occurs, outputs change from 1 to 0. when a compare match with tgra occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in tgra). the tgia interrupt handling routine writes the next output data (h'65) to ndrh. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing h'59, h'56, h'95... at succes sive tgia interrupts. if the dtc or dmac is set for activation by a tgia interrupt, pulse can be output without imposing a load on the cpu. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 589 of 1102 rej09b0365-0100 13.4.7 inverted pulse output if the g3inv, g2inv, g1inv, and g0inv bits in pmr are cleared to 0, values that are the inverse of the podr contents can be output. figure 13.13 shows the outputs when the g3inv an d g2inv bits are cleared to 0, in addition to the settings of figure 13.12. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrl po15 po14 po13 po12 po11 po10 po9 po8 time figure 13.13 inverted pulse output (example) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 590 of 1102 rej09b0365-0100 13.4.8 pulse output tri ggered by input capture pulse output of ppg0 can be triggered by tpu0 input capture as well as by compare match. if tgra functions as an input capture register in the tpu0 channel selected by pcr, pulse output will be triggered by the input capture signal. figure 13.14 shows the timing of this output. ppg1 cannot be used to trigger pulse output by input capturer. p n mn tioc pin input capture signal ndr podr mn po figure 13.14 pulse output tri ggered by input capture (example) section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 591 of 1102 rej09b0365-0100 13.5 usage notes 13.5.1 module stop state setting ppg operation can be disabled or enabled using the module stop control register. the initial value is for ppg operation to be halted. register access is enabled by clearing the module stop state. for details, refer to section 24, power-down modes. 13.5.2 operation of pulse output pins pins po0 to po15 are also used for other peripher al functions such as th e tpu. when output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. note, however, that data tr ansfer from ndr bits to podr bits takes place, regardless of the usage of the pins. pin functions should be changed only under conditions in which the output trigger event will not occur. 13.5.3 tpu setting when ppg1 is in use when using ppg1, output toggling on compare-matches must be specified in the tior register of the tpu that acts as the activation source and out put must be selected as the ppg1 function. section 13 programmable pulse generator (ppg) rev. 1.00 sep. 13, 2007 page 592 of 1102 rej09b0365-0100 section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 593 of 1102 rej09b0365-0100 section 14 8-bit timers (tmr) this lsi has four units (unit 0 to unit 3) of an on-chip 8-bit timer module that comprise two 8-bit counter channels, totaling eight channels. the 8-bi t timer module can be us ed to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers. figures 14.1 to 14.4 show block diagrams of the 8-bit timer module (unit 0 to unit 3). this section describes unit 0 (channels 0 and 1) and unit 2 (channels 4 and 5), both of which have the same functions. unit 2 and unit 3 can generate baud rate clock for sci and have the same functions. 14.1 features ? selection of seven clock sources the counters can be driven by one of six internal clock signals (p /2, p /8, p /32, p /64, p /1024, or p /8192) or an external clock input (only internal clock available in units 2 and 3: p , p /2, p /8, p /32, p /64, p /1024, and p /8192). ? selection of three ways to clear the counters the counters can be cleared on compare match a or b, or by an external reset signal. (this is available only in unit 0 and unit 1.) ? timer output control by a combination of two compare match signals the timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to output pulses with a desired duty cycle or pwm output. ? cascading of two channels operation as a 16-bit timer is possible, using tmr_0 for the upper 8 bits and tmr_1 for the lower 8 bits (16-bit count mode). tmr_1 can be used to count tmr_0 compare matches (compare match count mode). ? three interrupt sources compare match a, compare match b, and overflow interrupts can be requested independently. (this is available only in unit 0 and unit 1.) ? generation of trigger to start a/d converter conversion (available in unit 0 and unit 1 only) ? capable of generating baud rate clock for sci_5 and sci_6. (this is available only in unit 2 and unit 3). for details, see section 16, seri al communications inte rface (sci, irda, crc). ? module stop state specifiable section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 594 of 1102 rej09b0365-0100 cmia0 cmia1 cmib0 cmib1 ovi0 ovi1 tmo0 tmo1 tmci0 tmci1 tmri0 tmri1 tcora_1: tcnt_1: tcorb_1: tcsr_1: tcr_1: tccr_1: tcora_0: tcnt_0: tcorb_0: tcsr_0: tcr_0: tccr_0: p /2 p /8 p /32 p /64 p /1024 p /8192 counter clock 1 counter clock 0 compare match a1 compare match a0 overflow 1 overflow 0 counter clear 0 counter clear 1 compare match b1 compare match b0 comparator a_0 comparator a_1 tcora_0 tcorb_0 tcsr_0 tccr_0 tcora_1 tcnt_1 tcorb_1 tcsr_1 tccr_1 tcr_0 tcr_1 tcnt_0 comparator b_0 comparator b_1 a/d conversion start request signal * internal bus time constant register a_1 timer counter_1 time constant register b_1 timer control/status register_1 timer control register_1 timer counter control register_1 time constant register a_0 timer counter_0 time constant register b_0 timer control/status register_0 timer control register_0 timer counter control register_0 interrupt signals internal clocks clock select control logic external clocks [legend] channel 1 (tmr_1) channel 0 (tmr_0) note: * for the corresponding a/d converter channels, see section 18, a/d converter. figure 14.1 block diagram of 8-bit timer module (unit 0) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 595 of 1102 rej09b0365-0100 cmia2 cmia3 cmib2 cmib3 ovi2 ovi3 tmo2 tmo3 tmci2 tmci3 tmri2 tmri3 tcora_3: tcnt_3: tcorb_3: tcsr_3: tcr_3: tccr_3: tcora_2: tcnt_2: tcorb_2: tcsr_2: tcr_2: tccr_2: p /2 p /8 p /32 p /64 p /1024 p /8192 counter clock 3 counter clock 2 compare match a3 compare match a2 overflow 3 overflow 2 counter clear 2 counter clear 3 compare match b3 compare match b2 comparator a_2 comparator a_3 tcora_2 tcorb_2 tcsr_2 tccr_2 tcora_3 tcnt_3 tcorb_3 tcsr_3 tccr_3 tcr_2 tcr_3 tcnt_2 comparator b_2 comparator b_3 a/d conversion start request signal * internal bus time constant register a_3 timer counter_3 time constant register b_3 timer control/status register_3 timer control register_3 timer counter control register_3 time constant register a_2 timer counter_2 time constant register b_2 timer control/status register_2 timer control register_2 timer counter control register_2 interrupt signals internal clocks clock select control logic external clocks [legend] channel 3 (tmr_3) channel 2 (tmr_2) note: * for the corresponding a/d converter channels, see section 18, a/d converter. figure 14.2 block diagram of 8-bit timer module (unit 1) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 596 of 1102 rej09b0365-0100 cmia4 cmib4 cmia5 cmib5 tcora_5: tcnt_5: tcorb_5: tcsr_5: tcr_5: tccr_5: tcora_4: tcnt_4: tcorb_4: tcsr_4: tcr_4: tccr_4: p p /2 p /8 p /32 p /64 p /1024 p /8192 counter clock 5 counter clock 4 compare match a5 compare match a4 overflow 5 overflow 4 tmo4 tmo5 to sci_5 counter clear 4 counter clear5 compare match b5 compare match b4 comparator a_4 comparator a_5 tcora_4 tcorb_4 tcsr_4 tccr_4 tcora_5 tcnt_5 tcorb_5 tcsr_5 tccr_5 cmi4 cmi5 tcr_4 tcr_5 tcnt_4 comparator b_4 comparator b_5 internal bus time constant register a_5 timer counter_5 time constant register b_5 timer control/status register_5 timer control register_5 timer counter control register_5 time constant register a_4 timer counter_4 time constant register b_4 timer control/status register_4 timer control register_4 timer counter control register_4 interrupt signals internal clocks clock select control logic [legend] channel 5 (tmr_5) channel 4 (tmr_4) note: * for the corresponding a/d converter channels, see section 18, a/d converter. a/d conversion start request signal * figure 14.3 block diagram of 8-bit timer module (unit 2) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 597 of 1102 rej09b0365-0100 tcora_7: tcnt_7: tcorb_7: tcsr_7: tcr_7: tccr_7: tcora_6: tcnt_6: tcorb_6: tcsr_6: tcr_6: tccr_6: p p /2 p /8 p /32 p /64 p /1024 p /8192 counter clock 7 counter clock 6 compare match a7 compare match a6 overflow 7 overflow 6 counter clear 6 counter clear 7 compare match b7 compare match b6 comparator a_6 comparator a_7 tcora_6 tcorb_6 tcsr_6 tccr_6 tcora_7 tcnt_7 tcorb_7 tcsr_7 tccr_7 tcr_6 tcr_7 tcnt_6 comparator b_6 comparator b_7 internal bus time constant register a_7 timer counter_7 time constant register b_7 timer control/status register_7 timer control register_7 timer counter control register_7 time constant register a_6 timer counter_6 time constant register b_6 timer control/status register_6 timer control register_6 timer counter control register_6 interrupt signals internal clocks clock select control logic [legend] cmia6 cmib6 cmia7 cmib7 cmi6 cmi7 channel 7 (tmr_7) channel 6 (tmr_6) tmo6 tmo7 to sci_6 a/d conversion start request signal * note: * for the corresponding a/d converter channels, see section 18, a/d converter. figure 14.4 block diagram of 8-bit timer module (unit 3) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 598 of 1102 rej09b0365-0100 14.2 input/output pins table 14.1 shows the pin configuration of the tmr. table 14.1 pin configuration unit channel name symbol i/o function 0 0 timer output pin tmo0 output outputs compare match timer clock input pin tmci0 input inputs external clock for counter timer reset input pin tmri0 input inputs external reset to counter 1 timer output pin tmo1 output outputs compare match timer clock input pin tmci1 input inputs external clock for counter timer reset input pin tmri1 input inputs external reset to counter 1 2 timer output pin tmo2 output outputs compare match timer clock input pin tmci2 input inputs external clock for counter timer reset input pin tmri2 input inputs external reset to counter 3 timer output pin tmo3 output outputs compare match timer clock input pin tmci3 input inputs external clock for counter timer reset input pin tmri3 input inputs external reset to counter 2 4 ? ? ? ? 5 3 6 7 section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 599 of 1102 rej09b0365-0100 14.3 register descriptions the tmr has the following registers. unit 0: ? channel 0 (tmr_0): ? timer counter_0 (tcnt_0) ? time constant register a_0 (tcora_0) ? time constant register b_0 (tcorb_0) ? timer control register_0 (tcr_0) ? timer counter control register_0 (tccr_0) ? timer control/status register_0 (tcsr_0) ? channel 1 (tmr_1): ? timer counter_1 (tcnt_1) ? time constant register a_1 (tcora_1) ? time constant register b_1 (tcorb_1) ? timer control register_1 (tcr_1) ? timer counter control register_1 (tccr_1) ? timer control/status register_1 (tcsr_1) unit 1: ? channel 2 (tmr_2): ? timer counter_2 (tcnt_2) ? time constant register a_2 (tcora_2) ? time constant register b_2 (tcorb_2) ? timer control register_2 (tcr_2) ? timer counter control register_2 (tccr_2) ? timer control/status register_2 (tcsr_2) ? channel 3 (tmr_3): ? timer counter_3 (tcnt_3) ? time constant register a_3 (tcora_3) ? time constant register b_3 (tcorb_3) ? timer control register_3 (tcr_3) ? timer counter control register_3 (tccr_3) ? timer control/status register_3 (tcsr_3) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 600 of 1102 rej09b0365-0100 unit 2: ? channel 4 (tmr_4): ? timer counter_4 (tcnt_4) ? time constant register a_4 (tcora_4) ? time constant register b_4 (tcorb_4) ? timer control register_4 (tcr_4) ? timer counter control register_4 (tccr_4) ? timer control/status register_4 (tcsr_4) ? channel 5 (tmr_5): ? timer counter_5 (tcnt_5) ? time constant register a_5 (tcora_5) ? time constant register b_5 (tcorb_5) ? timer control register_5 (tcr_5) ? timer counter control register_5 (tccr_5) ? timer control/status register_5 (tcsr_5) unit 3: ? channel 6 (tmr_6): ? timer counter_6 (tcnt_6) ? time constant register a_6 (tcora_6) ? time constant register b_6 (tcorb_6) ? timer control register_6 (tcr_6) ? timer counter control register_6 (tccr_6) ? timer control/status register_6 (tcsr_6) ? channel 7 (tmr_7): ? timer counter_7 (tcnt_7) ? time constant register a_7 (tcora_7) ? time constant register b_7 (tcorb_7) ? timer control register_7 (tcr_7) ? timer counter control register_7 (tccr_7) ? timer control/status register_7 (tcsr_7) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 601 of 1102 rej09b0365-0100 14.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tcnt_0 and tcnt_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. bits cks2 to cks0 in tcr and bits icks1 and icks0 in tccr are used to select a clock. tcnt can be cleared by an external reset input signal, compare match a signa l, or compare match b signal. which signal to be used for clearing is selected by bits cclr1 and cclr0 in tcr. when tcnt overflows from h'ff to h'00, bit ovf in tcsr is set to 1. tcnt is initialized to h'00. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt_0 tcnt_1 bit bit name initial value r/w 14.3.2 time constant register a (tcora) tcora is an 8-bit readable/writable register. tcora_0 and tcora_1 comprise a single 16-bit register so they can be accessed together by a wo rd transfer inst ruction. the value in tcora is continually compared with the value in tcnt. when a match is detected, the corresponding cmfa flag in tcsr is set to 1. note however that comparison is disabled during the t2 state of a tcora write cycle. the timer output from the tmo pin can be freely controlled by this compare match signal (compare match a) and the settings of bits os1 and os0 in tcsr. tcora is initialized to h'ff. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora_0 tcora_1 bit bit name initial value r/w section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 602 of 1102 rej09b0365-0100 14.3.3 time constant register b (tcorb) tcorb is an 8-bit readable/writable register. tcorb_0 and tcorb_1 comprise a single 16-bit register so they can be accessed together by a wo rd transfer inst ruction. tcorb is continually compared with the value in tcnt . when a match is detected, th e corresponding cmfb flag in tcsr is set to 1. note however that comparison is disabled during the t2 state of a tcorb write cycle. the timer output from the tmo pin can be freely controlled by this compare match signal (compare match b) and the settings of bits os3 and os2 in tcsr. tcorb is initialized to h'ff. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb_0 tcorb_1 bit bit name initial value r/w 14.3.4 timer control register (tcr) tcr selects the tcnt clock source and the cond ition for clearing tcnt, and enables/disables interrupt requests. 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b selects whether cmfb interrupt requests (cmib) are enabled or disabled when the cmfb flag in tcsr is set to 1. * 2 0: cmfb interrupt requests (cmib) are disabled 1: cmfb interrupt requests (cmib) are enabled section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 603 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 cmiea 0 r/w compare match interrupt enable a selects whether cmfa interrupt requests (cmia) are enabled or disabled when the cmfa flag in tcsr is set to 1. * 2 0: cmfa interrupt requests (cmia) are disabled 1: cmfa interrupt requests (cmia) are enabled 5 ovie 0 r/w timer overflow interrupt enable * 3 selects whether ovf interrupt requests (ovi) are enabled or disabled when the ovf flag in tcsr is set to 1. 0: ovf interrupt requests (ovi) are disabled 1: ovf interrupt requests (ovi) are enabled 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 * 1 these bits select the method by which tcnt is cleared. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared at rising edge (tmris in tccr is cleared to 0) of the external reset input or when the external reset input is high (tmris in tccr is set to 1) * 3 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 * 1 these bits select the clock input to tcnt and count condition. see table 14.2. notes: 1. to use an external reset or external clock, the ddr and icr bits in the corresponding pin should be set to 0 and 1, respectively . for details, see section 11, i/o ports. 2. in unit 2 and unit 3, one interrupt signal is used for cmieb or cmiea. for details, see section 14.7, interrupt sources. 3. available only in unit 0 and unit 1. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 604 of 1102 rej09b0365-0100 14.3.5 timer counter co ntrol register (tccr) tccr selects the tcnt internal clock source and controls external reset input. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 tmris 0 r/w 2 ? 0 r 1 icks1 0 r/w 0 icks0 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. it should not be set to 0. 3 tmris 0 r/w timer reset input select * selects an external reset input when the cclr1 and cclr0 bits in tcr are b'11. 0: cleared at rising edge of the external reset 1: cleared when the external reset is high 2 ? 0 r reserved this bit is always read as 0. it should not be set to 0. 1 0 icks1 icks0 0 0 r/w r/w internal clock select 1 and 0 these bits in combination with bits cks2 to cks0 in tcr select the internal clock. see table 14.2. note: * available only in unit 0 and unit 1. the writ e value should always be 0 in unit 2 and unit 3. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 605 of 1102 rej09b0365-0100 table 14.2 clock input to tcnt and count condition (unit 0) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description tmr_0 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_1 overflow signal * 1 . tmr_1 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_0 compare match a * 1 . all 1 0 1 ? ? uses external clock. counts at rising edge * 2 . 1 1 0 ? ? uses external clock. counts at falling edge * 2 . 1 1 1 ? ? uses external clock. counts at both rising and falling edges * 2 . notes: 1. if the clock input of channel 0 is the t cnt_1 overflow signal and that of channel 1 is the tcnt_0 compare match signal, no incrementi ng clock is generated. do not use this setting. 2. to use the external clock, the ddr and i cr bits in the corresponding pin should be set to 0 and 1, respectively. for de tails, see section 11, i/o ports. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 606 of 1102 rej09b0365-0100 table 14.3 clock input to tcnt and count condition (unit 1) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description tmr_2 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_3 overflow signal * 1 . tmr_3 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at falling edge of p /8192. 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_2 compare match a * 1 . all 1 0 1 ? ? uses external clock. counts at rising edge * 2 . 1 1 0 ? ? uses external clock. counts at falling edge * 2 . 1 1 1 ? ? uses external clock. counts at both rising and falling edges * 2 . notes: 1. if the clock input of channel 2 is the t cnt_3 overflow signal and that of channel 3 is the tcnt_2 compare match signal, no incrementi ng clock is generated. do not use this setting. 2. to use the external clock, the ddr and i cr bits in the corresponding pin should be set to 0 and 1, respectively. for de tails, see section 11, i/o ports. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 607 of 1102 rej09b0365-0100 table 14.4 clock input to tcnt and count condition (unit 2) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description tmr_4 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_5 overflow signal * . tmr_5 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_4 compare match a *. all 1 0 1 ? ? setting prohibited 1 1 0 ? ? setting prohibited 1 1 1 ? ? setting prohibited note: * if the clock input of channel 4 is the tcnt_5 overflow signal and that of channel 5 is the tcnt_4 compare match signal, no incrementi ng clock is generated. do not use this setting. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 608 of 1102 rej09b0365-0100 table 14.5 clock input to tcnt and count condition (unit 3) tcr tccr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description tmr_6 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_7 overflow signal * . tmr_7 0 0 0 ? ? clock input prohibited 0 0 1 0 0 uses internal clock. counts at rising edge of p /8. 0 1 uses internal clock. counts at rising edge of p /2. 1 0 uses internal clock. counts at falling edge of p /8. 1 1 uses internal clock. counts at falling edge of p /2. 0 1 0 0 0 uses internal clock. counts at rising edge of p /64. 0 1 uses internal clock. counts at rising edge of p /32. 1 0 uses internal clock. counts at falling edge of p /64. 1 1 uses internal clock. counts at falling edge of p /32. 0 1 1 0 0 uses internal clock. counts at rising edge of p /8192. 0 1 uses internal clock. counts at rising edge of p /1024. 1 0 uses internal clock. counts at rising edge of p . 1 1 uses internal clock. counts at falling edge of p /1024. 1 0 0 ? ? counts at tcnt_6 compare match a *. all 1 0 1 ? ? setting prohibited 1 1 0 ? ? setting prohibited 1 1 1 ? ? setting prohibited note: * if the clock input of channel 6 is the tcnt_7 overflow signal and that of channel 7 is the tcnt_6 compare match signal, no incrementi ng clock is generated. do not use this setting. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 609 of 1102 rej09b0365-0100 14.3.6 timer control/s tatus register (tcsr) tcsr displays status flags, and controls compare match output. ? tcsr_0 ? tcsr_1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 2 os2 0 r/w 1 os1 0 r/w 0 os0 0 r/w 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 r 3 os3 0 r/w 2 os2 0 r/w 1 os1 0 r/w 0 os0 0 r/w bit bit name initial value r/w bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. ? tcsr_0 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare match flag b [setting condition] ? when tcnt matches tcorb [clearing conditions] ? when writing 0 after reading cmfb = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmib interrupt while the disel bit in mrb of the dtc is 0 * 3 section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 610 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 cmfa 0 r/(w) * 1 compare match flag a [setting condition] ? when tcnt matches tcora [clearing conditions] ? when writing 0 after reading cmfa = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmia interrupt while the disel bit in mrb in the dtc is 0 * 3 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] when writing 0 after reading ovf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4 adte 0 r/w a/d trigger enable * 3 selects enabling or disabling of a/d converter start requests by compare match a. 0: a/d converter start requests by compare match a are disabled 1: a/d converter start requests by compare match a are enabled 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 * 2 these bits select a method of tmo pin output when compare match b of tcorb and tcnt occurs. 00: no change when compare match b occurs 01: 0 is output when compare match b occurs 10: 1 is output when compare match b occurs 11: output is inverted when compare match b occurs (toggle output) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 611 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 * 2 these bits select a method of tmo pin output when compare match a of tcora and tcnt occurs. 00: no change when compare match a occurs 01: 0 is output when compare match a occurs 10: 1 is output when compare match a occurs 11: output is inverted when compare match a occurs (toggle output) notes: 1. only 0 can be written to bi ts 7 to 5, to clear these flags. 2. timer output is disabled when bits os3 to os0 are all 0. timer output is 0 until the first compare match occurs after a reset. 3. for the corresponding a/d converter ch annels, see section 18, a/d converter. ? tcsr_1 bit bit name initial value r/w description 7 cmfb 0 r/(w) * 1 compare match flag b [setting condition] ? when tcnt matches tcorb [clearing conditions] ? when writing 0 after reading cmfb = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmib interrupt while the disel bit in mrb of the dtc is 0* 3 section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 612 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 cmfa 0 r/(w) * 1 compare match flag a [setting condition] ? when tcnt matches tcora [clearing conditions] ? when writing 0 after reading cmfa = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when the dtc is activated by a cmia interrupt while the disel bit in mrb of the dtc is 0 * 3 5 ovf 0 r/(w) * 1 timer overflow flag [setting condition] when tcnt overflows from h'ff to h'00 [clearing condition] cleared by reading ovf when ovf = 1, then writing 0 to ovf (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 4 ? 1 r reserved this bit is always read as 1 and cannot be modified. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 * 2 these bits select a method of tmo pin output when compare match b of tcorb and tcnt occurs. 00: no change when compare match b occurs 01: 0 is output when compare match b occurs 10: 1 is output when compare match b occurs 11: output is inverted when compare match b occurs (toggle output) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 613 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 * 2 these bits select a method of tmo pin output when compare match a of tcora and tcnt occurs. 00: no change when compare match a occurs 01: 0 is output when compare match a occurs 10: 1 is output when compare match a occurs 11: output is inverted when compare match a occurs (toggle output) notes: 1. only 0 can be written to bi ts 7 to 5, to clear these flags. 2. timer output is disabled when bits os3 to os0 are all 0. timer output is 0 until the first compare match occurs after a reset. 3. available only in unit 0 and unit 1. 14.4 operation 14.4.1 pulse output figure 14.5 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. the control bits are set as follows: 1. clear the bit cclr1 in tcr to 0 and set the bit cclr0 in tcr to 1 so that tcnt is cleared at a tcora compare match. 2. set the bits os3 to os0 in tcsr to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides pulses output at a cycle determined by tcora with a pulse width determined by tcorb. no software intervention is required. the timer output is 0 until the first compare matc h occurs after a reset. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 614 of 1102 rej09b0365-0100 tcnt h'ff counter clear tcora tcorb h'00 tmo figure 14.5 example of pulse output 14.4.2 reset input figure 14.6 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a tmri inpu t. the control bits are set as follows: 1. set both bits cclr1 and cclr0 in tcr to 1 and set the tmris bit in tccr to 1 so that tcnt is cleared at the high level input of the tmri signal. 2. in tcsr, set bits os3 to os0 to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides pulses output at a desired delay time from a tmri input determined by tcora and with a pulse width determined by tcorb and tcora. tcnt tcorb tcora h'00 tmri tmo figure 14.6 example of reset input section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 615 of 1102 rej09b0365-0100 14.5 operation timing 14.5.1 tcnt count timing figure 14.7 shows the tcnt count timing for internal clock input. figure 14.8 shows the tcnt count timing for external clock input. note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at l east 2.5 states for increm ent at both edges. the counter will not increment correctly if th e pulse width is less than these values. p internal clock tcnt input clock tcnt n ? 1 n n + 1 figure 14.7 count timing for internal clock input p external clock input pin tcnt input clock tcnt n ? 1 n n + 1 figure 14.8 count timing for external clock input section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 616 of 1102 rej09b0365-0100 14.5.2 timing of cmfa and cm fb setting at compare match the cmfa and cmfb flags in tcsr are set to 1 by a compare match signal generated when the tcor and tcnt values match. the compare match si gnal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when the tcor and tcnt values match, the compare match signal is not generated until the next tcnt clock input. figure 14.9 shows this timing. p tcnt n n + 1 tcor n compare match signal cmf figure 14.9 timing of cmf setting at compare match 14.5.3 timing of timer output at compare match when a compare match signal is generated, the timer output changes as specified by the bits os3 to os0 in tcsr. figure 14.10 shows the timing when the timer output is toggled by the compare match a signal. p compare match a signal timer output pin figure 14.10 timing of toggled timer output at compare match a section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 617 of 1102 rej09b0365-0100 14.5.4 timing of counter clear by compare match tcnt is cleared when compare match a or b occurs, depending on the settings of the bits cclr1 and cclr0 in tcr. figure 14.11 shows the timing of this operation. p n h'00 compare match signal tcnt figure 14.11 timing of co unter clear by compare match 14.5.5 timing of tc nt external reset* tcnt is cleared at the rising edge or high level of an external reset input, depending on the settings of bits cclr1 and cclr0 in tcr. the clear pulse width must be at least 2 states. figure 14.12 and figure 14.13 shows the timing of this operation. note: * clearing by an external reset is available only in units 0 and 1. p clear signal external reset input pin tcnt n h'00 n ? 1 figure 14.12 timing of clearan ce by external reset (rising edge) p clear signal external reset input pin tcnt n h'00 n ? 1 figure 14.13 timing of clearan ce by external reset (high level) section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 618 of 1102 rej09b0365-0100 14.5.6 timing of overf low flag (ovf) setting the ovf bit in tcsr is set to 1 when tcnt overflows (changes from h'ff to h'00). figure 14.14 shows the timing of this operation. p ovf overflow signal tcnt h'ff h'00 figure 14.14 timing of ovf setting 14.6 operation with cascaded connection if the bits cks2 to cks0 in either tcr_0 or tcr_ 1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). 14.6.1 16-bit counter mode when the bits cks2 to cks0 in tcr_0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. (1) setting of compare match flags ? the cmf flag in tcsr_0 is set to 1 when a 16-bit compare match event occurs. ? the cmf flag in tcsr_1 is set to 1 when a lower 8-bit compare match event occurs. (2) counter clear specification ? if the cclr1 and cclr0 bits in tcr_0 have been set for counter clear at compare match, the 16-bit counter (tcnt_0 and tcnt_1 together) is cleared when a 16-b it compare match event occurs. the 16-bit counter (tcnt0 and tcnt1 toge ther) is cleared even if counter clear by the tmri0 pin has been set. ? the settings of the cclr1 and cclr0 bits in tc r_1 are ignored. the lower 8 bits cannot be cleared independently. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 619 of 1102 rej09b0365-0100 (3) pin output ? control of output from the tmo0 pin by the bits os3 to os0 in tcsr_0 is in accordance with the 16-bit compare match conditions. ? control of output from the tmo1 pin by the bits os3 to os0 in tcsr_1 is in accordance with the lower 8-bit compare match conditions. 14.6.2 compare match count mode when the bits cks2 to cks0 in tcr_1 are set to b'100, tcnt_1 counts compare match a for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clear are in accordance with the settings for each channel. 14.7 interrupt sources 14.7.1 interrupt sources and dtc activation ? interrupt in unit 0 and unit 1 there are three interrupt sources for the 8-bit timer (tmr_0 or tmr_1): cmia, cmib, and ovi. their interrupt sources and priorities are shown in table 14.6. each interrupt source is enabled or disabled by the corresponding interrupt enable bit in tcr or tcsr, and independent interrupt requests are sent for each to the interrupt controlle r. it is also possible to activate the dtc by means of cmia and cmib interrupts (this is available in unit 0 and unit 1 only). table 14.6 8-bit timer (tmr_0 or tmr_1) interrupt sources (in unit 0 and unit 1) signal name name interrupt source interrupt flag dtc activation priority cmia0 cmia0 tcora_0 compare match cmfa possible high cmib0 cmib0 tcorb_0 compare match cmfb possible ovi0 ovi0 tcnt_0 overflow ovf not possible low cmia1 cmia1 tcora_1 compare match cmfa possible high cmib1 cmib1 tcorb_1 compare match cmfb possible ovi1 ovi1 tcnt_1 overflow ovf not possible low section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 620 of 1102 rej09b0365-0100 ? interrupt in unit 2 and unit 3 there are two interrupt sources for the 8-bit timer (tmr_4 or tmr_5): cmia, cmib. the interrupt signal is cmi only. the interrupt sources are shown in table 14.7. when enabling or disabling is set by the interrupt enable bit in tcr or tcsr, and when either cmia or cmib interrupt source is generated, cmi is sent to th e interrupt controller. to verify which interrupt source is generated, confirm by checking each flag in tcsr. no overflow-r elated interrupt signal exists. dtc cannot be activ ated by this interrupt. table 14.7 8-bit timer (tmr_4 or tmr_5) interrupt sources (in unit 2 and unit 3) signal name name interrupt source interrupt flag dtc activation priority cmia4 tcora_4 compare match cmfa ? cmi4 cmib4 tcorb_4 compare match cmfb not possible cmia5 tcora_5 compare match cmfa ? cmi5 cmib5 tcorb_5 compare match cmfb not possible 14.7.2 a/d converter activation the a/d converter can be activated by a compare match a for the even channels of each tmr unit. * if the adte bit in tcsr is set to 1 when the cmfa flag in tcsr is set to 1 by the occurrence of a compare match a, a request to start a/d conversion is sent to the a/d converter. if the 8-bit timer conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. note: * for the corresponding a/d converter channels, see section 18, a/d converter. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 621 of 1102 rej09b0365-0100 14.8 usage notes 14.8.1 notes on setting cycle if the compare match is selected for counter clear, tc nt is cleared at the last state in the cycle in which the values of tcnt and tcor match. tcnt updates the counter value at this last state. therefore, the counter fr equency is obtained by the following formula. f = / (n + 1 ) f: counter frequency : operating frequency n: tcor value 14.8.2 conflict between tcnt write and counter clear if a counter clear signal is generated during the t 2 state of a tcnt write cycle, the clear takes priority and the write is not performed as shown in figure 14.15. p address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 14.15 conflict between tcnt write and clear section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 622 of 1102 rej09b0365-0100 14.8.3 conflict between tc nt write and increment if a tcnt input clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the counter is not incremented as shown in figure 14.16. p address tcnt address internal write signal tcnt input clock tcnt n m t 1 t 2 tcnt write cycle by cpu counter write data figure 14.16 conflict between tcnt write and increment 14.8.4 conflict between tcor write and compare match if a compare match event occurs during the t 2 state of a tcor write cycle, the tcor write takes priority and the compare match signal is inhibited as shown in figure 14.17. p address tcor address internal write signal tcnt tcor n m t 1 t 2 tcor write cycle by cpu tcor write data n n + 1 compare match signal inhibited figure 14.17 conflict between tcor write and compare match section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 623 of 1102 rej09b0365-0100 14.8.5 conflict between compare matches a and b if compare match events a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set fo r compare match a and comp are match b, as shown in table 14.8. table 14.8 timer output priorities output setting priority toggle output high 1-output 0-output no change low 14.8.6 switching of internal clocks and tcnt operation tcnt may be incremented erroneously depending on when the internal clock is switched. table 14.9 shows the relationship between the timing at which the internal clock is switched (by writing to the bits cks1 and cks0) and the tcnt operation. when the tcnt clock is generated from an internal clock, the rising or falling edge of the internal clock pulse are always monitored. table 14.9 assu mes that the falling edge is selected. if the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. th erefore, a tcnt clock pulse is generated and tcnt is incremented. this is similar to when the rising edge is selected. the erroneous increment of tcnt can also happen when switching between rising and falling edges of the internal clock, and when swit ching between internal and external clocks. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 624 of 1102 rej09b0365-0100 table 14.9 switching of internal clock and tcnt operation no. timing to change cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 n + 2 3 switching from high to low * 3 clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 n + 2 * 4 4 switching from high to high clock before switchover clock after switchover tcnt input clock tcnt cks bits changed n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated because the chan ge of the signal levels is considered as a falling edge; tcnt is incremented. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 625 of 1102 rej09b0365-0100 14.8.7 mode setting wi th cascaded connection if 16-bit counter mode and compare match count mode are specified at the same time, input clocks for tcnt_0 and tcnt_1 are not generated, and the counter stops. do not specify 16-bit counter mode and compare match count mode simultaneously. 14.8.8 module stop state setting operation of the tmr can be disabled or enabled using the module stop control register. the initial setting is for operation of the tmr to be halted. register access is enabled by clearing the module stop state. for details, s ee section 24, power-down modes. 14.8.9 interrupts in module stop state if the module stop state is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. in terrupts should therefore be disabled before entering the module stop state. section 14 8-bit timers (tmr) rev. 1.00 sep. 13, 2007 page 626 of 1102 rej09b0365-0100 section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 627 of 1102 rej09b0365-0100 section 15 watchdog timer (wdt) the watchdog timer (wdt) is an 8-bit timer that outputs an overflow signal ( wdtovf ) if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. at the same time, the wdt can also generate an internal reset signal. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. figure 15.1 shows a block diagram of the wdt. 15.1 features ? selectable from eight counter input clocks ? switchable between watchdog timer mode and interval timer mode ? in watchdog timer mode if the counter overflows, the wdt outputs wdtovf . it is possible to select whether or not the entire lsi is reset at the same time. ? in interval timer mode if the counter overflows, the wdt generates an interval timer interrupt (wovi). section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 628 of 1102 rej09b0365-0100 overflow interrupt control wovi (interrupt request signal) internal reset signal * wdtovf reset control rstcsr tcnt tcsr p /2 p /64 p /128 p /512 p /2048 p /8192 p /32768 p /131072 clock clock select internal clocks bus interface module bus tcsr: tcnt: rstcsr: note: * an internal reset signal can be generated by the rstcsr setting. timer control/status register timer counter reset control/status register wdt [legend] internal bus figure 15.1 block diagram of wdt 15.2 input/output pin table 15.1 shows the wdt pin configuration. table 15.1 pin configuration name symbol i/o function watchdog timer overflow* wdtovf output outputs a counter overflow signal in watchdog timer mode note: * in boundary scan valid mode, counter overflow signal output cannot be used. section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 629 of 1102 rej09b0365-0100 15.3 register descriptions the wdt has the following three registers. to prevent accidental overwriting, tcsr, tcnt, and rstcsr have to be written to in a method different from normal registers. for details, see section 15.6.1, notes on register access. ? timer counter (tcnt) ? timer control/status register (tcsr) ? reset control/status register (rstcsr) 15.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tc nt is initialized to h'00 when the tme bit in tcsr is cleared to 0. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 15.3.2 timer control/s tatus register (tcsr) tcsr selects the clock source to be input to tcnt, and the timer mode. bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 1 r 3 ? 1 r 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 630 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 ovf 0 r/(w) * overflow flag indicates that tcnt has overflowed in interval timer mode. only 0 can be written to this bit, to clear the flag. [setting condition] when tcnt overflows in interval timer mode (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing condition] cleared by reading tcsr when ovf = 1, then writing 0 to ovf (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode when tcnt overflows, an interval timer interrupt (wovi) is requested. 1: watchdog timer mode when tcnt overflows, the wdtovf signal is output. 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4, 3 ? all 1 r reserved these are read-only bits and cannot be modified. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the clock source to be input to tcnt. the overflow cycle for p = 20 mhz is indicated in parentheses. 000: clock p /2 (cycle: 25.6 s) 001: clock p /64 (cycle: 819.2 s) 010: clock p /128 (cycle: 1.6 ms) 011: clock p /512 (cycle: 6.6 ms) 100: clock p /2048 (cycle: 26.2 ms) 101: clock p /8192 (cycle: 104.9 ms) 110: clock p /32768 (cycle: 419.4 ms) 111: clock p /131072 (cycle: 1.68 s) note: * only 0 can be written to this bit, to clear the flag. section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 631 of 1102 rej09b0365-0100 15.3.3 reset control/st atus register (rstcsr) rstcsr controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the wdt internal reset signal caused by wdt overflows. 7 wovf 0 r/(w) * 6 rste 0 r/w 5 ? 0 r/w 4 ? 1 r 3 ? 1 r 2 ? 1 r 1 ? 1 r 0 ? 1 r bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog timer overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode, and only 0 can be written. [setting condition] when tcnt overflows (changed from h'ff to h'00) in watchdog timer mode [clearing condition] reading rstcsr when wovf = 1, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not this lsi is internally reset if tcnt overflows during watchdog timer operation. 0: lsi is not reset even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: lsi is reset if tcnt overflows section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 632 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 ? 0 r/w reserved although this bit is readable/writable, reading from or writing to this bit does not affect operation. 4 to 0 ? all 1 r reserved these are read-only bits and cannot be modified. note: * only 0 can be written to this bit, to clear the flag. 15.4 operation 15.4.1 watchdog timer mode to use the wdt in watchdog timer mode, set both the wt/ it and tme bits in tcsr to 1. during watchdog timer operation, if tcnt overflows without being rewritten because of a system crash or other error, the wdtovf signal is output. this ensures that tcnt does not overflow while the system is operating normally. software must prevent tcnt overflows by rewriting the tcnt value (normally h'00 is written) before overflow occurs. this wdtovf signal can be used to reset the lsi internally in watchdog timer mode. if tcnt overflows when the rste bit in rstcsr is set to 1, a signal that resets this lsi internally is generated at the same time as the wdtovf signal. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. the wdtovf signal is output for 133 cycles of p when rste = 1 in rstcsr, and for 130 cycles of p when rste = 0 in rstcsr. the internal reset signal is output for 519 cycles of p . when rste = 1, an internal reset signal is generated. since the system clock control register (sckcr) is initialized, the multiplication ratio of p becomes the initial value. when rste = 0, an internal reset signal is not generated. neither sckcr nor the multiplication ratio of p is changed. when tcnt overflows in watchdog timer mode, the wovf bit in rstcsr is set to 1. if tcnt overflows when the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire lsi. section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 633 of 1102 rej09b0365-0100 tcnt value h'00 time h'ff wt/ it = 1 tme = 1 h'00 written to tcnt wt/ it = 1 tme = 1 h'00 written to tcnt 133 states * 2 519 states wdtovf signal internal reset signal * 1 notes: 1. if tcnt overflows when the rste bit is set to 1, an internal reset signal is generated. 2. 130 states when the rste bit is cleared to 0. overflow wdtovf and internal reset are generated wovf = 1 figure 15.2 operation in watchdog timer mode section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 634 of 1102 rej09b0365-0100 15.4.2 interval timer mode to use the wdt as an interval timer, set the wt/ it bit to 0 and the tme bit to 1 in tcsr. when the wdt is used as an interval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows. therefore, an in terrupt can be generated at intervals. when the tcnt overflows in interval timer mode, an interval timer interrupt (wovi) is requested at the same time the ovf bit in the tcsr is set to 1. tcnt value h'00 time h'ff wt/ it = 0 tme = 1 wovi overflow overflow overflow overflow [legend] wovi: interval timer interrupt request wovi wovi wovi figure 15.3 operation in interval timer mode 15.5 interrupt source during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. the ovf flag must be cleared to 0 in the interrupt handling routine. table 15.2 wdt interrupt source name interrupt source interrupt flag dtc activation wovi tcnt overflow ovf impossible section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 635 of 1102 rej09b0365-0100 15.6 usage notes 15.6.1 notes on register access the watchdog timer's tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. (1) writing to tcnt, tcsr, and rstcsr tcnt and tcsr must be written to by a word transfer instruction. they cannot be written to by a byte transfer instruction. for writing, tcnt and tcsr are assigned to the same address. accordingly, perform data transfer as shown in figure 15.4. the transfer in struction writes the lower byte data to tcnt or tcsr. to write to rstcsr, execute a word transfer instruction for address h'ffa6. a byte transfer instruction cannot be used to write to rstcsr. the method of writing 0 to the wovf bit in rstcsr differs from that of writing to the rste bit in rstcsr. perform data transfer as shown in figure 15.4. at data transfer, the transfer in struction clears the wovf bit to 0, but has no effect on the rste bit. to write to the rste bit, perform data transfer as shown in figure 15.4. in this case, the transfer instruction writes the value in bit 6 of the lower byte to the rste bit, but has no effect on the wovf bit. tcnt write or writing to the rste bit in rstcsr: tcsr write: address: h'ffa4 (tcnt) h'ffa6 (rstcsr) 15 8 7 0 h'5a write data address: h'ffa4 (tcsr) 15 8 7 0 h'a5 write data writing 0 to the wovf bit in rstcsr: address: h'ffa6 (rstcsr) 15 8 7 0 h'a5 h'00 figure 15.4 writing to tcnt, tcsr, and rstcsr section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 636 of 1102 rej09b0365-0100 (2) reading from tcnt, tcsr, and rstcsr these registers can be read from in the same way as other registers. for reading, tcsr is assigned to address h'ffa4, tcnt to address h'ffa5, and rstcsr to address h'ffa7. 15.6.2 conflict between timer co unter (tcnt) write and increment if a tcnt clock pulse is generated during the t2 cycle of a tcnt write cycle, the write takes priority and the timer counter is not increm ented. figure 15.5 shows this operation. n m t 1 t 2 address p internal write signal tcnt input clock tcnt tcnt write cycle counter write data figure 15.5 conflict between tcnt write and increment 15.6.3 changing values of bits cks2 to cks0 if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. the watchdog timer must be stopped (by clearing the tme bit to 0) before the values of bits cks2 to cks0 are changed. 15.6.4 switching between watchdog ti mer mode and interval timer mode if the timer mode is switched from watchdog timer mode to interval timer mode while the wdt is operating, errors could occur in the incrementation. the watchdog timer must be stopped (by clearing the tme bit to 0) before switching the timer mode. section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 637 of 1102 rej09b0365-0100 15.6.5 internal reset in watchdog timer mode this lsi is not reset internally if tcnt ove rflows while the rste bit is cleared to 0 during watchdog timer mode operation, but tcnt and tcsr of the wdt are reset. tcnt, tcsr, and rstcr cannot be written to while the wdtovf signal is low. also note that a read of the wovf flag is not recognized during this period. to clear th e wovf flag, therefore, read tcsr after the wdtovf signal goes high, then write 0 to the wovf flag. 15.6.6 system reset by wdtovf signal if the wdtovf signal is input to the res pin, this lsi will not be initialized correctly. make sure that the wdtovf signal is not input logically to the res pin. to reset the entire system by means of the wdtovf signal, use a circuit like that shown in figure 15.6. reset input reset signal to entire system this lsi res wdtovf figure 15.6 circuit for system reset by wdtovf signal (example) 15.6.7 transition to watchdog tim er mode or software standby mode when the wdt operates in watchd og timer mode, a transition to software standby mode is not made even when the sleep instruction is executed when the ssby bit in sbycr is set to 1. instead, a transition to sleep mode is made. to transit to software standby mode, the sleep instruction must be executed after halting the wdt (clearing the tme bit to 0). when the wdt operates in interval timer mode, a transition to software standby mode is made through execution of the sleep instruction when the ssby bit in sbycr is set to 1. section 15 watchdog timer (wdt) rev. 1.00 sep. 13, 2007 page 638 of 1102 rej09b0365-0100 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 639 of 1102 rej09b0365-0100 section 16 serial co mmunications interface (sci, irda, crc) this lsi has seven independent serial commun ications interface (sci) channels. the sci can handle both asynchronous and clock synchronous serial communications. asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a universal asynchronous receiver/transmit ter (uart) or asynch ronous communication interface adapter (acia). a function is also pr ovided for serial communications between processors (multiprocessor communication function). the sci also supports the smart card (smart card) interface supporting iso/ iec 7816-3 (identification card) as an extended asynchronous communications mode. sci_5 enables transmitting and receiving irda communication waveform based on the irda specifications version 1.0. this lsi incorporates the on-chip crc (cyclic redundancy check) computing unit that realizes high reliability of high-speed data transfer as sci extended function. since the crc computing unit is not connected to sci, operation is executed by writing data to registers. figure 16.1 shows a block diagram of the sci_0 to sci_4. figure 16.2 shows a block diagram of the sci_5 and sci_6. 16.1 features ? choice of asynchronous or clock synchronous serial communications mode ? full-duplex communications capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected the external clock can be selected as a tran sfer clock source (except for the smart card interface). ? choice of lsb-first or msb-first transfer (except in the case of asynchronous mode 7-bit data) ? four interrupt sources the interrupt sources are tran smit-end, transmit-data-empty, receive-data-full, and receive error. the transmit-data-empty and receive-data-full interrupt so urces can activate the dtc or dmac. ? module stop state specifiable section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 640 of 1102 rej09b0365-0100 asynchronous mode: ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by r eading the rxd pin level directly in case of a framing error ? enables transfer rate clock i nput from tmr (sci_5, sci_6) ? average transfer rate generator (sci_2) 10.667-mhz operation: 115.152 kbps or 460.606 kbps can be selected 16-mhz operation: 115.196 kbps, 460.784 kbps, or 720 kbps can be selected 32-mhz operation: 720 kbps ? average transfer rate generator (sci_5, sci_6) 8-mhz operation: 460.784 kbps can be selected 10.667-mhz operation: 115.152 kbps or 460.606 kbps can be selected 12-mhz operation: 230.263 kbps or 460.526 kbps can be selected 16-mhz operation: 115.196 kbps, 460.784 kbps, 720 kbps, or 921.569 kbps can be selected 24-mhz operation: 115.132 kbps, 460.526 kbps, 720 kbps, or 921.053 kbps can be selected 32-mhz operation: 720 kbps can be selected clock synchronous mode: ? data length: 8 bits ? receive error detecti on: overrun errors smart card interface: ? an error signal can be automatically transmitted on detection of a parity error during reception ? data can be automatically re-transmitted on r eceiving an error signal during transmission ? both direct convention and inverse convention are supported section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 641 of 1102 rej09b0365-0100 table 16.1 lists the func tions of each channel. table 16.1 function list of sci channels sci_0, 1, 3, 4 sci_2 sci_5, sci_6 clock synchronous mode o o o asynchronous mode o o o tmr clock input ? ? o p = 8 hz ? ? 460.784 kbps p = 10.667 hz ? 460.606 kbps 115.152 kbps 460.606 kbps 115.152 kbps p = 12 hz ? ? 460.526 kbps 230.263 kbps p = 16 hz ? 720 kbps 460 784kbps 115.196 kbps 921.569 kbps 720 kbps 460.784 kbps 115.196 kbps p = 24 hz ? ? 921.053 kbps 720 kbps 460.526 kbps 115.132 kbps when average transfer rate generator is used p = 32 hz ? 720 kbps 720 kbps section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 642 of 1102 rej09b0365-0100 rxd txd sck clock p p /4 p /16 p /64 tei txi rxi eri scmr ssr scr smr transmission/ reception control baud rate generator brr module data bus rdr tsr rsr parity generation parity check [legend] rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register tdr bus interface internal data bus external clock scr: serial control register ssr: serial status register scmr: smart card mode register brr: bit rate register semr: serial extended mode register (available only for sci_2) average transfer rate generator (sci_2) figure 16.1 block diagram of sci_0, 1, 2, 3, and 4 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 643 of 1102 rej09b0365-0100 rxd0 txd0 clock p p /4 p /16 p /64 tei txi rxi eri scmr ssr scr smr semr ircr * transmission/ reception control baud rate generator brr tmr tmo4, 6 tmo5, 7 module data bus rdr tsr rsr parity generation parity check [legend] rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register note: * sci_5 only. tdr bus interface internal data bus average transfer rate generator sck ssr: serial status register scmr: smart card mode register brr: bit rate register semr: serial extended mode register ircr: irda control register (available only for sci_5) figure 16.2 block diagram of sci_5 and sci_6 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 644 of 1102 rej09b0365-0100 16.2 input/output pins table 16.2 lists the pin configuration of the sci. table 16.2 pin configuration channel pin name * i/o function sck0 i/o channel 0 clock input/output rxd0 input channel 0 receive data input 0 txd0 output channel 0 transmit data output sck1 i/o channel 1 clock input/output rxd1 input channel 1 receive data input 1 txd1 output channel 1 transmit data output sck2 i/o channel 2 clock input/output rxd2 input channel 2 receive data input 2 txd2 output channel 2 transmit data output sck3 i/o channel 3 clock input/output rxd3 input channel 3 receive data input 3 txd3 output channel 3 transmit data output sck4 i/o channel 4 clock input/output rxd4 input channel 4 receive data input 4 txd4 output channel 4 transmit data output sck5 i/o channel 5 clock input/output rxd5/irrxd input channel 5 receive data input 5 txd5/irtxd output channel 5 transmit data output sck6 i/o channel 6 clock input/output rxd6 input channel 6 receive data input 6 txd6 output channel 6 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 645 of 1102 rej09b0365-0100 16.3 register descriptions the sci has the following registers. some bits in the serial mode register (smr), serial status register (ssr), and serial control register (scr) have different functions in different modes ? normal serial communi cations interface mode and smart card interface mode; therefore, the bits are described separately for each mo de in the corresponding register sections. channel 0: ? receive shift register_0 (rsr_0) ? transmit shift register_0 (tsr_0) ? receive data register_0 (rdr_0) ? transmit data register_0 (tdr_0) ? serial mode register_0 (smr_0) ? serial control register_0 (scr_0) ? serial status re gister_0 (ssr_0) ? smart card mode register_0 (scmr_0) ? bit rate register_0 (brr_0) channel 1: ? receive shift register_1 (rsr_1) ? transmit shift register_1 (tsr_1) ? receive data register_1 (rdr_1) ? transmit data register_1 (tdr_1) ? serial mode register_1 (smr_1) ? serial control register_1 (scr_1) ? serial status re gister_1 (ssr_1) ? smart card mode register_1 (scmr_1) ? bit rate register_1 (brr_1) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 646 of 1102 rej09b0365-0100 channel 2: ? receive shift register_2 (rsr_2) ? transmit shift register_2 (tsr_2) ? receive data register_2 (rdr_2) ? transmit data register_2 (tdr_2) ? serial mode register_2 (smr_2) ? serial control register_2 (scr_2) ? serial status re gister_2 (ssr_2) ? smart card mode register_2 (scmr_2) ? bit rate register_2 (brr_2) channel 4: ? receive shift register_4 (rsr_4) ? transmit shift register_4 (tsr_4) ? receive data register_4 (rdr_4) ? transmit data register_4 (tdr_4) ? serial mode register_4 (smr_4) ? serial control register_4 (scr_4) ? serial status re gister_4 (ssr_4) ? smart card mode register_4 (scmr_4) ? bit rate register_4 (brr_4) channel 5: ? receive shift register_5 (rsr_5) ? transmit shift register_5 (tsr_5) ? receive data register_5 (rdr_5) ? transmit data register_5 (tdr_5) ? serial mode register_5 (smr_5) ? serial control register_5 (scr_5) ? serial status re gister_5 (ssr_5) ? smart card mode register_5 (scmr_5) ? bit rate register_5 (brr_5) ? serial extended mode register_5 (semr_5) ? irda control register_5 (ircr) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 647 of 1102 rej09b0365-0100 channel 6: ? receive shift register_6 (rsr_6) ? transmit shift register_6 (tsr_6) ? receive data register_6 (rdr_6) ? transmit data register_6 (tdr_6) ? serial mode register_6 (smr_6) ? serial control register_6 (scr_6) ? serial status re gister_6 (ssr_6) ? smart card mode register_6 (scmr_6) ? serial extended mode register_6 (semr_6) ? bit rate register_6 (brr_6) 16.3.1 receive shi ft register (rsr) rsr is a shift register which is used to receive se rial data input from the rxd pin and converts it into parallel data. when one frame of data ha s been received, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 16.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive da ta. when the sci has received one frame of serial data, it transfers the received serial data from rsr to rdr where it is stored. this allows rsr to receive the next data. since rsr and rdr function as a double buffer in this way, continuous receive operations can be performed . after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. bit bit name initial value r/w 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 648 of 1102 rej09b0365-0100 16.3.3 transmit data register (tdr) tdr is an 8-bit register that stores transmit data. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to ts r and starts transmission. the double-buffered structures of tdr and tsr enable continuous seri al transmission. if the next transmit data has already been written to tdr when one frame of da ta is transmitted, the sc i transfers the written data to tsr to continue transmission. although tdr can be read from or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. bit bit name initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w 16.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first automatically transfers transmit data from tdr to tsr, and then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. 16.3.5 serial mode register (smr) smr is used to set the sci's serial transfer format and select the baud rate generator clock source. some bits in smr have different functions in normal mode and smart card interface mode. ? when smif in scmr = 0 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w ? when smif in scmr = 1 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 649 of 1102 rej09b0365-0100 bit functions in normal serial communication interface mode (when smif in scmr = 0): bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: clock synchronous mode 6 chr 0 r/w character length (valid only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb (bit 7) in tdr is not transmitted in transmission. in clock synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (valid only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 4 o/ e 0 r/w parity mode (valid only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (valid only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is tr eated as the start bit of the next transmit frame. 2 mp 0 r/w multiprocessor mode (valid only in asynchronous mode) when this bit is set to 1, the multiprocessor function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 650 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 1, 0 these bits select the clock source for the baud rate generator. 00: p clock (n = 0) 01: p /4 clock (n = 1) 10: p /16 clock (n = 2) 11: p /64 clock (n = 3) for the relation between the se ttings of these bits and the baud rate, see section 16.3.9, bit rate register (brr). n is the decimal display of the value of n in brr (see section 16.3.9, bit ra te register (brr)). bit functions in smart card interface mode (when smif in scmr = 1): bit bit name initial value r/w description 7 gm 0 r/w gsm mode setting this bit to 1 allows gsm mode operation. in gsm mode, the tend set timing is put forward to 11.0 etu from the start and the clock output control function is appended. for details, see sections 16.7.6, data transmission (except in block transfer mode) and 16.7.8, clock output control. 6 blk 0 r/w setting this bit to 1 allows block transfer mode operation. for details, see section 16.7.3, block transfer mode. 5 pe 0 r/w parity enable (valid only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. set this bit to 1 in smart card interface mode. 4 o/ e 0 r/w parity mode (valid only when the pe bit is 1 in asynchronous mode) 0: selects even parity 1: selects odd parity for details on the usage of this bit in smart card interface mode, see section 16.7.2, data format (except in block transfer mode). section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 651 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 bcp1 bcp0 0 0 r/w r/w base clock pulse 1, 0 these bits select the number of base clock cycles in a 1- bit data transfer time in smart card interface mode. 00: 32 clock cycles (s = 32) 01: 64 clock cycles (s = 64) 10: 372 clock cycles (s = 372) 11: 256 clock cycles (s = 256) for details, see section 16.7.4, receive data sampling timing and reception margin. s is described in section 16.3.9, bit rate register (brr). 1 0 cks1 cks0 0 0 r/w r/w clock select 1, 0 these bits select the clock source for the baud rate generator. 00: p clock (n = 0) 01: p /4 clock (n = 1) 10: p /16 clock (n = 2) 11: p /64 clock (n = 3) for the relation between the se ttings of these bits and the baud rate, see section 16.3.9, bit rate register (brr). n is the decimal display of the value of n in brr (see section 16.3.9, bit ra te register (brr)). note: etu (elementary time unit): 1-bit transfer time section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 652 of 1102 rej09b0365-0100 16.3.6 serial control register (scr) scr is a register that enables/disables the follow ing sci transfer operations and interrupt requests, and selects the transfer clock source. for details on interrupt requests, see section 16.9, interrupt sources. some bits in scr have different functions in normal mode and smart card interface mode. ? when smif in scmr = 0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w bit bit name initial value r/w ? when smif in scmr = 1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w bit bit name initial value r/w bit functions in normal serial communication interface mode (when smif in scmr = 0): bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, a txi interrupt request is enabled. a txi interrupt request can be cancelled by reading 1 from the tdre flag and then clearing the flag to 0, or by clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt requests can be cancelled by reading 1 from the rdrf, fer, per, or orer flag and then clearing the flag to 0, or by clearing the rie bit to 0. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 653 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. under this condition, serial transmi ssion is started by writing transmit data to tdr, and clearing the tdre flag in ssr to 0. note that smr should be set prior to setting the te bit to 1 in order to desig nate the transmission format. if transmission is halted by clearing this bit to 0, the tdre flag in ssr is fixed to 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clock synchronous mode. note that smr should be set prior to setting the re bit to 1 in order to designate the reception format. even if reception is halted by clearing this bit to 0, the rdrf, fer, per, and orer flags are not affected and the previous value is retained. 3 mpie 0 r/w multiprocessor interrupt enable (valid only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is disabled. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, see se ction 16.5, multiprocessor communication function. when receive data including mpb = 0 in ssr is being received, transfer of the received data from rsr to rdr, detection of reception errors, and the settings of rdrf, fer, and orer flags in ssr are not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is automatically cleared to 0, and rxi and eri interrupt requests (in the case where the tie and rie bits in scr are set to 1) and setting of the fer and orer flags are enabled. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 654 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, a tei interrupt request is enabled. a tei interrupt request can be cancelled by reading 1 from the tdre flag and then clearing the flag to 0 in order to clear the tend flag to 0, or by clearing the teie bit to 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 (for sci_0, 1, 3, and 4) these bits select the clock source and sck pin function. ? asynchronous mode 00: on-chip baud rate generator the sck pin functions as i/o port. 01: on-chip baud rate generator the clock with the same frequency as the bit rate is output from the sck pin. 1x: external clock the clock with a frequency 16 times the bit rate should be input from the sck pin. ? clock synchronous mode 0x: internal clock the sck pin functions as the clock output pin. 1x: external clock the sck pin functions as the clock input pin. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 655 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 (for sci_2) these bits select the clock source and sck pin function. ? asynchronous mode 00: on-chip baud rate generator the sck pin functions as i/o port. 01: on-chip baud rate generator the clock with the same frequency as the bit rate is output from the sck pin. 1x: external clock or average transfer rate generator when an external clock is used, the clock with a frequency 16 times the bit rate should be input from the sck pin. when an average transfer rate generator is used. ? clock synchronous mode 0x: internal clock the sck pin functions as the clock output pin. 1x: external clock the sck pin functions as the clock input pin. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 656 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 (for sci_5 and sci_6) these bits select the clock source and sck pin function. ? asynchronous mode 00: on-chip baud rate generator the sck pin functions as i/o port. 01: on-chip baud rate generator the clock with the same frequency as the bit rate is output from the sck pin. 1x: external clock, tmr clock input or average transfer rate generator when an external clock is used, the clock with a frequency 16 times the bit rate should be input from the sck pin. when an average transfer rate generator is used. when tmr clock input is used. ? clock synchronous mode 0x: internal clock the sck pin functions as the clock output pin. 1x: external clock the sck pin functions as the clock input pin. [legend] x: don't care section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 657 of 1102 rej09b0365-0100 bit functions in smart card interface mode (when smif in scmr = 1): bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1,a txi interrupt request is enabled. a txi interrupt request can be cancelled by reading 1 from the tdre flag and then clearing the flag to 0, or by clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt requests can be cancelled by reading 1 from the rdrf, fer, per, or orer flag and then clearing the flag to 0, or by clearing the rie bit to 0. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. under this condition, serial transmi ssion is started by writing transmit data to tdr, and clearing the tdre flag in ssr to 0. note that smr should be set prior to setting the te bit to 1 in order to desig nate the transmission format. if transmission is halted by clearing this bit to 0, the tdre flag in ssr is fixed 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clock synchronous mode. note that smr should be set prior to setting the re bit to 1 in order to designate the reception format. even if reception is halted by clearing this bit to 0, the rdrf, fer, per, and orer flags are not affected and the previous value is retained. 3 mpie 0 r/w multiprocessor interrupt enable (valid only when the mp bit in smr is 1 in asynchronous mode) write 0 to this bit in smart card interface mode. 2 teie 0 r/w transmit end interrupt enable write 0 to this bit in smart card interface mode. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 658 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 these bits control the clock output from the sck pin. in gsm mode, clock output can be dynamically switched. for details, see section 16.7.8, clock output control. ? when gm in smr = 0 00: output disabled (sck pin functions as i/o port.) * 01: clock output 1x: reserved ? when gm in smr = 1 00: output fixed low 01: clock output 10: output fixed high 11: clock output 16.3.7 serial status register (ssr) ssr is a register containing status flags of th e sci and multiprocessor bi ts for transfer. tdre, rdrf, orer, per, and fer can only be cleared. some bits in ssr have different functions in normal mode and smart card interface mode. ? when smif in scmr = 0 bit bit name initial value r/w 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fre 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w note: * only 0 can be written, to clear the flag. ? when smif in scmr = 1 bit bit name initial value r/w 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 2 tend 1 r 1 mpb 0 r 0 mpbt 0 r/w note: * only 0 can be written, to clear the flag. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 659 of 1102 rej09b0365-0100 bit functions in normal serial communication interface mode (when smif in scmr = 0): bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when a txi interrupt request is issued allowing dmac or dtc to write data to tdr section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 660 of 1102 rej09b0365-0100 bit bit name initial value r/w description 6 rdrf 0 r/(w) * receive data register full indicates whether receive data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when an rxi interrupt request is issued allowing dmac or dtc to read data from rdr the rdrf flag is not affected and retains its previous value when the re bit in scr is cleared to 0. note that when the next serial reception is completed while the rdrf flag is being set to 1, an overrun error occurs and the received data is lost. 5 orer 0 r/(w) * overrun error indicates that an overrun error has occurred during reception and the reception ends abnormally. [setting condition] ? when the next serial reception is completed while rdrf = 1 in rdr, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. when the orer flag is set to 1, subsequent serial reception cannot be performed. note that, in clock synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to orer after reading orer = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the orer flag is not affected and retains its previous value. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 661 of 1102 rej09b0365-0100 bit bit name initial value r/w description 4 fer 0 r/(w) * framing error indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [setting condition] ? when the stop bit is 0 in 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the seco nd stop bit is not checked. note that receive data when the framing error occurs is transferred to rdr, however, the rdrf flag is not set. in addition, when the fer flag is being set to 1, the subsequent serial rece ption cannot be performed. in clock synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to fer after reading fer = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the fer flag is not affected and retains its previous value. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 662 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 per 0 r/(w) * parity error indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [setting condition] ? when a parity error is detected during reception receive data when the parity error occurs is transferred to rdr, however, the rdrf flag is not set. note that when the per flag is being set to 1, the subsequent serial reception cannot be performed. in clock synchronous mode, se rial transmission also cannot continue. [clearing condition] ? when 0 is written to per after reading per = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the per bit is not affected and retains its previous value. 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when a txi interrupt request is issued allowing dmac or dtc to write data to tdr 1 mpb 0 r multiprocessor bit stores the multiprocessor bit value in the receive frame. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer sets the multiprocessor bit value to be added to the transmit frame. note: * only 0 can be written, to clear the flag. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 663 of 1102 rej09b0365-0100 bit functions in smart card interface mode (when smif in scmr = 1): bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when a txi interrupt request is issued allowing dmac or dtc to write data to tdr 6 rdrf 0 r/(w) * receive data register full indicates whether receive data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when an rxi interrupt request is issued allowing dmac or dtc to read data from rdr the rdrf flag is not affected and retains its previous value even when the re bit in scr is cleared to 0. note that when the next reception is completed while the rdrf flag is being set to 1, an overrun error occurs and the received data is lost. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 664 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 orer 0 r/(w) * overrun error indicates that an overrun error has occurred during reception and the reception ends abnormally. [setting condition] ? when the next serial reception is completed while rdrf = 1 in rdr, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. when the orer flag is set to 1, subsequent serial reception cannot be performed. note that, in clock synchronous mode, serial transmission also cannot continue. [clearing condition] ? when 0 is written to orer after reading orer = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the orer flag is not affected and retains its previous value. 4 ers 0 r/(w) * error signal status [setting condition] ? when a low error signal is sampled [clearing condition] ? when 0 is written to ers after reading ers = 1 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 665 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 per 0 r/(w) * parity error indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [setting condition] ? when a parity error is detected during reception receive data when the parity error occurs is transferred to rdr, however, the rdrf flag is not set. note that when the per flag is being set to 1, the subsequent serial reception cannot be performed. in clock synchronous mode, se rial transmission also cannot continue. [clearing condition] ? when 0 is written to per after reading per = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) even when the re bit in scr is cleared, the per flag is not affected and retains its previous value. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 666 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to tdr. [setting conditions] ? when both the te and ers bits in scr are 0 ? when ers = 0 and tdre = 1 after a specified time passed after completion of 1-byte data transfer. the set timing depends on the register setting as follows: when gm = 0 and blk = 0, 2.5 etu after transmission start when gm = 0 and blk = 1, 1.5 etu after transmission start when gm = 1 and blk = 0, 1.0 etu after transmission start when gm = 1 and blk = 1, 1.0 etu after transmission start [clearing conditions] ? when 0 is written to tend after reading tend = 1 ? when a txi interrupt request is issued allowing dmac or dtc to write the next data to tdr 1 mpb 0 r multiprocessor bit not used in smart card interface mode. 0 mpbt 0 r/w multiprocessor bit transfer write 0 to this bit in smart card interface mode. note: * only 0 can be written, to clear the flag. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 667 of 1102 rej09b0365-0100 16.3.8 smart card mode register (scmr) scmr selects smart card interface mode and its format. 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 1 ? 1 ? bit bit name initial value r/w 3 sdir 0 r/w 2 sinv 0 r/w 0 smif 0 r/w bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 sdir 0 r/w smart card data transfer direction selects the serial/parallel conversion format. 0: transfer with lsb-first 1: transfer with msb-first this bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with lsb-first. 2 sinv 0 r/w smart card data invert inverts the transmit/receive data logic level. this bit does not affect the logic level of the parity bit. to invert the parity bit, invert the o/ e bit in smr. 0: tdr contents are transmitt ed as they are. receive data is stored as it is in rdr. 1: tdr contents are inverted before being transmitted. receive data is stored in inverted form in rdr. 1 ? 1 ? reserved this bit is always read as 1. 0 smif 0 r/w smart card interface mode select when this bit is set to 1, smart card interface mode is selected. 0: normal asynchronous or clock synchronous mode 1: smart card interface mode section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 668 of 1102 rej09b0365-0100 16.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rates can be set for each channel. table 16.2 shows the relationships between the n setting in brr and bit rate b for normal asynchronous mode and clock synchronous mo de, and smart card interface mode. the initial value of brr is h'ff, and it can be read from or written to by the cpu at all times. table 16.3 relationships between n setting in brr and bit rate b mode abcs bit bit rate error 0 n = ? 1 64 2 b 2n ? 1 p 10 6 error (%) = { ? 1 } 100 b 64 2 (n + 1) 2n ? 1 p 10 6 asynchronous mode 1 n = ? 1 32 2 b 2n ? 1 p 10 6 error (%) = { ? 1 } 100 b 32 2 (n + 1) 2n ? 1 p 10 6 clock synchronous mode n = ? 1 8 2 b 2n ? 1 p 10 6 smart card interface mode n = ? 1 s 2 b p 10 6 2n + 1 error (%) = b s 2 (n + 1) ? 1 100 2n + 1 p 10 6 { } [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) p : operating frequency (mhz) n and s: determined by the smr settings shown in the following table. smr setting smr setting cks1 cks0 n bcp1 bcp0 s 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 669 of 1102 rej09b0365-0100 table 16.4 shows sample n settings in brr in normal asynchronous mode. table 16.5 shows the maximum bit rate settable for each operating freque ncy. tables 16.7 and 16.9 show sample n settings in brr in clock synchronous mode and smar t card interface mode, respectively. in smart card interface mode, the number of base clock cy cles s in a 1-bit data transfer time can be selected. for details, see sectio n 16.7.4, receive data sampling timing and reception margin. tables 16.6 and 16.8 show the maximum bit rates with external clock input. when the abcs bit in the serial extended mode register_2, 5, and 6 (semr_2, 5, and 6) of sci_2, 5, and 6 are set to 1 in asynchronous mode, the bit rate is two times that of shown in table 16.4. table 16.4 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency p (mhz) 8 9.8304 10 12 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 141 0.03 2 174 ?0.26 2 177 ?0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 ?1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 ?2.34 31250 0 7 0.00 0 9 ?1.70 0 9 0.00 0 11 0.00 38400 ? ? ? 0 7 0.00 0 7 1.73 0 9 ?2.34 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 670 of 1102 rej09b0365-0100 operating frequency p (mhz) 12.288 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 0 9 0.00 ? ? ? 0 11 0.00 0 12 0.16 note: in sci_2, 5, and 6, this is an example when the abcs bit in semr_2, 5, and 6 is 0. when the abcs bit is set to 1, the bit rate is two times. table 16.4 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency p (mhz) 17.2032 18 19.6608 20 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 75 0.48 3 79 ?0.12 3 86 0.31 3 88 ?0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 ?0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 ?1.36 31250 0 16 1.20 0 17 0.00 0 19 ?1.70 0 19 0.00 38400 0 13 0.00 0 14 ?2.34 0 15 0.00 0 15 1.73 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 671 of 1102 rej09b0365-0100 operating frequency p (mhz) 25 30 33 35 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 110 ?0.02 3 132 0.13 3 145 0.33 3 154 0.23 150 3 80 0.47 3 97 ?0.35 3 106 0.39 3 113 ?0.06 300 2 162 ?0.15 2 194 0.16 2 214 ?0.07 2 227 ?0.06 600 2 80 0.47 2 97 ?0.35 2 106 0.39 2 113 ?0.06 1200 1 162 ?0.15 1 194 0.16 1 214 ?0.07 1 227 ?0.06 2400 1 80 0.47 1 97 ?0.35 1 106 0.39 1 113 ?0.06 4800 0 162 ?0.15 0 194 0.16 0 214 ?0.07 0 227 ?0.06 9600 0 80 0.47 0 97 ?0.35 0 106 0.39 0 113 ?0.06 19200 0 40 ?0.76 0 48 ?0.35 0 53 ?0.54 0 56 ?0.06 31250 0 24 0.00 0 29 0 0 32 0 0 34 0.00 38400 0 19 1.73 0 23 1.73 0 26 ?0.54 0 27 1.73 note: in sci_2, 5, and 6, this is an example when the abcs bit in semr_2, 5, and 6 is 0. when the abcs bit is set to 1, the bit rate is two times. table 16.5 maximum bit rate for each operating frequency (asynchronous mode) p (mhz) maximum bit rate (bit/s) n n p (mhz) maximum bit rate (bit/s) n n 8 250000 0 0 17.2032 537600 0 0 9.8304 307200 0 0 18 562500 0 0 10 312500 0 0 19.6608 614400 0 0 12 375000 0 0 20 625000 0 0 12.288 384000 0 0 25 781250 0 0 14 437500 0 0 30 937500 0 0 14.7456 460800 0 0 33 1031250 0 0 16 500000 0 0 35 1093750 0 0 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 672 of 1102 rej09b0365-0100 table 16.6 maximum bit rate with external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bit/s) p (mhz) external input clock (mhz) maximum bit rate (bit/s) 8 2.0000 125000 17.2032 4.3008 268800 9.8304 2.4576 153600 18 4.5000 281250 10 2.5000 156250 19.6608 4.9152 307200 12 3.0000 187500 20 5.0000 312500 12.288 3.0720 192000 25 6.2500 390625 14 3.5000 218750 30 7.5000 468750 14.7456 3.6864 230400 33 8.2500 515625 16 4.0000 250000 35 8.7500 546875 note: in sci_2, this is an example when the abcs bit in semr_2 is 0. when the abcs bit is set to 1, the bit rate is two times. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 673 of 1102 rej09b0365-0100 table 16.7 brr settings for various bit rates (clock synchronous mode) operating frequency p (mhz) 8 10 16 20 25 30 33 35 bit rate (bit/s) n n n n n n n n n n n n n n n n 110 250 3 124 ? ? 3 249 500 2 249 ? ? 3 124 ? ? 3 233 1k 2 124 ? ? 2 249 ? ? 3 97 3 116 3 128 3 136 2.5k 1 199 1 249 2 99 2 124 2 155 2 187 2 205 2 218 5k 1 99 1 124 1 199 1 249 2 77 2 93 2 102 2 108 10k 0 199 0 249 1 99 1 124 1 155 1 187 1 205 1 218 25k 0 79 0 99 0 159 0 199 0 249 1 74 1 82 1 87 50k 0 39 0 49 0 79 0 99 0 124 0 149 0 164 0 174 100k 0 19 0 24 0 39 0 49 0 62 0 74 0 82 0 87 250k 0 7 0 9 0 15 0 19 0 24 0 29 0 32 0 34 500k 0 3 0 4 0 7 0 9 ? ? 0 14 ? ? ? ? 1m 0 1 0 3 0 4 ? ? ? ? ? ? ? ? 2.5m 0 0 * 0 1 ? ? 0 2 ? ? ? ? 5m 0 0 * ? ? ? ? ? ? ? ? [legend] space: setting prohibited. ? : can be set, but there will be error. note: * continuous transmission or reception is not possible. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 674 of 1102 rej09b0365-0100 table 16.8 maximum bit rate with external clock input (clock synchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bit/s) p (mhz) external input clock (mhz) maximum bit rate (bit/s) 8 1.3333 1333333.3 20 3.3333 3333333.3 10 1.6667 1666666.7 25 4.1667 4166666.7 12 2.0000 2000000.0 30 5.0000 5000000.0 14 2.3333 2333333.3 33 5.5000 5500000.0 16 2.6667 2666666.7 35 5.8336 5833625.0 18 3.0000 3000000.0 table 16.9 brr settings for various bit rates (smart card interface mode, n = 0, s = 372) operating frequency p (mhz) 7.1424 10.00 10.7136 13.00 bit rate (bit/sec) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99 operating frequency p (mhz) 14.2848 16.00 18.00 20.00 bit rate (bit/sec) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.66 operating frequency p (mhz) 25.00 30.00 33.00 35.00 bit rate (bit/sec) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 3 12.49 0 3 5.01 0 4 7.59 0 4 1.99 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 675 of 1102 rej09b0365-0100 table 16.10 maximum bit rate for each operating frequency (smart card interface mode, s = 372) p (mhz) maximum bit rate (bit/s) n n p (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 18.00 24194 0 0 10.00 13441 0 0 20.00 26882 0 0 10.7136 14400 0 0 25.00 33602 0 0 13.00 17473 0 0 30.00 40323 0 0 14.2848 19200 0 0 33.00 44355 0 0 16.00 21505 0 0 35.00 47043 0 0 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 676 of 1102 rej09b0365-0100 16.3.10 serial extended mode register (semr_2) semr_2 selects the clock source in asynchronous mode of sci_2. the base clock is automatically specified when the average transfer rate operation is selected. 7 ? undefined r 6 ? undefined r 5 ? undefined r 4 ? undefined r bit bit name initial value r/w 3 abcs 0 r/w 2 acs2 0 r/w 1 acs1 0 r/w 0 acs0 0 r/w bit bit name initial value r/w description 7 to 4 ? undefined r reserved these bits are always read as undefined and cannot be modified. 3 abcs 0 r/w asynchronous mode base clock select (valid only in asynchronous mode) selects the base clock for a 1-bit period. 0: the base clock has a frequency 16 times the transfer rate 1: the base clock has a frequency 8 times the transfer rate section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 677 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 1 0 acs2 acs1 acs0 0 0 0 r/w r/w r/w asynchronous mode clock source select (valid when cke1 = 1 in asynchronous mode) these bits select the clock source for the average transfer rate function. when the average transfer rate function is enabled, the base clock is automatically specified regardless of the abcs bit value. 0000: external clock input 001: 115.152 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 010: 460.606 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 011: 720 kbps of average transfer rate specific to p = 32 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 100: setting prohibited 101: 115.196 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 110: 460.784 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 111: 720 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) the average transfer rate only supports operating frequencies of 10.667 mhz, 16 mhz, and 32 mhz. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 678 of 1102 rej09b0365-0100 16.3.11 serial extended mode register 5 and 6 (semr_5 and semr_6) semr_5 and semr_6 select the clock source in asynchronous mode of sci_5 and sci_6. the base clock is automatically specified when the average transfer rate operation is selected. tmq output in tmr unit 2 and unit 3 can also be set as the serial transfer base clock. figure 16.3 describes the examples of base clock features when the average transfer rate operation is selected. figure 16.4 describes the examples of base clock features when the tmo output in tmr is selected. 7 ? undefined r 6 ? undefined r 5 ? undefined r 4 abcs 0 r/w bit bit name initial value r/w 3 acs3 0 r/w 2 acs2 0 r/w 1 acs1 0 r/w 0 acs0 0 r/w bit bit name initial value r/w description 7 to 5 ? undefined r reserved these bits are always read as undefined and cannot be modified. 4 abcs 0 r/w asynchronous mode base clock select (valid only in asynchronous mode) selects the base clock for a 1-bit period. 0: the base clock has a frequency 16 times the transfer rate 1: the base clock has a frequency 8 times the transfer rate 3 2 1 0 acs3 acs2 acs1 acs0 0 0 0 0 r/w r/w r/w r/w asynchronous mode clock source select these bits select the clock source for the average transfer rate function in the asynchronous mode. when the average transfer rate f unction is enabled, the base clock is automatically specified regardless of the abcs bit value. the average transfer rate only corresponds to 8mhz, 10.667mhz, 12mhz, 16mhz, 24mhz, and 32mhz. no other clock is available. setting of acs3 to acs0 must be done in the asynchronous mode (the c/ a bit in smr = 0) and the external clock input mode (the cke bit i scr = 1). the setting examples are in figures 16.3 and 16.4. (each number in the four-digit number below corresponds to the value in th e bits acs3 to acs0 from left to right respectively.) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 679 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 1 0 acs3 acs2 acs1 acs0 0 0 0 0 r/w r/w r/w r/w 0000: external clock input 0001: 115.152 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0010: 460.606 kbps of average transfer rate specific to p = 10.667 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0011: 921.569 kbps of average transfer rate specific to p = 16 mhz is selected or 460.784 kbps of average transfer rate specific to p = 8mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0100: tmr clock input this setting allows the tmr compare match output to be used as the base clock. the table below shows the correspondence between the sci channels and the compare match output. sci channel tmr unit compare match output sci_5 unit 2 tmo4, tmo5 sci_6 unit 3 tmo6, tmo7 0101: 115.196 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0110: 460.784 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0111: 720 kbps of average transfer rate specific to p = 16 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 680 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 1 0 acs3 acs2 acs1 acs0 0 0 0 0 r/w r/w r/w r/w 1000: 115.132 kbps of average transfer rate specific to p = 24 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1001: 460.526 kbps of average transfer rate specific to p = 24 or mhz or 230.263 kbps of average transfer rate specific to p = 12mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1010: 720 kbps of average transfer rate specific to p = 24 mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1011: 921.053 kbps of average transfer rate specific to p = 24 or mhz or 460.526 kbps of average transfer rate specific to p = 12mhz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1100: 720 kbps of average transfer rate specific to p = 32 mhz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1101: reserved (setting prohibited) 111x: reserved (setting prohibited) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 681 of 1102 rej09b0365-0100 1234567891011 12345678 12 13 14 15 16 17 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 5.333 mhz 3.6848 mhz 123 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 22 4 5 6 7 8 9 10 11 12 13 14 15 16 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 2.667 mhz 1.8424 mhz base clock 10.667 mhz/2 = 5.333 mhz 5.333 mhz (38/55) = 3.6848 mhz (average) 1 bit = base clock 8 * base clock with 460.606-kbps average transfer rate (acs3 to 0 = b'0010) average transfer rate = 3.6848 mhz/8 = 460.606 kbps average error with 460.6 kbps = -0.043% 1 bit = base clock 16 * base clock 10.667 mhz/4= 2.667 mhz 2.667 mhz (38/55) = 1.8424 mhz (average) when = 10.667 mhz base clock with 115.152-kbps average transfer rate (acs3 to 0 = b'0001) average transfer rate = 1.8424 mhz/16 = 115.152 kbps average error with 115.2 kbps = -0.043% note: * the length of one bit varies according to the base clock synchronization. figure 16.3 examples of base clock wh en average transfer rate is selected (1) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 682 of 1102 rej09b0365-0100 12345678910 123 45 678 11 12 13 14 15 16 17 18 19 20 21 23 22 2425 1 2 5 6 7 8 9 101112131415161718 19202122232425 34 8 mhz 7.3725 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 8 mhz 8 mhz 7.3725 mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 12345678 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 5.76 mhz 123 2 mhz 1.8431 mhz 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 base clock 16 mhz/2 = 8 mhz 8 mhz (18/25) = 5.76 mhz (average) base clock with 720-kbps average transfer rate (acs3 to 0 = b'0111) average transfer rate = 5.76 mhz/8 = 720 kbps average error with 720 kbps = 0% base clock 16 mhz/2 = 8 mhz 8 mhz (47/51) = 7.3725 mhz (average) base clock with 921.569-kbps average transfer rate (acs3 to 0 = b'0011) average transfer rate = 7.3725 mhz/8 = 921.569 kbps average error with 921.6 kbps = -0.003% note: * the length of one bit varies according to the base clock synchronization. base clock 16 mhz/2 = 8 mhz 8 mhz (47/51) = 7.3725 mhz (average) 1 bit = base clock 16 * 1 bit = base clock 8 * 1 bit = base clock 8 * base clock with 460.784-kbps average transfer rate (acs3 to 0 = b'0110) average transfer rate = 7.3725 mhz/16 = 460.784 kbps average error with 460.8 kbps = -0.004% 1 bit = base clock 16 * base clock 16 mhz/8 = 2 mhz 2 mhz (47/51) = 1.8431 mhz (average) when = 16 mhz base clock with 115.196-kbps average transfer rate (acs3 to 0 = b'0101) average transfer rate = 1.8431 mhz/16 = 115.196 kbps average error with 115.2 kbps = -0.004% figure 16.3 examples of base clock wh en average transfer rate is selected (2) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 683 of 1102 rej09b0365-0100 1 2 3 4 5 6 7 8 9 101112131415161718192021 23 22 2425 1 2 5 6 7 8 9 101112131415161718 19202122232425 3 4 12 mhz 5.76 mhz 123 3 mhz 1.8421 mhz 4567891011121314151617 1 18 19 20 21 23 22 24 25 26 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 28 29 123 12 mhz 7.3684 mhz 4567891011121314151617 1 18 19 20 21 23 22 24 25 26 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 28 29 123 12 mhz 7.3684 mhz 4567891011121314151617 1 18 19 20 21 23 22 24 25 26 23 45 67 8 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 28 29 base clock 24 mhz/2 = 12 mhz 12 mhz (12/25) = 5.76 mhz (average) base clock with 720-kbps average transfer rate (acs3 to 0 = b'1010) average transfer rate = 5.76 mhz/8= 720 kbps average error with 720 kbps = 0% base clock 24 mhz/2 = 12 mhz 12 mhz (35/57) = 7.3684 mhz (average) base clock with 921.053-kbps average transfer rate (acs3 to 0 = b'1011) average transfer rate = 7.3684 mhz/8= 921.053 kbps average error with 921.6 kbps = -0.059% note: * the length of one bit varies according to the base clock synchronization. base clock 24 mhz/2 = 12 mhz 12 mhz (35/57) = 7.3684 mhz (average) 1 bit = base clock 16 * 1 bit = base clock 8 * 1 bit = base clock 8 * base clock with 460.526-kbps average transfer rate (acs3 to 0 = b'1001) average transfer rate = 7.3684 mhz/16 = 460.526 kbps average error with 921.6 kbps = -0.059% 1 bit = base clock 16 * base clock 24 mhz/8 = 3 mhz 3 mhz (35/57) = 1.8421 mhz (average) when = 24 mhz base clock with 115.132-kbps average transfer rate (acs3 to 0 = b'1000) average transfer rate =1.8421 mhz/16 = 115.132 kbps average error with 115.2 kbps = -0.059% figure 16.3 examples of base clock wh en average transfer rate is selected (3) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 684 of 1102 rej09b0365-0100 base clock tmo4 output = 4 mhz clock enable tmo5 output sck5 base clock = 4 mhz 3/4 = 3 mhz (average) 1 bit = base clock 16 average transfer rate = 3 mhz/16 = 187.5 kbps example when tmr clock input is used in sci_5 187.5-kbps average transfer rate is generated by tmr when = 32 mhz (1) tmo4 is set as a base clock and generates 4 mhz. (2) tmo5 is set as tcnt_4 compare match count and generates a clock enable multiplied by 3/4. the average transfer rate will be 3 mhz/16 = 187.5 kbps. tmr and sci settings: tcr_4 = h'09 (tcnt4 cleared by tcora_4 compare match, tcnt4 incremented at rising edge of p /2) tccr_4 = h'01 tcr_5 = h'0c (tcnt5 cleared by tcora_5 compare match, tcnt5 incremented by tcnt_4 compare match a) tccr_5 = h'00 tcsr_4 = h'09 (0 output on tcora_4 compare match, 1 output on tcorb_4 compare match) tcsr_5 = h'09 (0 output on tcora_5 compare match, 1 output on tcorb_5 compare match) tcnt_4 = tcnt_5 = 0 tcora_4 = h'03, tcorb_4 = h'01 tcora_5 = h'03, tcorb_5 = h'00 semr_5 = h'04 when sci_6 is used, set tmo6 as a base clock and tmo7 as a clock enable. clock enable base clock tmr (unit 2) tmo5 tmo4 sci_5 sck5 123412341234123412341234123 123 123 123 123 123 123 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 4 4 mhz 3 mhz figure 16.4 example of average transf er rate setting when tmr clock is input section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 685 of 1102 rej09b0365-0100 16.3.12 irda control register (ircr) ircr selects the function of sci_5. 7 ire 0 r/w 6 ircks2 0 r/w 5 ircks1 0 r/w 4 ircks0 0 r/w bit bit name initial value r/w 3 irtxinv 0 r/w 2 irrxinv 0 r/w 1 ? 0 ? 0 ? 0 ? bit bit name initial value r/w description 7 ire 0 r/w irda enable* sets the sci_5 i/o to normal sci or irda. 0: txd5/irtxd and rxd5/irrxd pins operate as txd5 and rxd5. 1: txd5/irtxd and rxd5/irrxd pins are operate as irtxd and irrxd. 6 5 4 irck2 irck1 irck0 0 0 0 r/w r/w r/w irda clock select 2 to 0 sets the pulse width of high state at encoding the irtxd output pulse when the irda function is enabled. 000: pulse-width = b 3/16 (bit rate 3/16) 001: pulse-width = p /2 010: pulse-width = p /4 011: pulse-width = p /8 100: pulse-width = p /16 101: pulse-width = p /32 110: pulse-width = p /64 111: pulse-width = p /128 3 irtxinv 0 r/w irtx data invert this bit specifies the inversion of the logic level in irtxd output. when inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: outputs the transmission data as it is as irtxd output 1: outputs the inverted transmission data as irtxd output section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 686 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 irrxinv 0 r/w irrx data invert this bit specifies the inversion of the logic level in irrxd output. when inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: uses the irrxd input data as it is as receive data. 1: uses the inverted irrxd input data as receive data. 1, 0 ? all 0 ? reserved these bits are always read as 0. it should not be set to 0. note: * the irda function should be used when the abcs bit in semr_5 is set to 0 and the acs3 to acs0 bits in semr_5 and semr_6 are set to b'0000. 16.4 operation in asynchronous mode figure 16.5 shows the general format for asynchronous serial communications. one frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). in asynchronous serial comm unication, the communication line is usually held in the mark state (high level). the sci monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. insi de the sci, the transmitter and receiver are independent units, en abling full-duplex communications . both the transmitter and the receiver also have a double-buffered structure, so that data can be r ead or written during transmission or reception, enabling con tinuous data transmission and reception. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 16.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 687 of 1102 rej09b0365-0100 16.4.1 data transfer format table 16.11 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, see section 16.5, multiprocessor communication function. table 16.11 serial transfer formats (asynchronous mode) s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop chr pe mp stop 00 00 00 01 01 00 01 01 10 00 10 01 11 00 11 01 0? 10 0? 11 1? 10 1? 11 [legend] s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 688 of 1102 rej09b0365-0100 16.4.2 receive data sampling timing and recept ion margin in asynchronous mode in asynchronous mode, the sci operates on a base clock with a frequency of 16 times* the bit rate. in reception, the sci samples the falling edge of the start bit using the base clock, and performs internal synchronization. since recei ve data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each bit, as shown in figure 16.6. thus the reception margin in asynchronous mode is determined by formula (1) below. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f ) | 100 [%] ... formula (1) 2n 1 n | d ? 0.5 | m: reception margin n: ratio of bit rate to clock (when abcs = 0, n = 16. when abcs = 1, n = 8.) d: duty cycle of clock (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock frequency deviation [legend] assuming values of f = 0 and d = 0.5 in formula (1), the receptio n margin is determined by the formula below. m = ( 0.5 ? ) 100 [%] = 46.875% 2 16 1 however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 16.6 receive data sampling timing in asynchronous mode note: * this is an example when the abcs bit in semr_2, 5, and 6 is 0. when the abcs bit is 1, a frequency of 8 times the bit rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 689 of 1102 rej09b0365-0100 16.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input to the sck pin can be selected as the sci's transfer clock, accor ding to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. when an external clock is input to the sck pin, the clock frequency should be 16 times the bit rate (when abcs = 0) and 8 times the bit rate (when abcs = 1). in addition, when an external cl ock is specified, the average transf er rate or the base clock of tmr_4 to tmr_7 can be selected by the acs3 to acs0 bits in semr_5 and semr_6. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 16.7. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 sck txd figure 16.7 phase relation between output clock and transmit data (asynchronous mode) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 690 of 1102 rej09b0365-0100 16.4.4 sci initializatio n (asynchronous mode) before transmitting and receiving data, first clear th e te and re bits in scr to 0, then initialize the sci as described in a sample flowchart in figure 16.8 when the op erating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the rdrf, per, fer, and orer flags, or rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 691 of 1102 rej09b0365-0100 16.4.5 serial data transmission (asynchronous mode) figure 16.9 shows an example of the operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a txi interrupt request is generated. because the txi interrup t processing routine writes the ne xt transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the next transmit data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 16.10 shows a sample flowchart for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt processing routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 16.9 example of operation fo r transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 692 of 1102 rej09b0365-0100 no section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 693 of 1102 rej09b0365-0100 16.4.6 serial data recep tion (asynchronous mode) figure 16.11 shows an example of the operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a start bit is detect ed, performs internal synchronization, stores receive data in rs r, and checks the parity bit and stop bit. 2. if an overrun error (when reception of the next data is completed while the rdrf flag in ssr is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error (when the stop bit is 0) is detected, the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception finishes successfu lly, the rdrf bit in ssr is se t to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interr upt processing routine reads th e receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine rxi interrupt request generated figure 16.11 example of sci operation for reception (example with 8-bit data, parity, one stop bit) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 694 of 1102 rej09b0365-0100 table 16.12 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains it s state before receiving data. reception cannot be resumed while a receive error flag is se t to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 16.12 shows a sample flowchart for serial data reception. table 16.12 ssr status flag s and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the stat e it had before data reception. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 695 of 1102 rej09b0365-0100 yes section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 696 of 1102 rej09b0365-0100 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 697 of 1102 rej09b0365-0100 16.5 multiprocessor communication function use of the multiprocessor communicat ion function enables data transfer to be performed among a number of processors sharin g communication lines by means of asynchronous serial communications using the multipr ocessor format, in which a mult iprocessor bit is added to the transfer data. when multiprocessor communicati on is carried out, each receiving station is addressed by a unique id code. the serial communi cation cycle consists of two component cycles: an id transmission cycle which sp ecifies the receiving station, an d a data transmission cycle for the specified receiving station. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 16.13 shows an example of inte r-processor communicat ion using the multiprocessor format. the transmitting station first sends data which include s the id code of the receiving station and a multiprocessor bit set to 1. it then transmits transmit data added with a multiprocessor bit cleared to 0. the receiving statio n skips data until data with a 1 multip rocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving st ation compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and orer in ssr to 1 are prohibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, th e mpb bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is invalid. all other bit settings are the same as those in no rmal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 698 of 1102 rej09b0365-0100 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) communication line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [legend] mpb: multiprocessor bit figure 16.13 example of communica tion using multip rocessor format (transmission of data h'aa to receiving station a) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 699 of 1102 rej09b0365-0100 16.5.1 multiprocessor seri al data transmission figure 16.14 shows a sample flowchart for multip rocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 700 of 1102 rej09b0365-0100 16.5.2 multiprocessor s erial data reception figure 16.16 shows a sample flowchart for multiproces sor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 16.15 shows an example of sci operatio n for multiprocessor format reception. mpie rdr value 0d0d1 d71 1 0d0d1 d7 01 1 1 data (id1) start bit mpb stop bit start bit data (data 1) mpb stop bit data (id2) start bit stop bit start bit data (data 2) stop bit rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine if not this station's id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station's id mpie rdr value 0d0d1 d71 1 0d0d1 d7 01 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine matches this station's id, so reception continues, and data is received in rxi interrupt processing routine mpie bit set to 1 again id2 (b) data matches station's id data 2 id1 mpie = 0 mpie = 0 figure 16.15 example of sc i operation for reception (example with 8-bit data, multiprocessor bit, one stop bit) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 701 of 1102 rej09b0365-0100 yes section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 702 of 1102 rej09b0365-0100 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 703 of 1102 rej09b0365-0100 16.6 operation in clock synchronous mode figure 16.17 shows the general format for clock synchronous communications. in clock synchronous mode, data is transmitted or received in synchronization with clock pulses. one character in transfer data consists of 8-bit data. in data transmission, the sci outputs data from one falling edge of the synchronization clock to the next. in data rece ption, the sci receives data in synchronization with the rising edge of the synchronization clock. after 8-bit data is output, the transmission line holds the msb output state. in clock synchronous mode, no parity bit or multiprocessor bit is adde d. inside the sci, the transmitte r and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so th at the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. don't care don't care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * holds a high level except during continuous transfer. figure 16.17 data format in clock synchronous communica tion (lsb-first) 16.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to th e setting of the cke1 and cke0 bits in scr. when the sci is operated on an internal clock, the synchronization clock is output from the sck pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. note that in the case of reception only, the sync hronization clock is output until an ov errun error occurs or until the re bit is cleared to 0. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 704 of 1102 rej09b0365-0100 16.6.2 sci initialization (clock synchronous mode) before transmitting and receiving data, first clear th e te and re bits in scr to 0, then initialize the sci as described in a sample flowchart in figure 16.18. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change. when the te bit is cleared to 0, the tdre flag is set to 1. however, clearing the re bit to 0 does not initialize the rdrf, per, fer, and orer flags, or rdr. wait section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 705 of 1102 rej09b0365-0100 16.6.3 serial data transmission (clock synchronous mode) figure 16.19 shows an example of the operation for transmission in clock synchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a txi interrupt request is generated. because the txi interrup t processing routine writes the ne xt transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the txd pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the last bit. 5. if the tdre flag is cleared to 0, the next tr ansmit data is transferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the txd pin retains the output state of the last bit. if the teie bit in s cr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 16.20 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (o rer, fer, or per) is set to 1. make sure to clear the receive error flags to 0 be fore starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 706 of 1102 rej09b0365-0100 transfer direction bit 0 serial data synchronization clock 1 frame tdre tend data written to tdr and tdre flag cleared to 0 in txi interrupt processing routine txi interrupt request generated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request generated tei interrupt request generated figure 16.19 example of operation for transmission in clock synchronous mode no section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 707 of 1102 rej09b0365-0100 16.6.4 serial data reception (clock synchronous mode) figure 16.21 shows an example of sci operation for reception in clock synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, an d stores the receive data in rsr. 2. if an overrun error (when reception of the next data is completed while the rdrf flag in ssr is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if reception finishes successfu lly, the rdrf bit in ssr is se t to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interr upt processing routine reads th e receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. bit 7 serial data synchronization clock 1 frame rdrf orer eri interrupt request generated by overrun error rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine rxi interrupt request generated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 16.21 example of operation fo r reception in clock synchronous mode transfer cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming r eception. figure 16.22 shows a sample flowchart for serial data reception. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 708 of 1102 rej09b0365-0100 yes section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 709 of 1102 rej09b0365-0100 yes section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 710 of 1102 rej09b0365-0100 16.7 operation in smart card interface mode the sci supports the smart card interface, sup porting the iso/ie c 7816-3 (identification card) standard, as an extended serial communications interface functio n. smart card interface mode can be selected using the appropriate register. 16.7.1 sample connection figure 16.24 shows a sample conn ection between the smart card and this lsi. as in the figure, since this lsi communicat es with the smart card using a single transmission line, interconnect the txd and rxd pins and pull up the data transmission line to v cc using a resistor. setting the re and te bits to 1 with the smart card not connected enables closed transmission/reception allowing self diagnosis. to supply the smart card with the clock pulses generated by the sci, input the sck pin output to the clk pin of the smart card. a reset signal can be supplied via the output port of this lsi. txd rxd this lsi v cc i/o main unit of the device to be connected smart card data line clk rst sck rx (port) clock line reset line figure 16.24 pin connectio n for smart card interface section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 711 of 1102 rej09b0365-0100 16.7.2 data format (except in block transfer mode) figure 16.25 shows the data transfer formats in smart ca rd interface mode. ? one frame contains 8-bit data and a parity bit in asynchronous mode. ? during transmission, at least 2 et u (elementary time unit: time requ ired for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. ? if a parity error is detected during reception, a lo w error signal is output for 1 etu after 10.5 etu has passed from the start bit. ? if an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. ds d0 d1 d2 d3 d4 d5 d6 d7 dp in normal transmission/reception output from the transmitting station ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error is generated output from the transmitting station de output from the receiving station [legend] ds: start bit d0 to d7: data bits dp: parity bit de: error signal figure 16.25 data formats in no rmal smart card interface mode for communications with the smart cards of the direct convention and inverse convention types, follow the procedure below. ds azzazz z za a (z) (z) state d0 d1 d2 d3 d4 d5 d6 d7 dp figure 16.26 direct conv ention (sdir = sinv = o/ e = 0) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 712 of 1102 rej09b0365-0100 for the direct convention type, logic levels 1 and 0 correspond to states z and a, respectively, and data is transferred with lsb-first as the start character, as shown in figure 16.26. therefore, data in the start character in the figu re is h'3b. when using the direct convention type, write 0 to both the sdir and sinv bits in scmr. write 0 to the o/ e bit in smr in order to use even parity, which is prescribed by the smart card standard. ds azzaaa z aa a (z) (z) state d7 d6 d5 d4 d3 d2 d1 d0 dp figure 16.27 inverse conv ention (sdir = sinv = o/ e = 1) for the inverse convention type, logic levels 1 and 0 correspond to states a and z, respectively and data is transferred with msb-first as the star t character, as shown in fi gure 16.27. therefore, data in the start character in the figure is h'3f. when using the inverse convention type, write 1 to both the sdir and sinv bits in scmr. the parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, an d corresponds to state z. since the sniv bit of this lsi only inverts data bits d7 to d0, write 1 to the o/ e bit in smr to invert the parity bit in both transmission and reception. 16.7.3 block transfer mode block transfer mode is different from normal sm art card interface mode in the following respects. ? even if a parity error is detect ed during reception, no error signal is output. since the per bit in ssr is set by error detection, clear the per bit before receiving the parity bit of the next frame. ? during transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. ? since the same data is not re-transmitted during transmission, the tend flag is set 11.5 etu after transmission start. ? although the ers flag in block transfer mode di splays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 713 of 1102 rej09b0365-0100 16.7.4 receive data sampling timing and rece ption margin only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. in this mode , the sci can operate on a base clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the bcp1 and bcp0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mo de). at reception, the falling edge of the start bit is sampled using the base clock in order to perform internal synchronization. receive data is sampled on th e 16th, 32nd, 186th and 128t h rising edges of the base clock so that it can be latched at the mi ddle of each bit as shown in figure 16.28. the reception margin here is determin ed by the following formula. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f ) | 100% 2n 1 n | d ? 0.5 | m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, 256) d: duty cycle of clock (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation [legend] assuming values of f = 0, d = 0.5, and n = 372 in the above formula, the reception margin is determined by the formula below. m = ( 0.5 ? ) 100% = 49.866% 2 372 1 internal basic clock 372 clock cycles 186 clock cycles receive data (rxd) synchronization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 16.28 receive data sampling timing in smart card interface mode (when clock frequency is 372 times the bit rate) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 714 of 1102 rej09b0365-0100 16.7.5 initialization before transmitting and receiving data, initia lize the sci using the following procedure. initialization is also necessary be fore switching from transmission to reception and vice versa. 1. clear the te and re bits in scr to 0. 2. set the icr bit of the corresponding pin to 1. 3. clear the error flags ers, per, and orer in ssr to 0. 4. set the gm, blk, o/ e , bcp1, bcp0, cks1, and cks0 bits in smr appropriately. also set the pe bit to 1. 5. set the smif, sdir, and sinv bits in scmr appropriately. when the ddr corresponding to the txd pin is cleared to 0, the txd and rxd pins are changed from port pins to sci pins, placing the pins into high impedance state. 6. set the value corresponding to the bit rate in brr. 7. set the cke1 and cke0 bits in scr appropri ately. clear the tie, rie, te, re, mpie, and teie bits to 0 simultaneously. when the cke0 bit is set to 1, the sck pin is allowed to output clock pulses. 8. set the tie, rie, te, and re bits in scr appropriately after waiti ng for at least a 1-bit interval. setting the te and re bits to 1 simultaneously is prohibited except for self diagnosis. to switch from reception to transmission, first veri fy that reception has co mpleted, then initialize the sci. at the end of initialization, re and te should be set to 0 and 1, respectively. reception completion can be verified by reading the rdrf, per, or orer flag. to switch from transmission to reception, first verify that transm ission has completed, then initialize the sci. at the end of initialization, te and re should be set to 0 and 1, respectively. transmission completion can be verified by reading the tend flag. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 715 of 1102 rej09b0365-0100 16.7.6 data transmission (except in block transfer mode) data transmission in smart card interface mode (exc ept in block transfer mode) is different from that in normal serial communicati ons interface mode in that an error signal is sampled and data can be re-transmitted. figure 16.29 shows the da ta re-transfer operation during transmission. 1. if an error signal from the receiving end is sampled after one frame of data has been transmitted, the ers bit in ssr is set to 1. here , an eri interrupt request is generated if the rie bit in scr is set to 1. clear the ers bit to 0 before the next parity bit is sampled. 2. for the frame in which an error signal is receiv ed, the tend bit in ssr is not set to 1. data is re-transferred from tdr to tsr allo wing automatic data retransmission. 3. if no error signal is returned from the receivi ng end, the ers bit in ssr is not set to 1. 4. in this case, one frame of data is determined to have been transmitted including re-transfer, and the tend bit in ssr is set to 1. here, a txi in terrupt request is generated if the tie bit in scr is set to 1. writing transmit data to tdr starts transmission of the next data. figure 16.31 shows a sample flowchart for transmission. all the processing steps are automatically performed using a txi interrupt request to activate the dtc or dmac. in transmission, the tend and tdre flags in ssr are simultaneously set to 1, thus generating a txi interrupt request if the tie bit in scr has been set to 1. this activates the dtc or dmac by a txi request thus allowing transfer of transmit da ta if the txi interrupt request is specified as a source of dtc or dmac activation beforehand. the tdre and tend flags are automatically cleared to 0 at data transfer by the dtc or dmac. if an error occurs, the sci automatically re- transmits the same data. during re-transmission, tend remains as 0, thus not activating the dtc or dmac. therefore, the sci and dtc or dmac automatically transmit the specified number of bytes, including re-transmission in the case of er ror occurrence. however, the ers flag is not automatically cleared; the ers flag must be cleared by previously setting the rie bit to 1 to enable an eri interrupt request to be generated at error occurrence. when transmitting/receiving data using the dtc or dmac, be sure to set and enable the dtc or dmac prior to making sci settings. for dtc or dmac settings, see section 10, data transfer controller (dtc) and section 9, dma controller (dmac). section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 716 of 1102 rej09b0365-0100 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds (n + 1) th transfer frame retransfer frame nth transfer frame tdre tend [1] fer/ers transfer from tdr to tsr transfer from tdr to tsr transfer from tdr to tsr [2] [4] [3] figure 16.29 data re-transfer op eration in sci transmission mode note that the tend flag is set in different timings depending on the gm bit setting in smr. figure 16.30 shows the tend flag set timing. ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5 etu txi (tend interrupt) 11.0 etu de guard time gm = 0 gm = 1 [legend] ds: start bit d0 to d7: data bits dp: parity bit de: error signal figure 16.30 tend flag set timing during transmission section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 717 of 1102 rej09b0365-0100 initialization no yes clear te bit in scr to 0 start transmission start no no no yes yes yes yes no end write data to tdr and clear tdre flag in ssr to 0 error processing error processing tend = 1 ? all data transmitted? tend = 1 ? ers = 0 ? ers = 0 ? figure 16.31 sample transmission flowchart section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 718 of 1102 rej09b0365-0100 16.7.7 serial data reception (except in block transfer mode) data reception in smart card interface mode is si milar to that in normal serial communications interface mode. figure 16.32 shows the data re-transfer operatio n during reception. 1. if a parity error is detected in receive data , the per bit in ssr is set to 1. here, an eri interrupt request is generated if the rie bit in scr is set to 1. clear the per bit to 0 before the next parity bit is sampled. 2. for the frame in which a parity error is de tected, the rdrf bit in ssr is not set to 1. 3. if no parity error is detected, the per bit in ssr is not set to 1. 4. in this case, data is determined to have be en received successfully, and the rdrf bit in ssr is set to 1. here, an rxi interrupt request is generated if the rie bit in scr is set to 1. figure 16.33 shows a samp le flowchart for reception. all the processing steps are automatically performed using an rxi interrupt request to activ ate the dtc or dmac. in reception, setting the rie bit to 1 allows an rxi interrupt request to be generated when the rdrf flag is set to 1. this activates the dtc or dmac by an rxi request thus allowing transfer of receive data if the rxi interrupt request is specified as a source of dt c or dmac activation beforehand. the rdrf flag is automatically cleared to 0 at data transfer by the dtc or dmac. if an error occurs during reception, i.e., either the orer or per flag is set to 1, a tran smit/receive error interrupt (eri) request is generated and the error flag must be cleared. if an error occurs, the dtc or dmac is not activated and receive data is skipped, therefor e, the number of bytes of receive data specified in the dtc or dmac is transferred. even if a pa rity error occurs and the per bit is set to 1 in reception, receive data is tr ansferred to rdr, thus allowing the data to be read. note: for operations in block transfer mode, see section 16.4, operation in asynchronous mode. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds (n + 1) th transfer frame retransfer frame nth transfer frame rdrf [1] per [2] [3] [4] figure 16.32 data re-transfer operation in sci reception mode section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 719 of 1102 rej09b0365-0100 initialization read data from rdr and clear rdrf flag in ssr to 0 clear re bit in scr to 0 start reception start error processing no no no yes yes orer = 0 and per = 0? rdrf = 1 ? all data received? yes figure 16.33 sample reception flowchart 16.7.8 clock output control clock output can be fixed using the cke1 and cke0 bits in scr when the gm bit in smr is set to 1. specifically, the minimum width of a clock pulse can be specified. figure 16.34 shows an example of clock output fixing timing when the cke0 bit is controlled with gm = 1 and cke1 = 0. given pulse width sck cke0 given pulse width figure 16.34 clock output fixing timing section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 720 of 1102 rej09b0365-0100 at power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. ? at power-on to secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. initially, port input is enabled in the high-impedance state. to fix the potential level, use a pull-up or pull-down resistor. 2. fix the sck pin to the specified output using the cke1 bit in scr. 3. set smr and scmr to enable smart card interface mode. set the cke0 bit in scr to 1 to start clock output. ? at mode switching ? at transition from smart card interf ace mode to software standby mode 1. set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the values for the output fixed state in software standby mode. (sci_0, 1, 2, and 4 only) 2. write 0 to the te and re bits in scr to stop transmission/recep tion. simultaneously, set the cke1 bit to the value for the outp ut fixed state in software standby mode. 3. write 0 to the cke0 bit in scr to stop the clock. 4. wait for one cycle of the serial clock. in th e mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. make the transition to software standby mode. ? at transition from smart card interf ace mode to software standby mode 1. clear software standby mode. 2. write 1 to the cke0 bit in scr to start clock output. a clock signal with the appropriate duty cycle is then generated. [1] [2] [3] [4] [5] [7] software standby normal operation normal operation [6] figure 16.35 clock stop and restart procedure section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 721 of 1102 rej09b0365-0100 16.8 irda operation if the irda function is enabled using the ire bit in ircr, the txd5 and rxd5 pins in sci_5 are allowed to encode and decode the waveform based on the irda specifications version 1.0 (function as the irtxd and irrxd pins)*. connecting these pins to the infrared data transceiver achieves infrared data communica tions based on the system defined by the irda specifications version 1.0. in the system defined by the irda specifications version 1.0, communication is started at a transfer rate of 9600 bps, which can be modifi ed later as required. since the irda interface provided by this lsi does not incorporate the capability of automatic modification of the transfer rate, the transfer rate must be modified through programming. figure 16.36 is the irda block diagram. pulse encoder pulse decoder ircr irda sci5 txd txd5/irtxd rxd rxd5/irrxd figure 16.36 irda block diagram note: the irda function should be used when the abcs bit in semr_5 is set to 0 and the acs3 to acs0 bits in semr_5 and semr_6 are set to b'0000. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 722 of 1102 rej09b0365-0100 (1) transmission during transmission, the output signals from the sci (uart frames) are converted to ir frames using the irda interface (see figure 16.37). for serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). the high-level pulse can be selected using the ircks2 to ircks0 bits in ircr. the high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) bit rate or (3/16 bit rate) +1.08 s at maximum. for example, when the frequency of system clock is 20 mhz, a high-level pulse width of 1.6 s can be specified because it is the smallest value in the range greater than 1.41 s. for serial data of level 1, no pulses are output. uart frame data ir frame data 0000 0 11 11 1 0000 0 11 11 1 transmission reception bit cycle pulse width is 1.6 s to 3/16 bit cycle start bit stop bit stop bit start bit figure 16.37 irda transmission and reception (2) reception during reception, ir frames ar e converted to uart frames us ing the irda interface before inputting to sci. 0 is output when the high level pulse is detected while 1 is output when no pulse is detected during one bit period. note that a pulse shorter than the minimum pulse width of 1.41 s is also regarded as a 0 signal. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 723 of 1102 rej09b0365-0100 (3) high-level puls e width selection table 16.13 shows possible settings for bits ircks2 to ircks0 (minimum pulse width), and this lsi's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. table 16.13 ircks2 to ircks0 bit settings operating bit rate (bps) (upper row)/bit interval 3/16 (s) (lower row) frequency 2400 9600 19200 38400 57600 115200 p (mhz) 78.13 19.53 9.77 4.88 3.26 1.63 7.3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.7456 101 101 101 101 101 101 16 101 101 101 101 101 101 17.2032 101 101 101 101 101 101 18 101 101 101 101 101 101 19.6608 101 101 101 101 101 101 20 101 101 101 101 101 101 25 110 110 110 110 110 110 30 110 110 110 110 110 110 33 110 110 110 110 110 110 35 110 110 110 110 110 110 section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 724 of 1102 rej09b0365-0100 16.9 interrupt sources 16.9.1 interrupts in normal seri al communication interface mode table 16.14 shows the interrup t sources in normal serial communications interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt request can activate the dtc or dmac to allow data transfer. the tdre flag is automatically cleared to 0 at data transfer by the dtc or dmac. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri in terrupt request is generate d. an rxi interrupt can activate the dtc or dmac to allow data transfer. the rdrf flag is automatically cleared to 0 at data transfer by the dtc or dmac. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt has priority for acceptance. however, note that if the tdre and tend flags are cl eared to 0 simultaneously by the txi interrupt processing routine, the sci cannot branch to the tei interrupt processing routine later. note that the priority order for interrupts is different between the group of sci_0, 1, 2, 3, and 4 and the group of sci_5 and sci_6. table 16.14 sci interrupt sources (sci_0, 1, 2, 3, and 4) name interrupt source interrupt flag dtc activation dmac activation priority eri receive error orer, fer, or per not possible not possible high rxi receive data full rdrf possible possible txi transmit data empty tdre possible possible tei transmit end tend not possible not possible low section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 725 of 1102 rej09b0365-0100 table 16.15 sci interrupt so urces (sci_5 and sci_6) name interrupt source interrupt flag dtc activation dmac activation priority rxi receive data full rdrf not possible possible high txi transmit data empty t dre not possible possible eri receive error orer, fer, or per not possible not possible tei transmit end tend not possible not possible low 16.9.2 interrupts in smar t card interface mode table 16.16 shows the interrup t sources in smart card interf ace mode. a transmit end (tei) interrupt request cannot be used in this mode. note that the priority order for interrupts is different between the group of sci_0, 1, 2, 3, and 4 and the group of sci_5 and sci_6. table 16.16 sci interrupt sources (sci_0, 1, 2, 3, and 4) name interrupt source interrupt flag dtc activation dmac activation priority eri receive error or error signal detection orer, per, or ers not pos sible not possible high rxi receive data full rdrf possible possible txi transmit data empty tend possible possible low table 16.17 sci interrupt so urces (sci_5 and sci_6) name interrupt source interrupt flag dtc activation dmac activation priority rxi receive data full rdrf not possible possible high txi transmit data empty t dre not possible possible eri receive error or error signal detection orer, per, or ers not possible not possible low section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 726 of 1102 rej09b0365-0100 data transmission/reception usin g the dtc or dmac is also possible in smart card interface mode, similar to in the normal sci mode. in tr ansmission, the tend and tdre flags in ssr are simultaneously set to 1, thus generating a txi interrupt. this activates the dtc or dmac by a txi request thus allowing transfer of transmit data if the txi reque st is specified as a source of dtc or dmac activation beforehand. the tdre an d tend flags are automatically cleared to 0 at data transfer by the dtc or dmac. if an error occurs, the sci automatically re-transmits the same data. during re-transmission, the tend flag remains as 0, thus not activating the dtc or dmac. therefore, the sci and dtc or dmac au tomatically transmit th e specified number of bytes, including re-transmission in the case of er ror occurrence. however, the ers flag in ssr, which is set at error occurrence , is not automatically cleared; th e ers flag must be cleared by previously setting the rie bit in scr to 1 to enable an eri interrupt request to be generated at error occurrence. when transmitting/receiving data using the dtc or dmac, be sure to set and enable the dtc or dmac prior to making sci settings. for dtc or dmac settings, see section 10, data transfer controller (dtc) and section 9, dma controller (dmac). in reception, an rxi interrupt request is generate d when the rdrf flag in ssr is set to 1. this activates the dtc or dmac by an rxi request thus allowing transfer of receive data if the rxi request is specified as a sour ce of dtc or dmac activation beforehand. the rdrf flag is automatically cleared to 0 at da ta transfer by the dtc or dmac . if an error occurs, the rdrf flag is not set but the error flag is set. theref ore, the dtc or dmac is not activated and an eri interrupt request is issued to the cpu instead; the error flag must be cleared. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 727 of 1102 rej09b0365-0100 16.10 usage notes 16.10.1 module stop state setting operation of the sci can be disabled or enabled using the module stop control register. the initial setting is for operation of the sci to be halted. register access is enabled by clearing the module stop state. for details, see section 24, power-down modes. 16.10.2 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the per flag may also be set. note that, since th e sci continues the receive operation even after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 16.10.3 mark state and break detection when the te bit is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by dr and ddr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line in mark state (the state of 1) until te is set to 1, set both ddr and dr to 1. since the te bit is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set ddr to 1 and dr to 0, and then clear th e te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 16.10.4 receive error flags and transmit operations (clock synchronous mode only) transmission cannot be started when a receive error flag (orer, fer, or rer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that the receive error flag s cannot be cleared to 0 even if the re bit is cleared to 0. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 728 of 1102 rej09b0365-0100 16.10.5 relation between writing to tdr and tdre flag the tdre flag in ssr is a status flag which indicat es that transmit data ha s been transferred from tdr to tsr. when the sci tran sfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr irrespective of the tdre flag status. however, if new data is written to tdr when the tdre flag is 0, that is, when the previous data has not been transferred to tsr yet, the previous data in tdr is lost. be sure to write transmit data to tdr after verifying that the tdre flag is set to 1. 16.10.6 restrictions on using dtc or dmac ? when the external clock source is used as a synchronization clock, update tdr by the dmac or dtc and wait for at least five p clock cycles before allowing the transmit clock to be input. if the transmit clock is input within four clock cycles after tdr modification, the sci may malfunction (see figure 16.38). ? when using the dmac or dtc to read rdr, be sure to set the receive end interrupt (rxi) as the dtc or dmac activation source. t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when external clock is supplied, t must be more than four clock cycles. tdre figure 16.38 sample transmission using dtc in clock synchronous mode ? the dtc is not activated by the rxi or txi request by sci_5 or sci6. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 729 of 1102 rej09b0365-0100 16.10.7 sci operations du ring power-down state transmission: before specifying the module stop state or making a transition to software standby mode, stop the transmit operations (te = tie = teie = 0). tsr, tdr, and ssr are reset. the states of the output pins in the module stop state or in software standby mode depend on the port settings, and the pins output a high-level signal after cancellation. if the transition is made during data transmission, the data being transmitted will be undefined. to transmit data in the same transmission mode after cancellation of the power-down state, set the te bit to 1, read ssr, write to tdr, clear tdre in this order, and then start transmission. to transmit data in a different transmission mode, initialize the sci first. figure 16.39 shows a sample flowchart for transition to software standby mode during transmission. figures 16.40 and 16.41 show the port pin states during transition to software standby mode. before specifying the module stop state or making a transition to software standby mode from the transmission mode using dtc transfer, stop all transmit operations (te = tie = teie = 0). setting the te and tie bits to 1 after cancellation se ts the txi flag to star t transmission using the dtc. reception: before specifying the module stop state or making a transition to software standby mode, stop the receive operations (re = 0). rsr, rdr, and ssr are reset. if transition is made during data reception, the data being received will be invalid. to receive data in the same recep tion mode after cancellation of th e power-down state, set the re bit to 1, and then start reception. to receive data in a diffe rent reception mode, initialize the sci first. for using the irda function, set the ire bit in addition to setting the re bit. figure 16.42 shows a sample flowchart for mode transition during reception. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 730 of 1102 rej09b0365-0100 start transmission transmission [1] no no no yes yes yes read tend flag in ssr make transition to software standby mode cancel software standby mode te = 0 initialization te = 1 [2] [3] all data transmitted? change operating mode? tend = 1 [1] data being transmitted is lost halfway. data can be normally transmitted from the cpu by setting the te bit to 1, reading ssr, writing to tdr, and clearing the tdre bit to 0 after clearing software standby mode; however, if the dtc has been activated, the data remaining in the dtc will be transmitted when both the te and tie bits are set to 1. [2] clear the tie and teie bits to 0 when they are 1. [3] setting of the module stop state is included. figure 16.39 sample flowchart for software standby mode transition during transmission te bit sck * output pin txd output pin port input/output port input/output port input/output start stop high output high output transmission start transmission end transition to software standby mode software standby mode canceled sci txd output port port sci txd output figure 16.40 port pin states during software standby mode transition (internal clock, asynchronous transmission) section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 731 of 1102 rej09b0365-0100 te bit sck output pin txd output pin port input/output port input/output port input/output high output * marking output transmission start transmission end transition to software standby mode software standby mode canceled sci txd output port port sci txd output last txd bit retained note: * initialized in software standby mode figure 16.41 port pin states during software standby mode transition (internal clock, clock synchronous transmission) start reception reception [1] no no yes yes read receive data in rdr read rdrf flag in ssr make transition to software standby mode cancel software standby mode re = 0 initialization re = 1 [2] change operating mode? rdrf = 1 [1] data being received will be invalid. [2] setting of the module stop state is included. figure 16.42 sample flowchart for softwa re standby mode transition during reception section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 732 of 1102 rej09b0365-0100 16.11 crc operation circuit the cyclic redundancy check (crc) operatio n circuit detects errors in data blocks. 16.11.1 features the features of the crc operation circuit are listed below. ? crc code generated for any desired data length in an 8-bit unit ? crc operation executed on eight bits in parallel ? one of three generating polynomials selectable ? crc code generation for lsb-first or msb-first communications selectable figure 16.43 shows a block diagram of the crc operation circuit. internal bus crc code generation circuit crccr crcdir crcdor control signal [legend] crccr: crcdir: crcdor: crc control register crc data input register crc data output register figure 16.43 block diagra m of crc operation circuit section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 733 of 1102 rej09b0365-0100 16.11.2 register descriptions the crc operation circuit has the following registers. ? crc control register (crccr) ? crc data input register (crcdir) ? crc data output register (crcdor) (1) crc control register (crccr) crccr initializes the crc operation circuit, switches the operation mode, and selects the generating polynomial. bit bit name initial value r/w 7 dorclr 0 w 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 lms 0 r/w 1 g1 0 r/w 0 g0 0 r/w bit bit name initial value r/w description 7 dorclr 0 w crcdor clear setting this bit to 1 clears crcdor to h'0000. 6 to 3 ? all 0 r reserved the initial value should not be changed. 2 lms 0 r/w crc operation switch selects crc code generation for lsb-first or msb-first communications. 0: performs crc operation for lsb-first communications. the lower byte (bits 7 to 0) is first transmitted when crcdor contents (crc code) are divided into two bytes to be transmitted in two parts. 1: performs crc operation for msb-first communications. the upper byte (bits 15 to 8) is first transmitted when crcdor contents (crc code) are divided into two bytes to be transmitted in two parts. section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 734 of 1102 rej09b0365-0100 bit bit name initial value r/w description 1 0 g1 g0 0 0 r/w r/w crc generating polynomial select: selects the polynomial. 00: reserved 01: x 8 + x 2 + x + 1 10: x 16 + x 15 + x 2 + 1 11: x 16 + x 12 + x 5 + 1 (2) crc data input register (crcdir) crcdir is an 8-bit readable/writable register, to which the bytes to be crc-operated are written. the result is obtained in crcdor. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w (3) crc data output register (crcdor) crcdor is a 16-bit readable/writable register th at contains the result of crc operation when the bytes to be crc-operated are written to cr cdir after crcdor is cleared. when the crc operation result is additionally written to the bytes to which crc operation is to be performed, the crc operation result will be h'0000 if the data c ontains no crc error. when bits 1 and 0 in crccr (g1 and g0 bits) are set to 0 and 1, respectivel y, the lower byte of this register contains the result. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 735 of 1102 rej09b0365-0100 16.11.3 crc operatio n circuit operation the crc operation circuit generates a crc code for lsb-first/msb-first communications. an example in which a crc code for hexadecimal data h'f0 is generated using the x 16 + x 12 + x 5 + 1 polynomial with the g1 and g0 bits in crccr set to b'11 is shown below. crccr crcdorh crcdorl crcdor clearing 1. write h'83 to crccr 1 7 0 0 0 00 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 2. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 1 0 11 1 1 0 0 0 1 11 1 crc code = h'f78f crc code output data 3. read from crcdor 7 7 7 fff0 8 7 00 0 4. serial transmission (lsb first) 1 1 1 1 0 1 1 1 1 0 0 0 1 11 1 1 1 1 1 0 00 0 figure 16.44 lsb-first data transmission crccr crcdorh crcdorl crcdor clearing 1. write h'87 to crccr 1 7 0 0 0 01 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 2. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 crc code = h'ef1f crc code output data 3. read from crcdor 7 7 0 ff1f e 7 00 0 4. serial transmission (msb first) 1 1 1 1 0 0 0 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 figure 16.45 msb-first data transmission section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 736 of 1102 rej09b0365-0100 crccr crcdorh crcdorl crcdor clearing 2. write h'83 to crccr 1 7 0 0 0 00 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 3. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 1 0 11 1 1 0 0 0 1 11 1 crcdir crcdorh crcdorl crc code generation 4. write h'8f to crcdir 1 7 0 0 0 11 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 1 1 1 1 0 11 1 crcdir crcdorh crcdorl crc code generation 5. write h'f7 to crcdir 1 1 1 1 0 11 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crc code = h'0000 no error crc code input data 6. read from crcdor 7 7 7 fff0 8 7 00 0 1. serial reception (lsb first) 1 1 1 1 0 1 1 1 1 0 0 0 1 11 1 1 1 1 1 0 00 0 figure 16.46 lsb-fi rst data reception section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 737 of 1102 rej09b0365-0100 crccr crcdorh crcdorl crcdor clearing 2. write h'83 to crccr 1 7 0 0 0 01 0 7 0 7 0 7 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 3. write h'f0 to crcdir 1 1 1 1 0 00 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 crcdir crcdorh crcdorl crc code generation 4. write h'ef to crcdir 1 7 1 1 0 11 0 7 0 7 0 7 0 1 1 0 0 0 1 1 11 1 0 0 0 0 0 00 0 crcdir crcdorh crcdorl crc code generation 5. write h'1f to crcdir 0 0 0 1 1 11 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 crc code = h'0000 no error crc code input data 6. read from crcdor 7 7 0 ff1f e 7 00 0 1. serial reception (msb first) 1 1 1 1 0 0 0 0 1 1 1 0 1 11 1 0 0 0 1 1 11 1 figure 16.47 msb-first data reception section 16 serial communicati ons interface (sci, irda, crc) rev. 1.00 sep. 13, 2007 page 738 of 1102 rej09b0365-0100 16.11.4 note on crc operation circuit note that the sequence to transmit the crc code differs between lsb-first transmission and msb-first transmission. crcdir crcdorh crcdorl 1. crc code generation 2. transmission data (i) lsb-first transmission crc code generation after specifying the operation method, write data to crcdir in the sequence of (1) (2) (3) (4). crc code output 7 7 70 0 0 0 70 00 0 777 7 (1) (2) (3) (4) (5) (6) (1) (2) (3) (4) (6) (5) (ii) msb-first transmission crc code output 77 000000 777 7 (6) (5) (4) (3) (2) (1) figure 16.48 lsb-first a nd msb-first transmit data section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 739 of 1102 rej09b0365-0100 section 17 i 2 c bus interface 2 (iic2) this lsi has a four-channel i 2 c bus interface. the i 2 c bus interface conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. figure 17.1 shows the block diagram of the i 2 c bus interface 2. figure 17.2 shows an example of i/o pin connections to external circuits. 17.1 features ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmi ssion/reception can be performed. ? start and stop conditions generated automatically in master mode ? selection of acknowledge output levels when receiving ? automatic loading of acknowledge bit when transmitting ? bit synchronization/wait function in master mode, the state of th e serial clock (scl) is monitored per bit, and the timing is synchronized automatically. if transmission or reception is not yet possible, drive the scl signal low until preparations are completed ? six interrupt sources transmit-data-empty (including slave-address match), tran smit-end, receive-data-full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, the scl and serial data (sda) pins function as nmos open-drain outputs. a voltage of 5v can be input to unit 1. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 740 of 1102 rej09b0365-0100 scl iccra transfer clock generator address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccrb icmr icsr iceir icdrr icdrs icdrt i 2 c bus control register a i 2 c bus control register b i 2 c mode register i 2 c status register i 2 c interrupt enable register i 2 c transmit data register i 2 c receive data register i 2 c bus shift register slave address register [legend] iccra: iccrb: icmr: icsr: icier: icdrt: icdrr: icdrs: sar: sar sda internal data bus figure 17.1 block diagram of i 2 c bus interface 2 section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 741 of 1102 rej09b0365-0100 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 17.2 connections to the external circuit by the i/o pins 17.2 input/output pins table 17.1 shows the pin configuration of the i 2 c bus interface 2. table 17.1 pin configuration of the i 2 c bus interface 2 channel abbreviation i/o function 0 0 scl0 i/o channel 0 serial clock i/o pin sda0 i/o channel 0 serial data i/o pin 1 scl1 i/o channel 1 serial clock i/o pin sda1 i/o channel 1 serial data i/o pin 1 2 scl2 i/o channel 2 serial clock i/o pin sda2 i/o channel 2 serial data i/o pin 3 scl3 i/o channel 3 serial clock i/o pin sda3 i/o channel 3 serial data i/o pin note: the pin symbols are represented as scl an d sda; channel numbers are omitted in this manual. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 742 of 1102 rej09b0365-0100 17.3 register descriptions the i 2 c bus interface 2 has the following registers. unit 0: ? channel 0: ? i 2 c bus control register a_0 (iccra_0) ? i 2 c bus control register b_0 (iccrb_0) ? i 2 c bus mode register_0 (icmr_0) ? i 2 c bus interrupt enable register_0 (icier_0) ? i 2 c bus status register_0 (icsr_0) ? slave address register_0 (sar_0) ? i 2 c bus transmit data register_0 (icdrt_0) ? i 2 c bus receive data register_0 (icdrr_0) ? i 2 c bus shift register_0 (icdrs_0) ? channel 1: ? i 2 c bus control register a_1 (iccra_1) ? i 2 c bus control register b_1 (iccrb_1) ? i 2 c bus mode register_1 (icmr_1) ? i 2 c bus interrupt enable register_1 (icier_1) ? i 2 c bus status register_1 (icsr_1) ? slave address register_1 (sar_1) ? i 2 c bus transmit data register_1 (icdrt_1) ? i 2 c bus receive data register_1 (icdrr_1) ? i 2 c bus shift register_1 (icdrs_1) unit 1: ? channel 2: ? i 2 c bus control register a_2 (iccra_2) ? i 2 c bus control register b_2 (iccrb_2) ? i 2 c bus mode register_2 (icmr_2) ? i 2 c bus interrupt enable register_2 (icier_2) ? i 2 c bus status register_2 (icsr_2) ? slave address register_2 (sar_2) section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 743 of 1102 rej09b0365-0100 ? i 2 c bus transmit data register_2 (icdrt_2) ? i 2 c bus receive data register_2 (icdrr_2) ? i 2 c bus shift register_2 (icdrs_2) ? channel 3: ? i 2 c bus control register a_3 (iccra_3) ? i 2 c bus control register b_3 (iccrb_3) ? i 2 c bus mode register_3 (icmr_3) ? i 2 c bus interrupt enable register_3 (icier_3) ? i 2 c bus status register_3 (icsr_3) ? slave address register_3 (sar_3) ? i 2 c bus transmit data register_3 (icdrt_3) ? i 2 c bus receive data register_3 (icdrr_3) ? i 2 c bus shift register_3 (icdrs_3) section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 744 of 1102 rej09b0365-0100 17.3.1 i 2 c bus control register a (iccra) iccra enables or disables i 2 c bus interface, controls transmi ssion or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w 7 ice 0 r/w 6 rcvd 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 cks3 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted 1: this bit is enabled for transfer operations (scl and sda pins are bus drive state) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select when arbitration is lost in master mode, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. operating modes are described below according to mst and trs combination. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits are valid only in master mode. make setting according to the required transfer rate. for details on the transfer rate, see table 17.2. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 745 of 1102 rej09b0365-0100 table 17.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock p = 8 mhz p = 10 mhz p = 20 mhz p = 25 mhz p = 33 mhz 0 0 0 0 p /28 286 khz 357 khz 714 khz 893 khz 1179 khz 1 p /40 200 khz 250 khz 500 khz 625 khz 825 khz 1 0 p /48 167 khz 208 khz 417 khz 521 khz 688 khz 1 p /64 125 khz 156 khz 313 khz 391 khz 516 khz 1 0 0 p /168 47.6 khz 59.5 khz 119 khz 149 khz 196 khz 1 p /100 80.0 khz 100 khz 200 khz 250 khz 330 khz 1 0 p /112 71.4 khz 89.3 khz 179 khz 223 khz 295 khz 1 p /128 62.5 khz 78.1 khz 156 khz 195 khz 258 khz 1 0 0 0 p /56 143 khz 179 khz 357 khz 446 khz 589 khz 1 p /80 100 khz 125 khz 250 khz 313 khz 413 khz 1 0 p /96 83.3 khz 104 khz 208 khz 260 khz 344 khz 1 p /128 62.5 khz 78.1 khz 156 khz 195 khz 258 khz 1 0 0 p /336 23.8 khz 29.8 khz 59.5 khz 74.4 khz 98.2 khz 1 p /200 40.0 khz 50.0 khz 100 khz 125 khz 165 khz 1 0 p /224 35.7 khz 44.6 khz 89.3 khz 112 khz 147 khz 1 p /256 31.3 khz 39.1 khz 78.1 khz 97.7 khz 129 khz 17.3.2 i 2 c bus control register b (iccrb) iccrb issues start/stop condition, manipulates the sda pin, monitors the scl pin, and controls reset in the i 2 c control module. bit bit name initial value r/w 7 bbsy 0 r/w 6 scp 1 r/w 5 sdao 1 r 4 ? 1 r/w 3 sclo 1 r 2 ? 1 ? 1 iicrst 0 r/w 0 ? 1 ? section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 746 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit indicates whether the i 2 c bus is occupied or released and to issue start and stop conditions in master mode. this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of sda = high, assuming that the stop condition has been issued. follow this procedure also when re-transmitting a start condition. to issue a start or stop condition, use the mov instruction. 6 scp 1 r/w start/stop condition issue this bit controls the issuance of start or stop condition in master mode. to issue a start condition, write 1 to bbsy and 0 to scp. a re-transmit start condition is issued in the same way. to issue a stop condition, write 0 to bbsy and 0 to scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r this bit monitors the output level of sda. 0: when reading, the sda pin outputs a low level 1: when reading the sda pin outputs a high level 4 ? 1 r/w reserved the write value should always be 1. 3 sclo 1 r this bit monitors the scl output level. when reading and sclo is 1, the scl pin outputs a high level. when reading and sclo is 0, the scl pin outputs a low level. 2 ? 1 ? reserved this bit is always read as 0. 1 iicrst 0 r/w iic control module reset this bit reset the iic control module except the i 2 c registers. if hang-up occurs because of communication failure during i 2 c operation, by setting this bit to 1, the 0 ? 1 ? reserved this bit is always read as 1. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 747 of 1102 rej09b0365-0100 17.3.3 i 2 c bus mode register (icmr) icmr selects msb first or lsb first, controls th e master mode wait and selects the number of transfer bits. bit bit name initial value r/w 7 ? 0 r/w 6 wait 0 r/w 5 ? 1 ? 4 ? 1 ? 3 bcwp 1 r/w 2 bc2 0 r/w 1 bc1 0 r/w 0 bc0 0 r/w bit bit name initial value r/w description 7 ? 0 r/w reserved the write value should always be 0. 6 wait 0 r/w wait insertion this bit selects whether to insert a wait after data transfer except for the acknowledge bit. when this bit is set to 1, after the falling of the clock for the last data bit, the low period is extended for two transfer clocks. when this bit is cleared to 0, data and the acknowledge bit are transferred consecutiv ely with no waits inserted. the setting of this bit is invalid in slave mode. 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 bcwp 1 r/w bc write protect this bit controls the modification of the bc2 to bc0 bits. when modifying, this bit should be cleared to 0 and the mov instruction should be used. 0: when writing, the values of bc2 to bc0 are set 1: when reading, 1 is always read when writing, the settings of bc2 to bc0 are invalid. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 748 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. the settings of these bits should be made during intervals between transfer frames. when setting these bits to a value other than 000, the setting should be made while the scl line is low. the value return to 000 at the end of a data transfe r including the acknowledge bit. 000: 9 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 i 2 c control module can be reset without setting the ports and initializing the registers. 17.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to be transferred, and confirms the acknowledge bit to be received. bit bit name initial value r/w 7 tie 0 r/w 6 teie 0 r/w 5 rie 0 r/w 4 nakie 0 r/w 3 stie 0 r/w 2 acke 0 r/w 1 ackbr 0 r 0 ackbt 0 r/w section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 749 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit data empty interrupt (txi) request. 0: transmit data empty interrupt (txi) request is disabled 1: transmit data empty interrupt (txi) request is enabled 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) request at the rising of the ninth clock while the tdre bit in icsr is set to 1. the tei request can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt (tei) request is disabled 1: transmit end interrupt (tei) request is enabled 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive full interrupt (rxi) request when receive data is transferred from icdrs to icdrr and the rdrf bit in icsr is set to 1. the rxi request can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt (rxi) request is disabled 1: receive data full interrupt (rxi) request is enabled 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt (naki) request when the nackf and al bits in icsr are set to 1. the naki request can be canceled by clearing the nackf or al bit, or the nakie bit to 0. 0: nack receive interrupt (naki) request is disabled 1: nack receive interrupt (naki) request is enabled section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 750 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt (stpi) request is disabled 1: stop condition detection interrupt (stpi) request is enabled 2 acke 0 r/w acknowledge bit decision select 0: the value of the acknowledge bit is ignored and continuous transfer is performed 1: if the acknowledge bit is 1, continuous transfer is suspended 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit spec ifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing 1: 1 is sent at the acknowledge timing section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 751 of 1102 rej09b0365-0100 17.3.5 i 2 c bus status register (icsr) icsr confirms the interrupt request flags and status. bit bit name initial value r/w 7 tdre 0 r/w 6 tend 0 r/w 5 rdrf 0 r/w 4 nackf 0 r/w 3 stop 0 r/w 2 al 0 r/w 1 aas 0 r/w 0 adz 0 r/w bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting condition] ? when data is transferred from icdrt to icdrs and icdrt becomes empty [clearing conditions] ? when 0 is written to this bit after reading tdre = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when data is written to icdrt 6 tend 0 r/w transmit end [setting condition] ? when the ninth clock of scl rises while the tdre flag is 1 [clearing conditions] ? when 0 is written to this bit after reading tend = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when data is written to icdrt section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 752 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 rdrf 0 r/w receive data register full [setting condition] ? when receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written to this bit after reading rdrf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? when data is read from icdrr 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is set to 1 [clearing condition] ? when 0 is written to this bit after reading nackf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 3 stop 0 r/w stop condition detection flag [setting condition] ? when a stop condition is detected after frame transfer [clearing condition] ? when 0 is written to this bit after reading stop = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 753 of 1102 rej09b0365-0100 bit bit name initial value r/w description 2 al 0 r/w arbitration lost flag this flag indicates that arbitration was lost in master mode. when two or more master devices attempt to seize the bus at nearly the same time, the i 2 c bus monitors sda, and if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? when the internal sda and the sda pin level disagree at the rising of scl in master transmit mode ? when the sda pin outputs a high level in master mode while a start condition is detected [clearing condition] ? when 0 is written to this bit after reading al = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 1 aas 0 r/w slave addr ess recognition flag in slave receive mode, this flag is set to 1 when the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written to this bit after reading aas = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 754 of 1102 rej09b0365-0100 bit bit name initial value r/w description 0 adz 0 r/w general call address recognition flag this bit is valid in slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written to this bit after reading adz = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 17.3.6 slave address register (sar) sar is sets the slave address. in slave mode, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the lsi operates as the slave device. bit bit name initial value r/w 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w 0 ? 0 r/w bit bit name initial value r/w description 7 to 1 sva6 to sva0 0 r/w slave address 6 to 0 these bits set a unique address differing from the addresses of other slave devices connected to the i 2 c bus. 0 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 755 of 1102 rej09b0365-0100 17.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects a space in the i 2 c bus shift register, it transf ers the transmit data which has been written to icdrt to icdrs and starts transmitting data. if the next data is written to icdrt during transmitting data to icdrs, continuous transmission is possible. bit bit name initial value r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 17.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit read-only regist er that stores the receive data. when one byte of data has been received, icdrr transfers the r eceive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only re gister; therefore, this register cannot be written to by the cpu. bit bit name initial value r/w 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r 17.3.9 i 2 c bus shift register (icdrs) icdrs is an 8-bit write-only register that is used to transmit/receive data. in transmission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr af ter one by of data is received. this register cannot be read from the cpu. bit bit name initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 756 of 1102 rej09b0365-0100 17.4 operation 17.4.1 i 2 c bus format figure 17.3 shows the i 2 c bus formats. figure 17.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (b) i 2 c bus format (start condition retransmission) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 17.3 i 2 c bus formats sda scl s sla r/ w a 9 8 1-7 9 8 1-7 9 8 1-7 data a data a p figure 17.4 i 2 c bus timing [legend] s: start condition. the master device drives sda from high to low while scl is high. sla: slave address r/ w : indicates the direction of data transfer; from the slave devi ce to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda low. data: transferred data p: stop condition. the master device drives sda from low to high while scl is high. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 757 of 1102 rej09b0365-0100 17.4.2 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device return an acknowledge si gnal. figures 17.5 and 17.6 show the operating timings in master transmit mode. the transmission procedure and operations in master transmit mode are described below. 1. set the icr bit in the corresponding register to 1. set the ice bit in iccra to 1. set the wait bit in icmr and the cks3 to cks0 bits in iccra to 1. (initial setting) 2. read the bssy flag in iccrb to confirm that the bus is free. set the mst and trs bits in iccra to select master transmit mode. then, write 1 to bbsy and 0 to scp using the mov instruction. (the start condition is issu ed.) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte shows the slave address and r/w) to icdrt. after this , when tdre is automatically cleared to 0, data is transferred from icdrt to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rising of the ninth tran smit clock pulse. read the ackbr bit in icier to confirm that the slave device has been selected. then, write the second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue a stop condition. to issue the stop condition, write 0 to bbsy and scp using the mov instruction. scl is fixed to a low level until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wa it for nack (nackf in icsr is 1) from the receive device while cke in icier is 1. then , issue the stop conditio n to clear tend or nackf. 7. when the stop bit in icsr is set to 1, th e operation returns to th e slave receive mode. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 758 of 1102 rej09b0365-0100 sda (master output) sda (slave output) tdre tend icdrt icdrs 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 212 3456789 a r/w scl (master output) slave address address + r/w data 1 data 2 address + r/w data 1 [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) [5] write data to icdrt (third byte) user processing figure 17.5 master transmit mode operation timing 1 sda (master output) sda (slave output) tdre tend icdrt icdrs 1 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2345678 9 a a/a scl (master output) data n data n [7] set slave receive mode [5] write data to icdrt [6] issue stop condition. clear tend. user processing figure 17.6 master transmit mode operation timing 2 section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 759 of 1102 rej09b0365-0100 17.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. figures 17.7 and 17.8 show the operation timings in master receive mode. the receptio n procedure and operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccra to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icddr is read (dummy r ead), reception is started, the receive clock pulse is output, and data is received, in synchronization with the in ternal clock. the master mode outputs the level specified by the ackbt in icier to sd a, at the ninth receive clock pulse. 3. after the reception of the first frame data is completed, the rdrf bit in icsr is set to 1 at the rising of the ninth receive cloc k pulse. at this time, the received data is read by reading icdrr. at the same time, rdrf is cleared. 4. the continuous reception is performed by reading icdrr and clearing rdrf to 0 every time rdrf is set. if the eighth receive clock pulse falls after reading icdrr by other processing while rdrf is 1, scl is fixed to a low level until icdrr is read. 5. if the next frame is the last receive data, set the rcvd bit in iccr1 before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition is issued. 7. when the stop bit in icsr is set to 1, read icdrr and clear rcvd to 0. 8. the operation returns to the slave receive mode. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 760 of 1102 rej09b0365-0100 sda (master output) sda (slave output) tdre tend icdrs icdrr 1 bit 7 a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 21 3456789 9 a scl (master output) master transmit mode master receive mode data 1 trs rdrf data 1 user processing [3] read icdrr [1] clear tend and trs, then tdre [2] read icdrr (dummy read) figure 17.7 master receive mode operation timing 1 section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 761 of 1102 rej09b0365-0100 sda (master output) sda (slave output) rdrf rcvd icdrs icdrr 1 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2345678 9 a a/ a scl (master output) data n-1 data n data n-1 data n user processing [8] set slave receive mode [5] set rcvd then read icdrr [6] issue stop condition [7] read icdrr and clear rcvd figure 17.8 master receive mode operation timing 2 17.4.4 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, and the master device outputs the receive clock pulse and returns an acknowle dge signal. figures 17.9 and 17.10 show the operation timings in slave transmit mode. the tr ansmission procedure and operations in slave transmit mode are described below. 1. set the icr bit in the corresponding register to 1, then set the ice bit in iccra to 1. set the ackbit in icier, and perform other initial settings. set the mst and trs bits in iccra to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following the detection of the start condition, the slave device outputs the level specified by ackbt in icier to sda, at the rising of the ninth clock pulse. at this time, if the eighth bit data (r/ w ) is 1, trs in iccra and tdre in icsr are set to 1, and the mode changes to slave transm it mode automatically. the continuous transmission is performed by writing the transmit data to icdrt every time tdre is set. 3. if tdre is set after writing the last transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when tend is set, clear tend. 4. clear trs for end processing, and read icdrr (dummy read) to free scl. 5. clear tdre. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 762 of 1102 rej09b0365-0100 sda (master output) sda (slave output) tdre tend icdrs icdrr 1 bit 7 a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 21 3456789 9 a scl (master output) slave receive mode slave transmit mode data 1 data 2 data 3 data 2 data 1 scl (slave output) trs icdrt user processing [2] write data (data 3) to icdrt [2] write data (data 1) to icdrt [2] write data (data 2) to icdrt figure 17.9 slave transmit mode operation timing 1 section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 763 of 1102 rej09b0365-0100 sda (master output) sda (slave output) tdre tend icdrs icdrr 1 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2345678 9 scl (master output) trs icdrt scl (slave output) a a/ a data n slave transmit mode slave receive mode user processing [3] clear tend [5] clear tdre [4] clear trs and read icdrr (dummy read) figure 17.10 slave transmit mode operation timing 2 section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 764 of 1102 rej09b0365-0100 17.4.5 slave receive operation in slave receive mode, the master device outputs th e transmit clock and the transmit data, and the slave device returns an acknowledge signal. figures 17.11 and 17.12 show the operation timings in slave receive mode. the receptio n procedure and operations in sl ave receive mode are described below. 1. set the icr bit in the corresponding register to 1. then, set the ice bit in iccra to 1. set the ackbt bit in icier and perform other initial settings. set the mst and trs bits in iccra to select slave receive mode and wa it until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave address outputs the level specified by ackbt in icier to sda, at the rising of the ninth clock pulse. at the same time, rdrf in icsr is set to read icdrr (dummy read). (since the read data show s the slave address and r/ w , it is not used). 3. read icdrr every time rdrf is set. if the eighth clock pulse falls while rdrf is 1, scl is fixed to a low level until icdrr is read. the change of the acknowledge (ackbt) setting before reading icdrr to be returned to the ma ster device is reflected in the next transmit frame. 4. the last byte data is read by reading icdrr. sda (master output) scl (slave output) sda (slave output) icdrs icdrr 12 1 345678 9 9 a a scl (master output) data 2 data 1 rdrf data 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 user processing [2] read icdrr (dummy read) [2] read icdrr figure 17.11 slave receive mode operation timing 1 section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 765 of 1102 rej09b0365-0100 icdrs icdrr a a rdrf sda (master output) scl (slave output) sda (slave output) 12345678 9 scl (master output) data 2 data 1 data 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 9 user processing [3] set ackbt [3] read icdrr [4] read icdrr figure 17.12 slave receive mode operation timing 2 17.4.6 noise canceller the logic levels at the scl and sda pins are routed through the noise cancellers before being latched internally. figure 17.13 shows a block diagram of the noise canceller circuit. the noise canceller consists of two cascaded latche s and a match detector. th e signal input to scl (or sda) is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d c q d sampling clock sampling clock scl input or sda input latch system clock period latch compare match detection circuit internal scl or internal sda sampling clock figure 17.13 block diag ram of noise canceller section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 766 of 1102 rej09b0365-0100 17.4.7 example of use sample flowcharts in resp ective modes that use the i 2 c bus interface are shown in figures 17.14 to 17.17. no no yes yes no yes no no no no yes yes yes yes yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] start [1] detect the state of the scl and sda lines [2] set to master transmit mode [3] issue the start condition [4] set the transmit data for the first byte (slave address + r/w) [5] wait for 1 byte of data to be transmitted [6] detect the acknowledge bit, transferred from the specified slave device [7] set the transmit data for the second and subsequent data (except for the last byte) [8] wait for icdrt empty [9] set the last byte of transmit data [10] wait for the completion of transmission of the last byte [11] clear the tend flag [12] clear the stop flag [13] issue the stop condition [14] wait for the creation of the stop condition [15] set to slave receive mode. clear tdre. initial settings read bbsy in iccrb set mst = 1 and trs = 1 in iccra bbsy = 0? write bbsy = 1 and scp = 0 write the transmit data in icdrt read tend in iscr tend = 1? read ackbr in icier ackbr = 0? transmit mode? read tdre in icsr tdre = 1? last byte? write the transmit data to icdrt read tend in icsr tend = 1? clear tend in icsr clear stop in icsr write bbsy = 0 and scp = 0 read stop in icsr stop = 1? set mst = 0 and trs = 0 in iccra clear trde in icsr end master receive mode write the transmit data to icdrt figure 17.14 sample flowchart of master transmit mode section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 767 of 1102 rej09b0365-0100 no yes rdrf = 1? no yes rdrf = 1? no yes stop = 1? no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] master receive mode [1] clear tend, set to master receive mode, then clear tdre * 1 * 2 [2] set acknowledge to the transmitting device * 1 * 2 [3] dummy read icdrr * 1 * 2 [4] wait for 1 byte of data to be received * 2 [5] check if (last receive -1) * 2 [6] read the receive data * 2 [7] set acknowledge of the last byte. disable continuous reception (rcvd = 1). * 2 [8] read receive data of (last byte -1). * 2 [9] wait for the last byte to be received [10] clear the stop flag [11] issue the stop condition [12] wait for the creation of stop condition [13] read the receive data of the last byte [14] clear rcvd to 0 [15] set to slave receive mode clear tend in icsr set trs = 0 (iccra) clear tdre in icsr set ackbt = 0 (icier) dummy read icdrr dummy read icsr last receive -1? read icdrr set ackbt = 1 (icier) set rcvd = 1 (iccra) read icdrr read rdrf in icsr clear stop in icsr write bbsy = 0 and scp = 0 read stop in icsr read icdrr set rcvd = 0 (iccra) set mst = 0 (iccra) end note: 1. do not generate an interrupt during steps [1] to [3]. 2. for one-byte reception, steps [2] to [6] do not need to be executed. after step [1], execute step [7]. in step [8], read icdrr (dummy read). figure 17.15 sample flowch art for master receive mode section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 768 of 1102 rej09b0365-0100 tdre = 1? yes yes no no no [1] [4] [5] [6] [7] [8] [9] [2] [3] yes tend = 1? [1] clear the aas flag. [2] set the transmit data for icdrt (except the last byte). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte of data to be transmitted. [6] clear the tend flag. [7] set to slave receive mode. [8] dummy read icdrr to free the scl line. [9] clear the tdre flag. slave transmit mode clear aas in icsr write the transmit data to icdrt read trd in icsr last byte? write the transmit data to icdrt read tend in icsr clear tend in icsr set trs = 0 (iccra) dummy read icdrr clear tdre in icsr end figure 17.16 sample flowchart for slave transmit mode section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 769 of 1102 rej09b0365-0100 no yes rdrf = 1? no yes rdrf = 1? no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. * [2] set the acknowledge for the transmit device. * [3] dummy read icdrr * [4] wait for 1 byte of data to be received * [5] detect (last reception -1) * [6] read the receive data. * [7] set the acknowledge for the last byte. * [8] read the receive data of (last byte -1). * [9] wait for the reception of the last byte to be completed. [10] read the last byte of receive data. slave receive mode clear aas in icsr set ackbt = 0 in icier dummy read icdrr read rdrf in icsr the last reception -1? read icdrr set ackbt = 1 in icier read icdrr read rdrf in icsr read icdrr end note: * for one-byte reception, steps [2] to [6] do not need to be executed. after step [1], execute step [7]. in step [8], read icdrr (dummy read). figure 17.17 sample flowch art for slave receive mode section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 770 of 1102 rej09b0365-0100 17.5 interrupt request there are six interrupt requ ests in this module; transmit data empt y, transmit end, receive data full, nack detection, stop recognition, and arbitratio n lost. table 17.3 shows the contents of each interrupt request. table 17.3 interrupt requests interrupt request abbreviat ion interrupt condition transmit data empty txi (tdre = 1) ? (tie = 1) transmit end tei (tend = 1) ? (teie = 1) receive data full rxi (rdrf = 1) ? (rie = 1) stop recognition stpi (stop = 1) ? (stie = 1) nack detection maki {(nackf = 1) + (al = 1)} ? (nakie = 1) arbitration lost 17.6 bit synchronous circuit this module has a possibility that the high-level period is shortened in the two states described below. in master mode, ? when scl is driven low by the slave device ? when the rising speed of scl is lowered by the load on the scl lin e (load capacitance or pull-up resistance) therefore, this module monitors scl and communicates bit by bit in synchronization. figure 17.18 shows the timing of the bit synchronous circuit, and table 17.4 shows the time for monitoring scl, i.e., a period from scl's departure from low-level output and its entry to a high impedance state until monitoring scl. section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 771 of 1102 rej09b0365-0100 scl monitor timing reference clock internal scl scl v ih figure 17.18 timing of the bit synchronous circuit table 17.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 0 7.5 tcyc 1 19.5 tcyc 1 0 17.5 tcyc 1 41.5 tcyc 17.7 usage notes 1. confirm the ninth falling edge of the clock cy cle before issuing a stop or a repeated start condition. the ninth falling edge can be confirmed by monitoring the sclo bit in the i 2 c bus control register b (iccrb). if a stop or a repeated start condition is issued at certain timing in either of the following cases, the stop or repeated start cond ition may be issued incorrectly. ? the rising time of the scl signal exceeds the time given in section 17.6, bit synchronous circuit, because of the load on the scl bu s (load capacitance or pull-up resistance). ? the bit synchronous circuit is activated because a slave device holds the scl bus low during the eighth clock. 2. the wait bit in the i 2 c bus mode register (icmr) must be held at 0. if the wait bit is set to 1, when a slave de vice holds the scl signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. 3. restriction in transfer rate setting value in multi-master mode section 17 i 2 c bus interface 2 (iic2) rev. 1.00 sep. 13, 2007 page 772 of 1102 rej09b0365-0100 when the transfer rate of i2c tr ansfer of this lsi is slower th an that of other master, the scl signal the width of which is unexpected may be output. to avoid this phenomenon, set a transfer rate of 1/1.8 or more of the fastest rate of other master to the transfer rate of i2c transfer rate. for example, if the fastest rate of other master s is 400 kbps, the i2c transfer rate of this lsi should be 223 kbps (= 400/1.8) or more. 4. restriction in bit manipulation when the mst and trs bits are set in multi-master mode when the mst and trs bits are set to mast er slave mode by manipulating these bits sequentially, the conflict state occurs as follows according to the timing that arbitration is lost; the al bit in icsr is set to 1, and set to master mode (mst = 1, trs = 1). there are the following methods to avoid this phenomenon. ? in multi-master mode, set the mst and trs bits by mov instruction. ? when arbitration is lost, confirm that the mst and trs bits are set to 0. if these bits are set to other than 0, set these bits to 0. 5. notes on master receive mode in master receive mode, when the rdrf bit is set to 1 at the eighth rising clock, the scl signal is pulled to "low" state. when icdrr is re ad near at the eighth falling clock, the scl signal level is released and the ninth clock is out put by fixing the eighth clock of receive data to "low" state. reading icdrr is not required. as a result, the failure to receive data occurs. there are the following methods to avoid this phenomenon. ? in master receive mode, read ic drr by the eighth rising clock. ? in master receive mode, set the rcvd bit to 1 and process the bit by the communication of every one byte. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 773 of 1102 rej09b0365-0100 section 18 a/d converter this lsi includes three units (units 0, 1, and 2) of successive approxima tion type 10-bit a/d converter. the a/d converter unit 0 allows up to ei ght analog input channels to be selected while the a/d converter units 1 and 2 allow up to four analog input channels to be selected. although this section explains the operation of the a/d converter unit 0, the a/d converter units 1 and 2 also have the same functional and operational features as are described in this section (unless otherwise noted). figures 18.1, 18.2, and 18.3 show block diagrams of the a/d converter units 0, 1, and 2, respectively. 18.1 features ? 10-bit resolution ? eight or four input channels (total eight input channels for the two units) four channels x three units (for units 0, 1, and 2) eight channels x one unit (for unit 0) + four channels x one unit (unit 2) ? conversion time: unit 0: (2.7 ms per channel) units 1 and 2: (2.7 ms per channel) ? two kinds of operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels, or 1 to 8 channels* 1 ? eight data registers for the a/d converter unit 0 and four data registers for units 1 and 2 (total twelve data registers for the three units) results of a/d conversion are held in a 16-bit data register for each channel. ? sample and hold functionality ? three types of conversion start conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (tpu)* 1 or 8-bit timer (tmr)* 2 , or an external trigger signal. ? function of starting units simultaneously a/d conversion for multiple units can be started by external trigger (adtrg0). ? interrupt source a/d conversion end interrupt (adi) request can be generated. ? module stop state specifiable notes: 1. only supported in the a/d converter unit 0. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 774 of 1102 rej09b0365-0100 2. for unit 0, a/d conversion can be started by a conversion start trigger by the tmr units 0 and 1 whereas for units 1 and 2 a/d conversion can be started by a conversion start trigger by the tmr units 2 and 3. module data bus control circuit internal data bus 10-bit a/d comparator + ? sample-and- hold circuit adi0 interrupt signal bus interface av cc vref av ss an0 an1 an2 an3 an4 an5 an6 an7 adtrg0 -a conversion start trigger from the tpu or tmr (units 0, 1) successive approximation register multiplexer [legend] adcr_0: a/d control register_0 adcsr_0: a/d control/status register_0 addra_0: a/d data register a_0 addrb_0: a/d data register b_0 addrc_0: a/d data register c_0 addrd_0: a/d data register d_0 addre_0: a/d data register e_0 addrf_0: a/d data register f_0 addrg_0: a/d data register g_0 addrh_0: a/d data register h_0 addra_0 addrb_0 addrc_0 addrd_0 addre_0 addrf_0 addrg_0 addrh_0 adcsr_0 adcr_0 synchronization circuit selector adtrg0 -b figure 18.1 block diagram of a/d converter unit 0 (ad_0) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 775 of 1102 rej09b0365-0100 module data bus control circuit internal data bus 10-bit a/d comparator + ? sample-and- hold circuit adi1 interrupt signal bus interface av cc vref av ss adtrg0 -a conversion start trigger from the tmr (units 2, 3) successive approximation register multiplexer [legend] adcr_1: a/d control register_1 adcsr_1: a/d control/status register_1 addra_1: a/d data register a_1 addrb_1: a/d data register b_1 addrc_1: a/d data register c_1 addrd_0: a/d data register d_1 addre_0: a/d data register e_1 addrf_0: a/d data register f_1 addrg_0: a/d data register g_1 addrh_0: a/d data register h_1 addra_1 addrb_1 addrc_1 addrd_1 addre_1 addrf_1 addrg_1 addrh_1 adcsr_1 adcr_1 synchronization circuit selector adtrg0 -b adtrg1 -a adtrg1 -b an4 an5 an6 an7 figure 18.2 block diagram of a/d converter unit 1 (ad_1) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 776 of 1102 rej09b0365-0100 module data bus control circuit internal data bus 10-bit a/d comparator + ? sample-and- hold circuit adi0 interrupt signal bus interface av cc vref av ss adtrg0 -a conversion start trigger from the tmr (units 2, 3) successive approximation register multiplexer [legend] adcr_2: a/d control register_2 adcsr_2: a/d control/status register_2 addra_2: a/d data register a_2 addrb_2: a/d data register b_2 addrc_2: a/d data register c_2 addrd_2: a/d data register d_2 addre_2: a/d data register e_2 addrf_2: a/d data register f_2 addrg_2: a/d data register g_2 addrh_2: a/d data register h_2 addra_2 addrb_2 addrc_2 addrd_2 addre_2 addrf_2 addrg_2 addrh_2 adcsr_2 adcr_2 synchronization circuit selector adtrg0 -b adtrg2 an8 an9 an10 an11 figure 18.3 block diagram of a/d converter unit 2 (ad_2) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 777 of 1102 rej09b0365-0100 18.2 input/output pins table 18.1 shows the pin configuration of the a/d converter. table 18.1 pin configuration unit abbr. pin name symbol i/o function analog input pin 0 an0 input analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input a/d external trigger input pin 0_a adtrg0 -a input external trigger input pin 0_a for starting a/d conversion * 1 * 2 0 ad_0 a/d external trigger input pin 0_b adtrg0 -b input external trigger input pin 0_a for starting a/d conversion * 1 * 2 analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input analog inputs a/d external trigger input pin 1_a adtrg1 _a input external trigger input 1_a for starting a/d conversion * a/d external trigger input pin 1_b adtrg1 _b input external trigger input 1_b for starting a/d conversion * a/d external trigger input pin 0_a adtrg0 -a input external trigger input pin 0_a for starting a/d conversion * 1 * 2 1 ad_1 a/d external trigger input pin 0_b adtrg0 -b input external trigger input pin 0_a for starting a/d conversion * 1 * 2 section 18 a/d converter rev. 1.00 sep. 13, 2007 page 778 of 1102 rej09b0365-0100 unit abbr. pin name symbol i/o function analog input pin 8 an8 input analog input pin 9 an9 input analog input pin 10 an10 input analog input pin 11 an11 input analog inputs 2 ad_2 a/d external trigger input pin 2 adtrg2 input external trigger input for starting a/d conversion * a/d external trigger input pin 0_a adtrg0 -a input external trigger input pin 0_a for starting a/d conversion * 1 * 2 a/d external trigger input pin 0_b adtrg0 -b input external trigger input pin 0_a for starting a/d conversion * 1 * 2 analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground common reference voltage pin vref input a/d conversion reference voltage note: 1. selectable by setting of the trgs1, trgs0, and extrgs bits in adcr. 2. the adtrg0 input pin can be selected by the adtrg0s bit in pfcr6. for details, see section 11, i/o ports. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 779 of 1102 rej09b0365-0100 18.3 register descriptions the a/d converter has the following registers. unit 0 (a/d_0) registers: ? a/d data register a_0 (addra_0) ? a/d data register b_0 (addrb_0) ? a/d data register c_0 (addrc_0) ? a/d data register d_0 (addrd_0) ? a/d data register e_0 (addre_0) ? a/d data register f_0 (addrf_0) ? a/d data register g_0 (addrg_0) ? a/d data register h_0 (addrh_0) ? a/d control/status register_0 (adcsr_0) ? a/d control register_0 (adcr_0) unit 1 (a/d_1) registers: ? a/d data register a_1 (addra_1) ? a/d data register b_1 (addrb_1) ? a/d data register c_1 (addrc_1) ? a/d data register d_1 (addrd_1) ? a/d data register e_1 (addre_1) ? a/d data register f_1 (addrf_1) ? a/d data register g_1 (addrg_1) ? a/d data register h_1 (addrh_1) ? a/d control/status register_1 (adcsr_1) ? a/d control register_1 (adcr_1) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 780 of 1102 rej09b0365-0100 unit 2 (a/d_2) registers: ? a/d data register a_2 (addra_2) ? a/d data register b_2 (addrb_2) ? a/d data register c_2 (addrc_2) ? a/d data register d_2 (addrd_2) ? a/d data register e_2 (addre_2) ? a/d data register f_2 (addrf_2) ? a/d data register g_2 (addrg_2) ? a/d data register h_2 (addrh_2) ? a/d control/status register_2 (adcsr_2) ? a/d control register_2 (adcr_2) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 781 of 1102 rej09b0365-0100 18.3.1 a/d data registers a to h (addra to addrh) there are eight 16-bit read-only addr registers, addra to addrh, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 18.2. the converted 10-bit data is stored in bits 15 to 6. the lower 6-bit data is always read as 0. the data bus between the cpu an d the a/d converter has a 16-bit width. the data can be read directly from the cpu. addr must not be accessed in 8-bit units and must be accessed in 16-bit units. 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r bit bit name initial value r/w table 18.2 analog input channels and corresponding addr registers a/d data register storing conversion result analog input channel unit 1* 1 unit 1* 2 unit 1* 3 an0 addra_0 (unit 0) ? ? an1 addrb_0 (unit 0) ? ? an2 addrc_0 (unit 0) ? ? an3 addrd_0 (unit 0) ? ? an4 addre_0 (unit 0)* 1 addre_1 (unit 1)* 2 ? an5 addrf_0 (unit 0)* 1 addrf_1 (unit 1)* 2 ? an6 addrg_0 (unit 0)* 1 addrg_1 (unit 1)* 2 ? an7 addrh_0 (unit 0)* 1 addrh_1 (unit 1)* 2 ? an8 ? ? addra_2 (unit 2)* 3 an9 ? ? addrb_2 (unit 2)* 3 an10 ? ? addrc_2 (unit 2)* 3 an11 ? ? addrd_2 (unit 2)* 3 notes: *1 a/d conversion should be not performed on the same channel by multiple units. *2 the addra_1 to addrd_1 registers for unit 1 are not used. *3 the addre_2 to addrh_2 registers for unit 2 are not used. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 782 of 1102 rej09b0365-0100 18.3.2 a/d control/status register for unit 0 (adcsr_0) adcsr_0 controls a/d conversion operations. 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 - 0 r/w 3 ch3 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? completion of a/d conversion in single mode ? completion of a/d conversion on all specified channels in scan mode [clearing conditions] ? writing of 0 after reading adf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? reading from addr after activation of the dmac or dtc by an adi interrupt 6 adie 0 r/w a/d interrupt enable setting this bit to 1 enables adi interrupts by adf. 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters wait state. setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when a/d conversion on the specified channel ends. in scan mode, a/d conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. 4 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 783 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 selects analog input together with bits scane and scans in adcr. ? when scane = 0 and scans = x 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1xxx: setting prohibited ? when scane = 1 and scans = 0 0000: an0 0001: an0 and an1 0010: an0 to an2 0011: an0 to an3 0100: an4 0101: an4 and an5 0110: an4 to an6 0111: an4 to an7 1xxx: setting prohibited ? when scane = 1 and scans = 1 0000: an0 0001: an0 and an1 0010: an0 to an2 0011: an0 to an3 0100: an0 to an4 0101: an0 to an5 0110: an0 to an6 0111: an0 to an7 1xxx: setting prohibited [legend] x: don't care note: * only 0 can be written to this bit, to clear the flag. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 784 of 1102 rej09b0365-0100 18.3.3 a/d control/status register for unit 1 (adcsr_1) adcsr_1 controls a/d conversion operations. 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 excks 0 r/w 3 ch3 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? completion of a/d conversion in single mode ? completion of a/d conversion on all specified channels in scan mode [clearing conditions] ? writing of 0 after reading adf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? reading from addr after activation of the dmac or dtc by an adi interrupt 6 adie 0 r/w a/d interrupt enable setting this bit to 1 enables adi interrupts by adf. 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters wait state. setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when a/d conversion on the specified channel ends. in scan mode, a/d conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. 4 excks 0 r/w clock extension select specifies the a/d conversion ti me in combination with the cks1 and cks0 bits in adcr. be sure to set these three bits at one time. for details, see the description of the adcr resisters. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 785 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 selects analog input together with bits scane and scans in adcr. ? when scane = 0 and scans = x 00xx: setting prohibited 0100: an4 0101: an5 0110: an6 0111: an7 1xxx: setting prohibited ? when scane = 1 and scans = 0 00xx: setting prohibited 0100: an4 0101: an4 and an5 0110: an4 to an6 0111: an4 to an7 1xxx: setting prohibited ? when scane = 1 and scans = 1 xxxx: setting prohibited [legend] x: don't care note: * only 0 can be written to this bit, to clear the flag. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 786 of 1102 rej09b0365-0100 18.3.4 a/d control/status register for unit 2 (adcsr_2) adcsr_2 controls a/d conversion operations. 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 excks 0 r/w 3 ch3 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 0 r/w bit bit name initial value r/w note: * only 0 can be written to this bit, to clear the flag. bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? completion of a/d conversion in single mode ? completion of a/d conversion on all specified channels in scan mode [clearing conditions] ? writing of 0 after reading adf = 1 (when the cpu is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) ? reading from addr after activation of the dmac or dtc by an adi interrupt 6 adie 0 r/w a/d interrupt enable setting this bit to 1 enables adi interrupts by adf. 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters wait state. setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when a/d conversion on the specified channel ends. in scan mode, a/d conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. 4 excks 0 r/w clock extension select specifies the a/d conversion ti me in combination with the cks1 and cks0 bits in adcr. be sure to set these three bits at one time. for details, see the description of the adcr resisters. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 787 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 selects analog input together with bits scane and scans in adcr. ? when scane = 0 and scans = x 0xxx: setting prohibited 1000: an8 1001: an9 1010: an10 1011: an11 1xxx: setting prohibited ? when scane = 1 and scans = 0 0xxx: setting prohibited 1000: an8 1001: an8 and an9 1010: an8 to an10 1011: an8 to an11 1xxx: setting prohibited ? when scane = 1 and scans = 1 xxxx: setting prohibited [legend] x: don't care note: * only 0 can be written to this bit, to clear the flag. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 788 of 1102 rej09b0365-0100 18.3.5 a/d control register (adcr_0) unit 0 adcr enables a/d conversion to be started by an external trigger input. 7 trgs1 0 r/w 6 trgs0 0 r/w 5 scane 0 r/w 4 scans 0 r/w 3 cks1 0 r/w 2 cks0 0 r/w 1 - 0 r/w 0 extrgs 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 0 trgs1 trgs0 extrgs 0 0 0 r/w r/w r/w timer trigger select 1 and 0 these bits select enabling or di sabling of the start of a/d conversion by a trigger signal. 000: disables a/d conversion start by external trigger 010: enables a/d conversion start by external trigger from tpu (unit 0) 100: enables a/d conversion start by external trigger from tmr (units 0 and 1) 110: enables a/d conversion start by the adtrg0 pin * 1 * 2 001: setting prohibited 011: setting prohibited 101: setting prohibited 111: enables a/d conversion start by the adtrg0 pin * 1 * 2 (starts units simultaneously) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 789 of 1102 rej09b0365-0100 bit bit name initial value r/w description 5 4 scane scans 0 0 r/w r/w scan mode these bits select the a/ d conversion operating mode. 0x: single mode 10: scan mode. a/d conversion is performed continuously for channels 1 to 4. 11: scan mode. a/d conversion is performed continuously for channels 1 to 8. 3 2 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits set the a/d conversion time. first select the a/d conversion time by setting bits cks1 and cks0 while adst = 0 and then set the mode of a/d conversion. cks1, and cks0 00: a/d conversion time = 530 states* 2 (max.) 01: a/d conversion time = 266 states* 2 (max.) 10: a/d conversion time = 134 states* 2 (max.) 11: a/d conversion time = 68 states* 2 (max.) 1 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. [legend] x: don't care notes: 1. to set a/d conversion to start by the adtrg pin, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, re spectively. for details, see section 11, i/o ports. 2. select the adtrg0 input pin by the adtrg0s bit in pfcr6. for details, see section 11, i/o ports. 3. p criterion section 18 a/d converter rev. 1.00 sep. 13, 2007 page 790 of 1102 rej09b0365-0100 18.3.6 a/d control register (adcr_1) unit 1 adcr enables a/d conversion to be started by an external trigger input. 7 trgs1 0 r/w 6 trgs0 0 r/w 5 scane 0 r/w 4 scans 0 r/w 3 cks1 0 r/w 2 cks0 0 r/w 1 adstclr 0 r/w 0 extrgs 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 0 trgs1 trgs0 extrgs 0 0 0 r/w r/w r/w timer trigger select 1 and 0 these bits select enabling or di sabling of the start of a/d conversion by a trigger signal. 000: disables a/d conversion start by external trigger 010: setting prohibited 100: setting prohibited 110: enables a/d conversion start by the adtrg1 -a pin * 1 * 2 001: enables a/d conversion start by the adtrg1 -b pin * 1 * 2 011: setting prohibited 101: enables a/d conversion start by external trigger from tmr (units 2 and 3) 111: enables a/d conversion start by the adtrg0 pin* 1 * 2 (starts units simultaneously) 5 4 scane scans 0 0 r/w r/w scan mode these bits select the a/ d conversion operating mode. 0x: single mode 10: scan mode. a/d conversion is performed continuously for channels 1 to 4. 11: setting prohibited section 18 a/d converter rev. 1.00 sep. 13, 2007 page 791 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock for a/d conversion in combination with the excks bit. first select the a/d conversion time by setting bits excks, cks1 and cks0 while adst = 0 and then set the mode of a/d conversion. excks, cks1, and cks0 000: a/d conversion time = 530 states* 3 (max.) 001: a/d conversion time = 266 states* 3 (max.) 010: a/d conversion time = 134 states* 3 (max.) 011: a/d conversion time = 68 states* 3 (max.) 100: a/d conversion time = 332 states (max.) 101: a/d conversion time = 168 states* 3 (max.) 110: a/d conversion time = 87 states* 3 (max.) 111: a/d conversion time = 46 states* 3 (max.) 1 adstclr 0 r/w a/d start clear this bit enables or disables automatic clearing of the adst bit in scan mode. 0: the adst bit is not automatically cleared to 0 in scan mode. 1: clears the adst bit to 0 upon completion of the a/d conversion for all of the selected channels in scan mode. [legend] x: don't care notes: 1. to set a/d conversion to start by the adtrg pin, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, re spectively. for details, see section 11, i/o ports. 2. select the adtrg0 input pin by the adtrg0s bit in pfcr6. for details, see section 11, i/o ports. 3. only possible in unit 0. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 792 of 1102 rej09b0365-0100 18.3.7 a/d control register (adcr_2) unit 2 adcr enables a/d conversion to be started by an external trigger input. 7 trgs1 0 r/w 6 trgs0 0 r/w 5 scane 0 r/w 4 scans 0 r/w 3 cks1 0 r/w 2 cks0 0 r/w 1 adstclr 0 r/w 0 extrgs 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 0 trgs1 trgs0 extrgs 0 0 0 r/w r/w r/w timer trigger select 1 and 0 these bits select enabling or disabli ng of the start of a/d conversion by a trigger signal. 000: disables a/d conversion start by external trigger 010: setting prohibited 100: setting prohibited 110: enables a/d conversion start by the adtrg2 pin * 1 * 2 001: setting prohibited 011: setting prohibited 101: enables a/d conversion start by external trigger from tmr (units 2 and 3) 111: enables a/d conversion start by the adtrg0 pin* 1 * 2 (starts units simultaneously) 5 4 scane scans 0 0 r/w r/w scan mode these bits select the a/d conversion operating mode. 0x: single mode 10: scan mode. a/d conversion is performed continuously for channels 1 to 4. 11: setting prohibited section 18 a/d converter rev. 1.00 sep. 13, 2007 page 793 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 2 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock for a/d conversion in combination with the excks bit. first select the a/d co nversion time by setting bits excks, cks1 and cks0 while adst = 0 and then set the mode of a/d conversion. excks, cks1, and cks0 000: a/d conversion time = 530 states* 3 (max.) 001: a/d conversion time = 266 states* 3 (max.) 010: a/d conversion time = 134 states* 3 (max.) 011: a/d conversion time = 68 states* 3 (max.) 100: a/d conversion time = 332 states (max.) 101: a/d conversion time = 168 states* 3 (max.) 110: a/d conversion time = 87 states* 3 (max.) 111: a/d conversion time = 46 states* 3 (max.) 1 adstclr 0 r/w a/d start clear this bit enables or disables automatic clearing of the adst bit in scan mode. 0: the adst bit is not automatically cleared to 0 in scan mode. 1: clears the adst bit to 0 upon completion of the a/d conversion for all of the selected channels in scan mode. [legend] x: don't care notes: 1. to set a/d conversion to start by the adtrg pin, the ddr bit and icr bit for the corresponding pin should be set to 0 and 1, re spectively. for details, see section 11, i/o ports. 2. select the adtrg0 input pin by the adtrg0s bit in pfcr6. for details, see section 11, i/o ports. 3. only possible in unit 0. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 794 of 1102 rej09b0365-0100 18.4 operation the a/d converter has two operating modes: single mode and scan mode. first select the clock for a/d conversion (adclk). when changing the operating mode or analog input channel, to prevent incorrect operation, first clear the adst bit in adcsr to 0. the adst bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 18.4.1 single mode in single mode, a/d conversion is to be performed only once on the analog input of the specified single channel. 1. a/d conversion for the selected channel is started when the adst bit in adcsr is set to 1 by software, tpu* 1 , tmr* 2 , or an external trigger input. 2. when a/d conversion is completed, the a/d conversion result is transferred to the corresponding a/d data register of the channel. 3. when a/d conversion is completed, the adf b it in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi in terrupt request is generated. 4. the adst bit remains at 1 during a/d conv ersion, and is automatically cleared to 0 when a/d conversion ends. the a/d converter enters wa it state. if the adst bit is cleared to 0 during a/d conversion, a/d conversion stops and the a/d converter enters a wait state. notes: 1. only possible in unit 0. 2. as conversion start trigger, units 0 and 1 of tmr, and units 2 and 3 of tmr are available in unit 0, and unit 1, respectively. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 795 of 1102 rej09b0365-0100 adie adst adf addra addrb addrc addrd channel 0 (an0) operation state channel 1 (an1) operation state channel 2 (an2) operation state channel 3 (an3) operation state set * set * set * a/d conversion start clear * clear * waiting for conversion waiting for conversion waiting for conversion waiting for conversion waiting for conversion reading a/d conversion result reading a/d conversion result a/d conversion 1 a/d conversion 2 a/d conversion result 1 a/d conversion result 2 waiting for conversion note: * indicates the timing of instruction execution by software. figure 18.4 example of a/d converter op eration (single mode, channel 1 selected) 18.4.2 scan mode in scan mode, a/d conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight* channels. two types of scan mode are provided, that is , continuous scan mode where a/d conversion is repeatedly performed and one-cycle scan mode where a/d conversion is performed for the sp ecified channels for one cycle. (1) continuous scan mode 1. when the adst bit in adcsr is set to 1 by software, tpu* 1 , tmr* 2 , or an external trigger input, a/d conversion starts on the first channel in the specified channel group. consecutive a/d conversion* 1 on a maximum of four channels (scane and scans = b'10) or on a maximum of eight channels (scane and scans = b'11) can be selected. when consecutive a/d conversion is performed on four channels, a/d conversion starts on an0 when ch3 and ch2 of unit 0 = b'00, on an4 when ch3 and ch2 of units 0 and 1 = b'01, on an8 when section 18 a/d converter rev. 1.00 sep. 13, 2007 page 796 of 1102 rej09b0365-0100 ch3 and ch2 of unit 2 = b?10. when consecutive a/d conversion* 1 is performed on eight channels, a/d conversion starts on an0 when ch3 = b'0. 2. when a/d conversion for each channel is comple ted, the a/d conversion result is sequentially transferred to the corresponding addr of each channel. 3. when a/d conversion of all selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. a/d conversion of the first channel in the group starts again. 4. the adst bit is not cleared automatically, and steps 2 to 3 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and the a/d converter enters wait state. if the adst bit is la ter set to 1, a/d conversion starts again from the first channel in the group. notes: 1. only possible in unit 0. 2. as conversion start trigger, units 0 and 1 of tmr, and units 2 and 3 of tmr are available in unit 0, and unit 1, respectively. adst adf addra addrb addrc addrd set * 1 clear * 1 clear * 1 * 2 waiting for conversion channel 0 (an0) operation state channel 1 (an1) operation state channel 2 (an2) operation state channel 3 (an3) operation state waiting for conversion a/d conver- sion 1 a/d conversion result 3 waiting for conversion waiting for conversion waiting for conversion a/d conversion result 2 a/d conversion result 4 a/d conver- sion 5 a/d conver- sion 4 a/d conversion time waiting for conversion a/d conver- sion 3 waiting for conversion waiting for conversion waiting for conversion a/d conver- sion 2 a/d conversion result 1 transfer a/d conversion consecutive execution notes: 1. 2. indicates the timing of instruction execution by software. data being converted is ignored. figure 18.5 example of a/d conversion (continuous scan mode, three chan nels (an0 to an2) selected) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 797 of 1102 rej09b0365-0100 (2) one-cycle scan mode (only enabled in units 1 and 2) 1. set the adstclr bit in adcr to 1. 2. when the adst bit in adcsr is set to 1 by software, tpu, tmr (units 2 and 3), or an external trigger input, a/d conversion starts on the first channel in the specified channel group. consecutive a/d conversion on a maximum of four channels (scane and scans = b'10) or on a maximum of eight channels (scane and scans = b'11) can be selected. for unit 1, a/d conversion starts on an4 when ch3 and ch2 = b'01. for unit 2, a/d conversion starts on an8 when ch3 and ch2 = b'10. 3. when a/d conversion for each channel is completed, the a/d conversion result is sequentially transferred to the corresponding addr of each channel. 4. when a/d conversion of all selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 5. the adst bit is automatical ly cleared when a/d conversion is completed for all of the channels that have been selected. a/d conver sion stops and the a/d converter enters a wait state. a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion time a/d conversion one-cycle execution adst adf addre addrf addrg addrh channel 4 (an4) operation state channel5 (an5) operation state channel 6 (an6) operation state channel 7 (an7) operation state set * clear * waiting for conversion waiting for conversion waiting for conversion waiting for conversion waiting for conversion waiting for conversion transfer waiting for conversion a/d conversion 1 a/d conversion 2 a/d conversion 3 note: * indicates the timing of instruction execution by software. figure 18.6 example of a/d conversion (one-cycle scan mode, three channels (an4 to an6) selected) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 798 of 1102 rej09b0365-0100 18.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) passes after the adst bit in adcsr is set to 1, then starts a/d conversion. figure 18.7 shows the a/d conversion timing. tables 18.3 and 18.4 show the a/d conversion time. as shown in figure 18.7, the a/d conversion time (t conv ) includes the a/d conversion start delay time (t d ) and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. the total conversion time ther efore varies within the ranges indicated in tables 18.3 and 18.4. in scan mode, the values given in tables 18.3 and 18.4 apply to the first conversion time. the values given in table 18.5 apply to the second and subsequent conversions. in either case, bits cks1 and cks0 in adcr should be set so that the conversion time is within the ranges indicated by the a/d conversion characteristics. (1) (2) t d t spl t conv p address write signal input sampling timing adf [legend] (1): adcsr write cycle (2): adcsr address t d: a/d conversion start delay time t spl : input sampling time t conv : a/d conversion time figure 18.7 a/d conversion timing section 18 a/d converter rev. 1.00 sep. 13, 2007 page 799 of 1102 rej09b0365-0100 table 18.3 a/d conversion ch aracteristics (excks1 = 0) cks1 = 0 cks1 = 1 cks = 0 cks = 1 cks = 0 cks = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay time t d 18 ? 33 10 ? 17 6 ? 9 4 ? 5 input sampling time t spl ? 319 ? ? 159 ? ? 79 ? ? 29 ? a/d conversion time t conv 515 ? 530 259 ? 266 131 ? 134 67 ? 68 note: values in the table are the number of states. table 18.4 a/d conversion characteristics (excks1 = 1) (units 1 and 2) cks1 = 0 cks1 = 1 cks = 0 cks = 1 cks = 0 cks = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay time t d 3 ? 10 3 ? 6 3 ? 5 3 ? 4 input sampling time t spl ? 120 ? ? 60 ? ? 30 ? ? 15 ? a/d conversion time t conv 325 ? 332 165 ? 168 85 ? 87 45 ? 46 note: values in the table are the number of states. table 18.5 a/d conversion time (scan mode) (unit 0) cks1 cks2 conversion time (number of states) 0 512 (fixed) 0 1 256 (fixed) 0 128 (fixed) 1 1 64 (fixed) section 18 a/d converter rev. 1.00 sep. 13, 2007 page 800 of 1102 rej09b0365-0100 table 18.6 a/d conversion time (scan mode) (units 1 and 2) excks cks1 cks0 conversion time (number of states) 0 512 (fixed) 0 1 256 (fixed) 0 128 (fixed) 0 1 1 64 (fixed) 0 512 (fixed) 0 1 256 (fixed) 0 128 (fixed) 1 1 1 64 (fixed) 18.4.4 external tr igger input timing a/d conversion can be externally triggered. for unit 0, an external trigger is input from the adtrg0 pin when the trgs1, trgs0, and extrgs bits are set to b'110 in adcr_0. for unit 1, an external trigger is input from either the adtrg1 pin or the adtrg2 pin when the trgs1, trgs0, and extrgs bits are set to either b'110 or b?001 in adcr_1. for unit 2, an external trigger is input from either the adtrg2 pin when the trgs1, trgs0, and extrgs bits are set to b'110 in adcr_2. a/d conversion starts when the adst bit in adcsr is set to 1 on the falling edge of the adtrg pin. other operations, in both single and scan modes, are the same as when the adst bit has been set to 1 by software. figure 18.8 shows the timing. also, a/d conversion for multiple units can be externally triggered (multiple units can start simultaneously). for units 0, 1, and 2, an external trigger is input from the adtrg0 pin when the trgs1, trgs0, and extrgs bits are set to b'111 in adcr_0, adcr_1, and adcr_2. a/d conversion starts when the adst bit in adcsr is set to 1 on the falling edge of the adtrg0 pin. the timing is different from the one when multiple units do not start simultaneously. figure 18.9 shows the timing. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 801 of 1102 rej09b0365-0100 a/d conversion adst p adtrg internal trigger signal figure 18.8 external tr igger input timing (trgs1, trgs0, and extrgs b?111) adtrg adst a/d conversion p internal trigger signal figure 18.9 external trigger input timing when multiple units start simultaneously (trsg1, trgs0, and extrgs = b'111) 18.5 interrupt source the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. setting the adie bit to 1 when the adf bit in adcsr is set to 1 after a/d conversion is completed enables adi interrupt requests. the data transfer controller (dtc)* and dma controller (dmac) can be activated by an adi interrupt. having the converted data read by the dtc* or dmac in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 802 of 1102 rej09b0365-0100 note: * only possible in unit 0. table 18.7 a/d converter interrupt source name interrupt source interrupt fl ag dtc activation dmac activation adi0 a/d conversion end adf possible * possible note: * only possible in unit 0. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 803 of 1102 rej09b0365-0100 18.6 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes. ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 18.10). ? offset error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 18.11). ? full-scale error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 18.11). ? nonlinearity error the error with respect to the ideal a/d convers ion characteristic between the zero voltage and the full-scale voltage. does not in clude the offset error, full-scal e error, or qu antization error (see figure 18.11). ? absolute accuracy the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 804 of 1102 rej09b0365-0100 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 18.9 a/d conversion accuracy definitions fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 18.10 a/d conversion accuracy definitions section 18 a/d converter rev. 1.00 sep. 13, 2007 page 805 of 1102 rej09b0365-0100 18.7 usage notes 18.7.1 module stop function setting operation of the a/d converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the a/d conver ter to be halted. register access is enabled by clearing the module stop state. set the cks1 and cks2 bits to 1 and clear the adst, trgs1, trgs0, and extrgs bits all to 0 to disable a/d conversion when entering module stop state after operation of the a/d converter. after that, se t the module stop contro l register after executing a dummy read by one word. for details, see section 24, power-down modes. 18.7.2 a/d input hold functi on in software standby mode when this lsi enters software standby mode with a/d conversion enabled, the analog inputs are retained, and the analog power supply current is e qual to as during a/d conversion. if the analog power supply current needs to be reduced in software standby mode, set the cks1 and cks2 bits to 1 and clear the adst, trgs1, trgs0, and extrgs bits all to 0 to disable a/d conversion. after that, enter software standby mode af ter executing a dummy read by one word. 18.7.3 permissible si gnal source impedance this lsi's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k ? or less. this specification is provided to enable the a/d converter's sample -and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k ? , charging may be insufficient and it may not be possible to guarantee the a/d convers ion accuracy. however, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 5 k ? , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coe fficient (e.g., 5 mv/ s or greater) (see figure 18.12). when converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 806 of 1102 rej09b0365-0100 equivalent circuit of the a/d converter this lsi 20 pf cin = 15 pf 5 k ? low-pass filter c = 0.1 f (recommended value) sensor output impedance r 5 k ? sensor input figure 18.12 example of analog input circuit 18.7.4 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefor e noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, acting as antennas. 18.7.5 setting range of analog power supply and other pins if the conditions shown below are not met, the relia bility of the lsi may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss v an vref. ? relation between avcc, avss and vcc, vss as the relationship between avcc, avss and vcc, vss, set avcc = vcc 0.3 v and avss = vss. if the a/d converter is not used, set avcc = vcc and avss = vss. ? vref setting range the reference voltage at the vref pin should be set in the range vref avcc. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 807 of 1102 rej09b0365-0100 18.7.6 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. digital circuitry must be isolated from the analog input pins (an0 to an11), analog reference power supply (vref), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable ground (vss) on the board. 18.7.7 notes on no ise countermeasures a protection circuit connected to prevent damage du e to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an11) should be connected between avcc and avss as shown in figure 18.12. also, the bypass capac itors connected to avcc and the filter capacitor connected to the an0 to an11 pins must be connected to avss. if a filter capacitor is connected, the input currents at the an0 to an11 pins are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current in put via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants. section 18 a/d converter rev. 1.00 sep. 13, 2007 page 808 of 1102 rej09b0365-0100 av cc * 1 * 1 vref an0 to an7 av ss notes: values are reference values. 1. 2. r in : input impedance r in * 2 100 ? 0.1 f 0.01 f 10 f figure 18.13 example of analog input protection circuit table 18.8 analog pin specifications item min. max. unit analog input capacitance ? 20 pf permissible signal source impedance ? 5 k ? 20 pf to a/d converter an0 to an11 5 k ? note: values are reference values. figure 18.14 analog input pin equivalent circuit section 19 d/a converter rev. 1.00 sep. 13, 2007 page 809 of 1102 rej09b0365-0100 section 19 d/a converter 19.1 features ? 8-bit resolution ? two output channels ? maximum conversion time of 10 s (with 20 pf load) ? output voltage of 0 v to v ref ? d/a output hold function in software standby mode ? module stop state specifiable module data bus internal data bus vref av cc da1 da0 av ss 8-bit d/a control circuit bus interface [legend] dadr0: d/a data register 0 dadr1: d/a data register 1 dacr01: d/a control register 01 dadr0 dadr1 dacr01 figure 19.1 block di agram of d/a converter section 19 d/a converter rev. 1.00 sep. 13, 2007 page 810 of 1102 rej09b0365-0100 19.2 input/output pins table 19.1 shows the pin configuration of the d/a converter. table 19.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground reference voltage pin vref input d/a conversion reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output 19.3 register descriptions the d/a converter has the following registers. ? d/a data register 0 (dadr0) ? d/a data register 1 (dadr1) ? d/a control register 01 (dacr01) 19.3.1 d/a data registers 0 and 1 (dadr0 and dadr1) dadr0 and dadr1 are 8-bit readable/writable registers that store data to which d/a conversion is to be performed. whenever an analog output is enabled, the values in dadr are converted and output to the analog output pins. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w bit bit name initial value r/w section 19 d/a converter rev. 1.00 sep. 13, 2007 page 811 of 1102 rej09b0365-0100 19.3.2 d/a control register 01 (dacr01) dacr01 controls the operatio n of the d/a converter. 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 r 3 ? 1 r 2 ? 1 r 1 ? 1 r 0 ? 1 r bit bit name initial value r/w bit bit name initial value r/w description 7 daoe1 0 r/w d/a output enable 1 controls d/a conversion and analog output. 0: analog output of channel 1 (da1) is disabled 1: d/a conversion of channel 1 is enabled. analog output of channel 1 (da1) is enabled. 6 daoe0 0 r/w d/a output enable 0 controls d/a conversion and analog output. 0: analog output of channel 0 (da0) is disabled 1: d/a conversion of channel 0 is enabled. analog output of channel 0 (da0) is enabled. 5 dae 0 r/w d/a enable used together with the daoe0 and daoe1 bits to control d/a conversion. when this bit is cleared to 0, d/a conversion is controlled independently for channels 0 and 1. when this bit is set to 1, d/a conversion for channels 0 and 1 is controlled together. output of conversion results is always controlled by the daoe0 and daoe1 bits. for details, see table 19.2, control of d/a conversion. 4 to 0 ? all 1 r reserved these are read-only bits and cannot be modified. section 19 d/a converter rev. 1.00 sep. 13, 2007 page 812 of 1102 rej09b0365-0100 table 19.2 control of d/a conversion bit 5 dae bit 7 daoe1 bit 6 daoe0 description 0 0 0 d/a conversion is disabled. 1 d/a conversion of channel 0 is enabled and d/a conversion of channel 1 is disabled. analog output of channel 0 (da0) is enabled and analog output of channel 1 (da1) is disabled. 1 0 d/a conversion of channel 0 is disabled and d/a conversion of channel 1 is enabled. analog output of channel 0 (da0) is disabled and analog output of channel 1 (da1) is enabled. 1 d/a conversion of channels 0 and 1 is enabled. analog output of channels 0 and 1 (da0 and da1) is enabled. 1 0 0 d/a conversion of channels 0 and 1 is enabled. analog output of channels 0 and 1 (da0 and da1) is disabled. 1 d/a conversion of channels 0 and 1 is enabled. analog output of channel 0 (da0) is enabled and analog output of channel 1 (da1) is disabled. 1 0 d/a conversion of channels 0 and 1 is enabled. analog output of channel 0 (da0) is disabled and analog output of channel 1 (da1) is enabled. 1 d/a conversion of channels 0 and 1 is enabled. analog output of channels 0 and 1 (da0 and da1) is enabled. section 19 d/a converter rev. 1.00 sep. 13, 2007 page 813 of 1102 rej09b0365-0100 19.4 operation the d/a converter includes d/a conversion circuits for two channels, each of which can operate independently. when the daoe bit in dacr01 is set to 1, d/a conversion is enabled and the conversion result is output. an operation example of d/a conversion on channel 0 is shown below. figure 19.2 shows the timing of this operation. 1. write the conversion data to dadr0. 2. set the daoe0 bit in dacr01 to 1 to start d/a conversion. the conversion result is output from the analog output pin da0 after the conversion time t dconv has elapsed. the conversion result continues to be output until dadr0 is writte n to again or the daoe0 bit is cleared to 0. the output value is expressed by the following formula: contents of dadr/256 v ref 3. if dadr0 is written to again, the conversion is immediately started. the conversion result is output after the conversion time t dconv has elapsed. 4. if the daoe0 bit is cleared to 0, analog output is disabled. conversion data 1 conversion result 1 high-impedance state t dconv dadr0 write cycle da0 daoe0 dadr0 address p dacr01 write cycle conversion data 2 conversion result 2 t dconv [legend] t dconv : d/a conversion time dadr0 write cycle dacr01 write cycle figure 19.2 example of d/a converter operation section 19 d/a converter rev. 1.00 sep. 13, 2007 page 814 of 1102 rej09b0365-0100 19.5 usage notes 19.5.1 module stop state setting operation of the d/a converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the d/a conver ter to be halted. register access is enabled by clearing the module stop stat e. for details, refer to section 24, power-down modes. 19.5.2 d/a output hold function in software standby mode when this lsi enters software standby mode w ith d/a conversion enable d, the d/a outputs are retained, and the analog power supply current is equal to as during d/a conversion. if the analog power supply current needs to be reduced in software standby mode, clear the adst, trgs1, and trgs0 bits all to 0 to disable d/a conversion. section 20 ram rev. 1.00 sep. 13, 2007 page 815 of 1102 rej09b0365-0100 section 20 ram this lsi has a high-speed static ram. the ram is connected to the cpu by a 32-bit data bus, enabling one-state access by the cpu to all byte data, word data, and longword data. the ram can be enabled or disabled by means of the rame bit in the sy stem control register (syscr). for details on syscr, refer to section 3.2.2, system control register (syscr). the ram size is 56 kbytes in th e h8sx/1648, 40 kbytes in the h8 sx/1644, and 24 kbytes in the h8sx/1642. product classification ram size ram addresses h8sx/1642 24 kbytes h'ff6000 to h'ffbfff h8sx/1644 40 kbytes h'ff2000 to h'ffbfff flash memory version h8sx/1648 56 kbytes h?fee200 to h?ffbfff section 20 ram rev. 1.00 sep. 13, 2007 page 816 of 1102 rej09b0365-0100 section 21 flash memory rev. 1.00 sep. 13, 2007 page 817 of 1102 rej09b0365-0100 section 21 flash memory the flash memory has the followin g features. figure 21.1 is a bloc k diagram of the flash memory. 21.1 features ? rom size product classification rom size rom address h8sx/1642 r5f61642 256 kbyt es h'000000 to h'03ffff (modes 1, 2, 3, 6, and 7) h8sx/1644 r5f61644 512 kbyt es h'000000 to h'07ffff (modes 1, 2, 3, 6, and 7) h8sx/1648 r5f61648 1 mbyt e h'000000 to h'0fffff (modes 1, 2, 3, 6, and 7) ? two memory mats the start addresses of two memory spaces (memor y mats) are allocated to the same address. the mode setting in the initiation determines which memory mat is initiated first. the memory mats can be switched by using the bank-switching method after initiation. ? user mat initiated at a reset in user mode: 256 kbytes/512 kbytes/1 mbyte ? user boot mat is initiated at reset in user boot mode: 16 kbytes ? programming/erasing interface by the download of on-chip program this lsi has a programming/erasing program. after downloading this program to the on-chip ram, programming/erasure can be performed by setting the parameters. ? programming/erasing time programming time: 1 ms (typ.) for 128-byte simultaneous programming erasing time: 600 ms (typ.) per 1 block (64 kbytes) ? number of programming the number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) ? three on-board programming modes boot mode: using the on-chip sci_4, the user mat and user boot mat can be programmed/erased. in boot mode, the bit rate be tween the host and this lsi can be adjusted automatically. user program mode: using a desired interface, the user mat can be programmed/erased. section 21 flash memory rev. 1.00 sep. 13, 2007 page 818 of 1102 rej09b0365-0100 user boot mode: using a desired interface, the user boot program can be made and the user mat can be programmed/erased. ? off-board programming mode programmer mode: using a prom programmer, the user mat and user boot mat can be programmed/erased. ? programming/erasing protection protection against programming/erasure of the flash memory can be set by hardware protection, software protection, or error protection. ? flash memory emulation function using the on-chip ram realtime emulation of the flash memory progra mming can be performed by overlaying parts of the flash memory (user mat) area and the on-chip ram. section 21 flash memory rev. 1.00 sep. 13, 2007 page 819 of 1102 rej09b0365-0100 fccs fpcs fecs fkey fmats ftdar ramer control unit memory mat unit flash memory user mat: 256 kbytes (h8sx/1642) 512 kbytes (h8sx/1644) 1 mbyte (h8sx/1648) user boot mat: 16 kbytes operating mode module bus mode pins internal data bus (32 bits) internal address bus [legend] fccs: flash code control/status register fpcs: flash program code select register fecs: flash erase code select register fkey: flash key code register fmats: flash mat select register ftdar: flash transfer destination address register ramer: ram emulation register figure 21.1 block diagram of flash memory section 21 flash memory rev. 1.00 sep. 13, 2007 page 820 of 1102 rej09b0365-0100 21.2 mode transition diagram when the mode pins are set in the reset state an d reset start is performed, this lsi enters each operating mode as shown in figure 21.2. although the flash memory can be read in user mode, it cannot be programmed or erased. the flash memory can be programmed or erased in boot mode, user program mode, user boot mode, and programmer mode. the differences between boot mode, user program mode, user boot mode, and programmer mode are shown in table 21.1. reset state programmer mode user mode user program mode user boot mode boot mode on-board programming mode res = 0 res = 0 user mode setting user boot mode setting res = 0 boot mode sett ing res = 0 res = 0 programmer mode setting * 1 ram emulation can be available rom disabled mode res = 0 rom disabled mode setting * 2 notes: * in this lsi, the user program mode is defined as the period from the timing when a program concerning programming and erasure is started in user mode to the timing when the program is completed. 1. programming and erasure is started. 2. programing and erasure is completed. figure 21.2 mode transition of flash memory section 21 flash memory rev. 1.00 sep. 13, 2007 page 821 of 1102 rej09b0365-0100 table 21.1 differences between boot mode , user program mode, user boot mode, and programmer mode item boot mode user program mode user boot mode programmer mode programming/ erasing environment on-board programming on-board programming on-board programming off-board programming programming/ erasing enable mat ? user mat ? user boot mat ? user mat ? user mat ? user mat ? user boot mat programming/ erasing control command programming/ erasing interface programming/ erasing interface command all erasure o (automatic) o o o (automatic) block division erasure o * 1 o o program data transfer from host via sci from desired device via ram from desired device via ram via programmer ram emulation o o reset initiation mat embedded program storage area user mat user boot mat * 2 ? transition to user mode changing mode and reset completing programming/ erasure * 3 changing mode and reset ? notes: 1. all-erasure is performed. afte r that, the specified block can be erased. 2. first, the reset vector is fetched from the embedded program storage area. after the flash memory related registers are checked, the reset vector is fetched from the user boot mat. 3. in this lsi, the user programming mode is defined as the period from the timing when a program concerning programming and erasur e is started to the timing when the program is completed. for details on a program concerning programming and erasure, see section 21.8.2, user program mode. section 21 flash memory rev. 1.00 sep. 13, 2007 page 822 of 1102 rej09b0365-0100 21.3 memory mat configuration the memory mats of flash memory in this lsi consists of the 256-kbyte/512-kbyte/1-mbyte user mat and 16-kbyte user boot mat. the start addresses of the user mat and user boot mat are allocated to the same address. therefore, when the program execution or data access is performed between the two memory mats, the me mory mats must be sw itched by the flash mat select register (fmats). the user mat or user boot mat can be read in all modes. however, the user boot mat can be programmed or erased only in boot mode and programmer mode. the size of the user mat is different from that of the user boot mat. addresses which exceed the size of the 16-kbyte user boot mat should not be accessed. if an attempt is made, data is read as an undefined value. user mat user boot mat h'000000 h'07ffff * 2 notes: 1. 256 kbytes in the h8sx/1642. 1 mbyte in the h8sx/1648. 2. h'03ffff in the h8sx/1642. h'0fffff in the h8sx/1648. h'000000 h'003fff 512 kbytes * 1 16 kbytes figure 21.3 memory mat configuration (h8sx/1644) section 21 flash memory rev. 1.00 sep. 13, 2007 page 823 of 1102 rej09b0365-0100 21.4 block structure 21.4.1 block diagram of h8sx/1642k figure 21.4 (1) shows the block structure of the 256-kbyte user mat. the heavy-line frames indicate the erase blocks. the thin-line frames indicate the programming units and the values inside the frames stand for the addresses. the user mat is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the user mat can be erased in these divided block units. programming is done in 128-byte units starting from where the lower address is h'00 or h'80. ram emulation can be performed in the eight 4-kbyte blocks. eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 4 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes eb8 erase unit: 32 kbytes eb9 erase unit: 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'004f80 h'004f81 h'004f82 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 h'005f80 h'005f81 h'005f82 h'006f80 h'006f81 h'006f82 h'007f80 h'007f81 h'007f82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eb10 eb11 erase unit: 64 kbytes h'03ffff h'02007f h'03007f programming unit: 128 bytes programming unit: 128 bytes h'020000 h'020001 h'020002 h'030000 h'030001 h'030002 h'02ff80 h'02ff81 h'02ff82 h'03ff80 h'03ff81 h'03ff82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h'02ffff figure 21.4 user mat bloc k structure of h8sx/1642 section 21 flash memory rev. 1.00 sep. 13, 2007 page 824 of 1102 rej09b0365-0100 21.4.2 block diagram of h8sx/1644 figure 21.4 (2) shows the block structure of the 512-kbyte user mat. the heavy-line frames indicate the erase blocks. the thin-line frames indicate the programming units and the values inside the frames stand for the addresses. the user mat is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the user mat can be erased in these divided block units. programming is done in 128-byte units starting from where the lower address is h'00 or h'80. ram emulation can be performed in the eight 4-kbyte blocks. eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 4 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes eb8 erase unit: 32 kbytes eb9 erase unit: 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'004f80 h'004f81 h'004f82 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 h'005f80 h'005f81 h'005f82 h'006f80 h'006f81 h'006f82 h'007f80 h'007f81 h'007f82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eb10 eb15 erase unit: 64 kbytes h'07ffff h'02007f h'07007f programming unit: 128 bytes programming unit: 128 bytes h'020000 h'020001 h'020002 h'070000 h'070001 h'070002 h'0aff80 h'0aff81 h'0aff82 h'07ff80 h'07ff81 h'07ff82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 21.4 user mat bloc k structure of h8sx/1644 section 21 flash memory rev. 1.00 sep. 13, 2007 page 825 of 1102 rej09b0365-0100 21.4.3 block diagram of h8sx/1648 figure 21.4 (3) shows the block structure of the 1-mbyte user mat. the heavy-line frames indicate the erase blocks. the thin-line frames indicate the programming units and the values inside the frames stand for the addresses. the user mat is divided into fifteen 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the user mat can be erased in these divided block units. programming is done in 128-byte units starting from where the lower address is h'00 or h'80. ram emulation can be performed in the eight 4-kbyte blocks. eb0 erase unit: 4 kbytes eb1 erase unit: 4 kbytes eb2 erase unit: 4 kbytes eb3 erase unit: 4 kbytes eb4 erase unit: 4 kbytes eb5 erase unit: 4 kbytes eb6 erase unit: 4 kbytes eb7 erase unit: 4 kbytes eb8 erase unit: 32 kbytes eb9 erase unit: 64 kbytes h'000000 h'000001 h'000002 h'00007f h'000fff h'00107f h'00207f h'00307f h'00407f h'004fff h'00507f h'005fff h'001fff h'002fff h'003fff h'01ffff h'00607f h'006fff h'00707f h'007fff h'00807f h'00ffff h'01007f programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'001000 h'001001 h'001002 h'002000 h'002001 h'002002 h'003000 h'003001 h'003002 h'004000 h'004001 h'004002 h'005000 h'005001 h'005002 h'006000 h'006001 h'006002 h'007000 h'007001 h'007002 h'008000 h'008001 h'008002 h'010000 h'010001 h'010002 h'000f80 h'000f81 h'000f82 h'001f80 h'001f81 h'001f82 h'002f80 h'002f81 h'002f82 h'003f80 h'003f81 h'003f82 h'004f80 h'004f81 h'004f82 h'00ff80 h'00ff81 h'00ff82 h'01ff80 h'01ff81 h'01ff82 h'005f80 h'005f81 h'005f82 h'006f80 h'006f81 h'006f82 h'007f80 h'007f81 h'007f82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eb10 eb23 erase unit: 64 kbytes h'0fffff h'02007f h'0f007f programming unit: 128 bytes programming unit: 128 bytes h'020000 h'020001 h'020002 h'0f0000 h'0f0001 h'0f0002 h'0eff80 h'0eff81 h'0eff82 h'0fff80 h'0fff81 h'0fff82 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 21.4 user mat bloc k structure of h8sx/1648 section 21 flash memory rev. 1.00 sep. 13, 2007 page 826 of 1102 rej09b0365-0100 21.5 programming/erasing interface programming/erasure of the flash memory is done by downloading an on-chip programming/ erasing program to the on-chip ram and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming /erasing interface parameters. the procedure program for user program mode and user boot mode is made by the user. figure 21.5 shows the procedure for crea ting the procedure program. for de tails, see section 21.8.2, user program mode. download on-chip program by setting vbr, fkey, and sco bit in fccs yes no execute initialization (downloaded program execution) select on-chip program to be downloaded and specify destination programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) start procedure program for programming/erasing end procedure program programming/erasing completed? figure 21.5 procedure for creating procedure program (1) selection of on-chip pr ogram to be downloaded this lsi has programming/erasing programs which can be downloaded to the on-chip ram. the on-chip program to be downloaded is selected by the programming /erasing interface registers. the start address of the on-chip ram where an on-chip program is downloaded is specified by the flash transfer destination address register (ftdar). section 21 flash memory rev. 1.00 sep. 13, 2007 page 827 of 1102 rej09b0365-0100 (2) download of on-chip program the on-chip program is automatically downloaded by setting the flash key code register (fkey) and the sco bit in the flash code control/status re gister (fccs) after initializing the vector base register (vbr). the memory mat is replaced w ith the embedded progra m storage area during download. since the memory mat cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip ram). since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. the vbr contents can be changed after completion of download. (3) initialization of programming/erasure a pulse with the specified period must be applied when programming or erasing. the specified pulse width is made by the method in which wait loop is configured by the cpu instruction. accordingly, the operating frequency of the cpu needs to be set before programming/erasure. the operating frequency of the cpu is set by th e programming/erasing interface parameter. (4) execution of programming/erasure the start address of the programming destination and the program data are specified in 128-byte units when programming. the block to be erased is specified with the erase block number in erase-block units when erasing. specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. the on-chip program is executed by using the jsr or bsr instruction and executing the subroutin e call of the specified address in the on-chip ram. the execution result is returned to the programming/erasing interface parameter. the area to be programmed must be erased in advance when programming flash memory. all interrupts are disabled duri ng programming/erasure. (5) when programming/erasure is executed consecutively when processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasure can be reali zed by updating the st art address of the programming destination and program data, or the erase block number. since the downloaded on-chip program is left in the on-chip ram even after programming/erasure co mpletes, download and initialization are not required when the same processing is executed consecutively. section 21 flash memory rev. 1.00 sep. 13, 2007 page 828 of 1102 rej09b0365-0100 21.6 input/output pins the flash memory is controlled through the input/output pins shown in table 21.2. table 21.2 pin configuration abbreviation i/o function res input reset emle input on-chip emulator enable pin (emle = 0 for flash memory programming/erasure) md2 to md0 input set operating mode of this lsi txd4 output serial transmit data output (used in boot mode) rxd4 input serial receive data input (used in boot mode) 21.7 register descriptions the flash memory has th e following registers. programming/erasing interface registers: ? flash code control/status register (fccs) ? flash program code sel ect register (fpcs) ? flash erase code select register (fecs) ? flash key code register (fkey) ? flash mat select register (fmats) ? flash transfer destination address register (ftdar) programming/erasing interface parameters: ? download pass and fail result parameter (dpfr) ? flash pass and fail result parameter (fpfr) ? flash program/erase frequency parameter (fpefeq) ? flash multipurpose address area parameter (fmpar) ? flash multipurpose data destination area parameter (fmpdr) ? flash erase block select parameter (febs) ? ram emulation register (ramer) section 21 flash memory rev. 1.00 sep. 13, 2007 page 829 of 1102 rej09b0365-0100 there are several operating modes for accessing th e flash memory. respecti ve operating modes, registers, and parameters are assigned to the user mat and user boot mat. the correspondence between operating modes and registers/parameters for use is shown in table 21.3. table 21.3 registers/parameters and target modes register/parameter down- load initiali- zation program- ming erasure read ram emulation fccs o ? ? ? ? ? fpcs o ? ? ? ? ? fecs o ? ? ? ? ? fkey o ? o o ? ? fmats ? ? o * 1 o * 1 o * 2 ? programming/ erasing interface registers ftdar o ? ? ? ? ? dpfr o ? ? ? ? ? fpfr ? o o o ? ? fpefeq ? o ? ? ? ? fmpar ? ? o ? ? ? fmpdr ? ? o ? ? ? programming/ erasing interface parameters febs ? ? ? o ? ? ram emulation ramer ? ? ? ? ? o notes: 1. the setting is required when programming or erasing the user mat in user boot mode. 2. the setting may be required according to the combination of initiation mode and read target memory mat. 21.7.1 programming/erasing interface registers the programming/erasing interface re gisters are 8-bit registers that can be accessed only in bytes. these registers are initialized by a reset. (1) flash code control/status register (fccs) fccs monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip ram. section 21 flash memory rev. 1.00 sep. 13, 2007 page 830 of 1102 rej09b0365-0100 7 ? 1 r 6 ? 0 r 5 ? 0 r 4 fler 0 r 3 ? 0 r 0 sco 0 (r)/w 2 ? 0 r 1 ? 0 r bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 ? ? ? 1 0 0 r r r reserved these are read-only bits and cannot be modified. 4 fler 0 r flash memory error indicates that an error has occurred during programming or erasing the flash memory. when this bit is set to 1, the flash memory enters the error protection state. when this bit is set to 1, high voltage is applied to the internal flash memory. to reduce the damage to the flash memory, the reset must be released after the reset input period (period of res = 0) of at least 100 s. 0: flash memory operates normally (error protection is invalid) [clearing condition] ? at a reset 1: an error occurs during programming/erasing flash memory (error protection is valid) [setting conditions] ? when an interrupt, such as nmi, occurs during programming/erasure. ? when the flash memory is read during programming/erasure (including a vector read and an instruction fetch). ? when the sleep instruction is executed during programming/erasure (including software standby mode). ? when a bus master other than the cpu, such as the dmac and dtc, obtains bus mastership during programming/erasure. section 21 flash memory rev. 1.00 sep. 13, 2007 page 831 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 sco 0 (r)/w * source program copy operation requests the on-chip programming/erasing program to be downloaded to the on-chip ram. when this bit is set to 1, the on-chip program which is selected by fpcs or fecs is automatically downloaded in the on-chip ram area specified by ftdar. in order to set this bit to 1, the ram emulation mode must be canceled, h'a5 mu st be written to fkey, and this operation must be executed in the on-chip ram. dummy read of fccs must be executed twice immediately after setting this bit to 1. all interrupts must be disabled during download. this bit is cleared to 0 when download is completed. during program download initiated with this bit, particular processing which accompanies bank- switching of the program storage area is executed. before a download request, initialize the vbr contents to h'00000000. after download is completed, the vbr contents can be changed. 0: download of the program ming/erasing program is not requested. [clearing condition] ? when download is completed 1: download of the progr amming/erasing program is requested. [setting conditions] (when all of the following conditions are satisfied) ? not in ram emulation mode (the rams bit in ramer is cleared to 0) ? h'a5 is written to fkey ? setting of this bit is executed in the on-chip ram note: * this is a write-only bit. this bit is always read as 0. section 21 flash memory rev. 1.00 sep. 13, 2007 page 832 of 1102 rej09b0365-0100 (2) flash program code select register (fpcs) fpcs selects the programming program to be downloaded. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 ppvs 0 r/w 2 ? 0 r 1 ? 0 r bit bit name initial value r/w bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 ppvs 0 r/w program pulse verify selects the programming program to be downloaded. 0: programming program is not selected. [clearing condition] when transfer is completed 1: programming program is selected. (3) flash erase code select register (fecs) fecs selects the erasing program to be downloaded. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 epvb 0 r/w 2 ? 0 r 1 ? 0 r bit bit name initial value r/w bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these are read-only bits and cannot be modified. 0 epvb 0 r/w erase pulse verify block selects the erasing program to be downloaded. 0: erasing program is not selected. [clearing condition] when transfer is completed 1: erasing program is selected. section 21 flash memory rev. 1.00 sep. 13, 2007 page 833 of 1102 rej09b0365-0100 (4) flash key code register (fkey) fkey is a register for software protection that enables to download the on-chip program and perform programming/erasure of the flash memory. 7 k7 0 r/w 6 k6 0 r/w 5 k5 0 r/w 4 k4 0 r/w 3 k3 0 r/w 0 k0 0 r/w 2 k2 0 r/w 1 k1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 6 5 4 3 2 1 0 k7 k6 k5 k4 k3 k2 k1 k0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w key code when h'a5 is written to fkey, writing to the sco bit in fccs is enabled. when a value other than h'a5 is written, the sco bit cannot be set to 1. therefore, the on-chip program cannot be downloaded to the on-chip ram. only when h'5a is written can programming/erasure of the flash memory be executed. when a value other than h'5a is written, even if the programming/erasing program is executed, progr amming/erasure cannot be performed. h'a5: writing to the sco bit is enabled. (the sco bit cannot be set to 1 when fkey is a value other than h'a5.) h'5a: programming/erasure of the flash memory is enabled. (when fkey is a value other than h'a5, the software protecti on state is entered.) h'00: initial value section 21 flash memory rev. 1.00 sep. 13, 2007 page 834 of 1102 rej09b0365-0100 (5) flash mat select register (fmats) fmats selects the user mat or user boot mat. writing to fmats should be done when a program in the on-chip ram is being executed. 7 ms7 0/1 * r/w 6 ms6 0 r/w 5 ms5 0/1 * r/w 4 ms4 0 r/w 3 ms3 0/1 * r/w 0 ms0 0 r/w 2 ms2 0 r/w 1 ms1 0/1 * r/w bit bit name initial value r/w note: * this bit is set to 1 in user boot mode, otherwise cleared to 0. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 r/w r/w r/w r/w r/w r/w r/w r/w mat select the memory mats can be switched by writing a value to fmats. when h'aa is written to fmats, the user boot mat is selected. when a value other than h'aa is written, the user mat is selected. switch the mats following the memory mat switching procedure in section 21.11, switching between user mat and user boot mat. the user boot mat cannot be selected by fmats in user programming mode. the user boot mat can be selected in boot mode or programmer mode. h'aa: the user boot mat is selected. (the user mat is selected when fmats is a value other than h'aa.) (initial value when initiated in user boot mode.) h'00: the user mat is selected. (initial value when initiated in a mode except for user boot mode.) note: * this bit is set to 1 in user boot mode, otherwise cleared to 0. section 21 flash memory rev. 1.00 sep. 13, 2007 page 835 of 1102 rej09b0365-0100 (6) flash transfer destination address register (ftdar) ftdar specifies the start address of the on-chip ram at which to download an on-chip program. ftdar must be set before setting the sco bit in fccs to 1. 7 tder 0 r/w 6 tda6 0 r/w 5 tda5 0 r/w 4 tda4 0 r/w 3 tda3 0 r/w 0 tda0 0 r/w 2 tda2 0 r/w 1 tda1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 tder 0 r/w transfer destination address setting error this bit is set to 1 when an error has occurred in setting the start address specified by bits tda6 to tda0. a start address error is determined by whether the value set in bits tda6 to tda0 is within the range of h'00 to h'02 when download is executed by setting the sco bit in fccs to 1. make sure t hat this bit is cleared to 0 before setting the sco bit to 1 and the value specified by bits tda6 to tda0 should be within the range of h'00 to h'02. 0: the value specified by bits tda6 to tda0 is within the range. 1: the value specified by bits tda6 to tda0 is between h'03 and h'ff and down load has stopped. 6 5 4 3 2 1 0 tda6 tda5 tda4 tda3 tda2 tda1 tda0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w transfer destination address specifies the on-chip ram start address of the download destination. a value between h'00 and h'02, and up to 4 kbytes can be specified as the start address of the on-chip ram. h'00: h'ff9000 is specifi ed as the start address. h'01: h'ffa000 is specifi ed as the start address. h'02: h'ffb000 is specifi ed as the start address. h'03 to h'7f: setting prohibited. (specifying a value from h'03 to h'7f sets the tder bit to 1 and stops download of the on-chip program.) section 21 flash memory rev. 1.00 sep. 13, 2007 page 836 of 1102 rej09b0365-0100 21.7.2 programming/erasing interface parameters the programming/erasing interface parameters speci fy the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. these parameters use the gene ral registers of the cpu (er0 and er1) or the on-chip ram area. the initial values of programmi ng/erasing interface parameters are undefined at a reset or a transition to software standby mode. since registers of the cpu except for er0 and er1 are saved in the stack area during download of an on-chip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). the return value of the processing result is written in r0. the programmi ng/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. table 21.4 shows the usable parameters and target modes. the meaning of the bits in the flash pass and fail result parameter (fpfr) varies in in itialization, programming, and erasure. table 21.4 parameters and target modes parameter download initialization programming erasure r/w initial value allocation dpfr o ? ? ? r/w undefined on-chip ram * fpfr o o o o r/w undefined r0l of cpu fpefeq ? o ? ? r/w undefined er0 of cpu fmpar ? ? o ? r/w undefined er1 of cpu fmpdr ? ? o ? r/w undefined er0 of cpu febs ? ? ? o r/w undefined er0 of cpu note: * a single byte of the start address of the on-chip ram specified by ftdar download control: the on-chip program is automatically downloaded by setting the sco bit in fccs to 1. the on-chip ram area to download th e on-chip program is th e 4-kbyte area starting from the start address specified by ftdar. download is set by the programming/e rasing interface registers, and the download pass and fail result parameter (dpfr) indicates the return value. section 21 flash memory rev. 1.00 sep. 13, 2007 page 837 of 1102 rej09b0365-0100 initialization before programming/erasure: the on-chip program includes the initialization program. a pulse with the specified period must be applied when programming or erasing. the specified pulse width is made by the method in which wait loop is configured by the cpu instruction. accordingly, the operating frequency of the cpu must be set. the initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. programming: when the flash memory is programmed , the start address of the programming destination on the user mat and the program data must be passed to the programming program. the start address of the programming destination on the user mat must be stored in general register er1. this parameter is called the flas h multipurpose address area parameter (fmpar). the program data is always in 128-byte units. when the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling th e dummy code (h'ff). the boundary of the start address of the programming destination on the user mat is aligned at an address where the lower eight bits (a7 to a0) are h'00 or h'80. the program data for the user mat must be prep ared in consecutive areas. the program data must be in a consecutive space which can be accessed using the mov.b in struction of the cpu and is not in the flash memory space. the start address of the area that stores the data to be written in the user mat must be set in general register er0. this parameter is called the flash multipurpose data destination area parameter (fmpdr). for details on the programming procedure, see section 21.8.2, user program mode. erasure: when the flash memory is erased, the eras e block number on the user mat must be passed to the erasing program which is downloaded. the erase block number on the user mat must be set in general register er0. this parameter is called the flash erase block select parameter (febs). one block is selected from the block numbers of 0 to 19 as the erase block number. for details on the erasing procedure, see section 21.8.2, user program mode. section 21 flash memory rev. 1.00 sep. 13, 2007 page 838 of 1102 rej09b0365-0100 (1) download pass and fail result parameter (d pfr: single byte of start address in on- chip ram specified by ftdar) dpfr indicates the return value of the download result. the dpfr value is used to determine the download result. 7 ? 6 ? 5 ? 4 ? 3 ? 0 sf 2 ss 1 fk bit bit name bit bit name initial value r/w description 7 to 3 ? ? ? unused these bits return 0. 2 ss ? r/w source select error detect only one type can be specified for the on-chip program which can be downloaded. when the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: download program selection is normal 1: download program selection is abnormal 1 fk ? r/w flash key register error detect checks the fkey value (h'a5) and returns the result. 0: fkey setting is normal (h'a5) 1: fkey setting is abnormal (value other than h'a5) 0 sf ? r/w success/fail returns the download result. reads back the program downloaded to the on-chip ram and determines whether it has been transferred to the on-chip ram. 0: download of the program has ended normally (no error) 1: download of the program has ended abnormally (error occurs) section 21 flash memory rev. 1.00 sep. 13, 2007 page 839 of 1102 rej09b0365-0100 (2) flash pass and fail parameter (fpf r: general register r0l of cpu) fpfr indicates the return values of the initia lization, programming, and erasure results. the meaning of the bits in fpfr varies depending on the processing. (a) initialization be fore programming/erasure fpfr indicates the return valu e of the initialization result. 7 ? 6 ? 5 ? 4 ? 3 ? 0 sf 2 ? 1 fq bit bit name bit bit name initial value r/w description 7 to 2 ? ? ? unused these bits return 0. 1 fq ? r/w frequency error detect compares the specified cp u operating frequency with the operating frequencies supported by this lsi, and returns the result. 0: setting of operating frequency is normal 1: setting of operating frequency is abnormal 0 sf ? r/w success/fail returns the initialization result. 0: initialization has ended normally (no error) 1: initialization has ended abnormally (error occurs) section 21 flash memory rev. 1.00 sep. 13, 2007 page 840 of 1102 rej09b0365-0100 (b) programming fpfr indicates the return valu e of the programming result. 7 ? 6 md 5 ee 4 fk 3 ? 0 sf 2 wd 1 wa bit bit name bit bit name initial value r/w description 7 ? ? ? unused returns 0. 6 md ? r/w programming mode related setting error detect detects the error protection state and returns the result. when the error protection state is entered, this bit is set to 1. whether the error prot ection state is entered or not can be confirmed with the fler bit in fccs. for conditions to enter the error protection state, see section 21.9.3, error protection. 0: normal operation (fler = 0) 1: error protection state, and programming cannot be performed (fler = 1) 5 ee ? r/w programming execution error detect writes 1 to this bit when t he specified data could not be written because the user mat was not erased. if this bit is set to 1, there is a high possibility that the user mat has been written to partially. in this case, after removing the error factor, erase the user mat. if fmats is set to h'aa and the user boot mat is selected, an error occurs when programming is performed. in this case, both the user mat and user boot mat have not been written to. programming the user boot mat should be performed in boot mode or programmer mode. 0: programming has ended normally 1: programming has ended abnormally (programming result is not guaranteed) section 21 flash memory rev. 1.00 sep. 13, 2007 page 841 of 1102 rej09b0365-0100 bit bit name initial value r/w description 4 fk ? r/w flash key register error detect checks the fkey value (h'5a) before programming starts, and returns the result. 0: fkey setting is normal (h'5a) 1: fkey setting is abnormal (value other than h'5a) 3 ? ? ? unused returns 0. 2 wd ? r/w write data address detect when an address not in the flash memory area is specified as the start addres s of the storage destination for the program data, an error occurs. 0: setting of the start addres s of the storage destination for the program data is normal 1: setting of the start addres s of the storage destination for the program data is abnormal 1 wa ? r/w write address error detect when the following items are specified as the start address of the programming destination, an error occurs. ? an area other than flash memory ? the specified address is not aligned with the 128- byte boundary (lower eight bits of the address are other than h'00 and h'80) 0: setting of the start address of the programming destination is normal 1: setting of the start address of the programming destination is abnormal 0 sf ? r/w success/fail returns the programming result. 0: programming has ended normally (no error) 1: programming has ended abnormally (error occurs) section 21 flash memory rev. 1.00 sep. 13, 2007 page 842 of 1102 rej09b0365-0100 (c) erasure fpfr indicates the return va lue of the erasure result. 7 ? 6 md 5 ee 4 fk 3 eb 0 sf 2 ? 1 ? bit bit name bit bit name initial value r/w description 7 ? ? ? unused returns 0. 6 md ? r/w erasure mode related setting error detect detects the error protection state and returns the result. when the error protection state is entered, this bit is set to 1. whether the error prot ection state is entered or not can be confirmed with the fler bit in fccs. for conditions to enter the error protection state, see section 21.9.3, error protection. 0: normal operation (fler = 0) 1: error protection state, and programming cannot be performed (fler = 1) 5 ee ? r/w erasure execution error detect returns 1 when the user mat could not be erased or when the flash memory related register settings are partially changed. if this bit is set to 1, there is a high possibility that the user mat has been erased partially. in this case, afte r removing the error factor, erase the user mat. if fmats is set to h'aa and the user boot mat is selected, an error occurs when erasure is performed. in this case, both the user mat and user boot mat have not been erased. erasing of the user boot mat should be performed in boot mode or programmer mode. 0: erasure has ended normally 1: erasure has ended abnormally section 21 flash memory rev. 1.00 sep. 13, 2007 page 843 of 1102 rej09b0365-0100 bit bit name initial value r/w description 4 fk ? r/w flash key register error detect checks the fkey value (h'5a) before erasure starts, and returns the result. 0: fkey setting is normal (h'5a) 1: fkey setting is abnormal (value other than h'5a) 3 eb ? r/w erase block select error detect checks whether the specified erase block number is in the block range of the user mat, and returns the result. 0: setting of erase block number is normal 1: setting of erase block number is abnormal 2, 1 ? ? ? unused these bits return 0. 0 sf ? r/w success/fail indicates the erasure result. 0: erasure has ended normally (no error) 1: erasure has ended abnormally (error occurs) (3) flash program/erase frequency paramet er (fpefeq: general register er0 of cpu) fpefeq sets the operating frequency of the cpu. the operating frequency available in this lsi ranges from 8 mhz to 35 mhz. 31 ? 30 ? 29 ? 28 ? 27 ? 24 ? 26 ? 25 ? bit bit name 23 ? 22 ? 21 ? 20 ? 19 ? 16 ? 18 ? 17 ? bit bit name 15 f15 14 f14 13 f13 12 f12 11 f11 8 f8 10 f10 9 f9 bit bit name 7 f7 6 f6 5 f5 4 f4 3 f3 0 f0 2 f2 1 f1 bit bit name section 21 flash memory rev. 1.00 sep. 13, 2007 page 844 of 1102 rej09b0365-0100 bit bit name initial value r/w description 31 to 16 ? ? ? unused these bits should be cleared to 0. 15 to 0 f15 to f0 ? r/w frequency set these bits set the operating frequency of the cpu. when the pll multiplication function is used, set the multiplied frequency. the setting value must be calculated as follows: 1. the operating frequency shown in mhz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. the value multiplied by 100 is converted to the binary digit and is written to fpefeq (general register er0). for example, when the oper ating frequency of the cpu is 35.000 mhz, the value is as follows: 1. the number of three decim al places of 35.000 is rounded. 2. the formula of 35.00 100 = 3500 is converted to the binary digit and b'0000 1101 1010 1100 (h'0dac) is set to er0. section 21 flash memory rev. 1.00 sep. 13, 2007 page 845 of 1102 rej09b0365-0100 (4) flash multipurpose address area parame ter (fmpar: general register er1 of cpu) fmpar stores the start address of the programming destination on the user mat. when an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. the error occurrence is indicated by the wa bit in fpfr. 31 moa31 30 moa30 29 moa29 28 moa28 27 moa27 24 moa24 26 moa26 25 moa25 23 moa23 22 moa22 21 moa21 20 moa20 19 moa19 16 moa16 18 moa18 17 moa17 15 moa15 14 moa14 13 moa13 12 moa12 11 moa11 8 moa8 10 moa10 9 moa9 7 moa7 6 moa6 5 moa5 4 moa4 3 moa3 0 moa0 2 moa2 1 moa1 bit bit name bit bit name bit bit name bit bit name bit bit name initial value r/w description 31 to 0 moa31 to moa0 ? r/w these bits store the st art address of the programming destination on the user mat. consecutive 128-byte programming is executed star ting from the specified start address of the user mat. therefore, the specified start address of the program ming destination becomes a 128-byte boundary, and moa6 to moa0 are always cleared to 0. section 21 flash memory rev. 1.00 sep. 13, 2007 page 846 of 1102 rej09b0365-0100 (5) flash multipurpose data destination parameter (fmpdr: general register er0 of cpu) fmpdr stores the start address in the area which st ores the data to be programmed in the user mat. when the storage destination for the program data is in flash memory, an error occurs. the error occurrence is indicated by the wd bit in fpfr. 31 mod31 30 mod30 29 mod29 28 mod28 27 mod27 24 mod24 26 mod26 25 mod25 23 mod23 22 mod22 21 mod21 20 mod20 19 mod19 16 mod16 18 mod18 17 mod17 15 mod15 14 mod14 13 mod13 12 mod12 11 mod11 8 mod8 10 mod10 9 mod9 7 mod7 6 mod6 5 mod5 4 mod4 3 mod3 0 mod0 2 mod2 1 mod1 bit bit name bit bit name bit bit name bit bit name bit bit name initial value r/w description 31 to 0 mod31 to mod0 ? r/w these bits store the st art address of the area which stores the program data for the user mat. consecutive 128-byte data is programmed to the user mat starting from the specified start address. section 21 flash memory rev. 1.00 sep. 13, 2007 page 847 of 1102 rej09b0365-0100 (6) flash erase block select parameter (febs: general register er0 of cpu) ? h8sx/1642 febs specifies the erase block number. settable values range from 0 to 11 (h'0000 to h'000b). a value of 0 corresponds to block eb0 and a value of 11 corresponds to block eb11. an error occurs when a value over the range (from 0 to 15) is set. ? h8sx/1644 febs specifies the erase block number. settable values range from 0 to 15 (h'0000 to h'000f). a value of 0 corresponds to block eb0 and a value of 15 corresponds to block eb15. an error occurs when a value over the range (from 0 to 15) is set. ? h8sx/1648 febs specifies the erase block number. settable values range from 0 to 23 (h'0000 to h'0017). a value of 0 corresponds to block eb0 and a value of 23 corresponds to block eb23. an error occurs when a value over the range (from 0 to 23) is set. bit bit name initial value r/w bit bit name initial value r/w bit bit name initial value r/w 7 ? r/w 6 ? r/w 5 ? r/w 4 ? r/w 3 ? r/w 0 ? r/w 2 ? r/w 1 ? r/w bit bit name initial value r/w 15 ? r/w 14 ? r/w 13 ? r/w 12 ? r/w 11 ? r/w 8 ? r/w 10 ? r/w 9 ? r/w 23 ? r/w 22 ? r/w 21 ? r/w 20 ? r/w 19 ? r/w 16 ? r/w 18 ? r/w 17 ? r/w 31 ? r/w 30 ? r/w 29 ? r/w 28 ? r/w 27 ? r/w 24 ? r/w 26 ? r/w 25 ? r/w section 21 flash memory rev. 1.00 sep. 13, 2007 page 848 of 1102 rej09b0365-0100 21.7.3 ram emulation register (ramer) ramer specifies the user mat area overlaid w ith part of the on-chip ram (h'ffa000 to h'ffafff) when performing emulation of programming the user mat. ramer should be set in user mode or user program mode. to ensure dependable emulation, the memory mat to be emulated must not be accessed immediately after changing the ramer contents. when accessed at such a timing, correct operation is not guaranteed. 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w bit bit name initial value r/w bit bit name initial value r/w description 7 to 4 ? 0 r reserved these are read-only bits and cannot be modified. 3 rams 0 r/w ram select selects the function which emulates the flash memory using the on-chip ram. 0: disables ram emulation function 1: enables ram emulation function (all blocks of the user mat are protected against programming and erasing) 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area select these bits select the user mat area overlaid with the on-chip ram when rams = 1. the following areas correspond to the 4-kbyte erase blocks. 000: h'000000 to h'000fff (eb0) 001: h'001000 to h'001fff (eb1) 010: h'002000 to h'002fff (eb2) 011: h'003000 to h'003fff (eb3) 100: h'004000 to h'004fff (eb4) 101: h'005000 to h'005fff (eb5) 110: h'006000 to h'006fff (eb6) 111: h'007000 to h'007fff (eb7) section 21 flash memory rev. 1.00 sep. 13, 2007 page 849 of 1102 rej09b0365-0100 21.8 on-board programming mode when the emle pin is set to low level, the mode pins (md0, md1, and md2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. on-board programming mode has three operating modes: boot mode, user boot mode, and user program mode. table 21.5 shows the pin setting for each operating mode. for details on th e state transition of each operating mode for flash memory, see figure 21.2. table 21.5 on-board prog ramming mode setting mode setting emle md2 md1 md0 user boot mode 0 0 0 1 boot mode 0 0 1 0 user program mode 0 1 1 0 0 1 1 1 21.8.1 boot mode boot mode executes programming/erasure of the user mat or user boot mat by means of the control command and program data transmitted from the externally connected host via the on-chip sci_4. in boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. the serial communications mode is set to asynchronous mode. the system configuration in boot mode is shown in figure 21.6. interrupts are ignored in boot mode. configure the user system so that interrupts do not occur. rxd4 t xd4 software for analyzing control commands (on-chip) flash memory on-chip ram sci_4 this lsi host programming tool and program data control command, program data response figure 21.6 system configuration in boot mode section 21 flash memory rev. 1.00 sep. 13, 2007 page 850 of 1102 rej09b0365-0100 (1) serial interfa ce setting by host the sci_4 is set to asynchronous mode, and the seri al transmit/receive format is set to 8-bit data, one stop bit, and no parity. when a transition to boot mode is made, the boot program embedded in this lsi is initiated. when the boot program is initiated, this lsi m easures the low period of asynchronous serial communication data (h'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the sci_4 to match that of the host. when bit rate adjustment is completed, this lsi transmits 1 byte of h'00 to the host as the bit adjustment end sign. when the host receives this bit adjustment en d sign normally, it transmits 1 byte of h'55 to this lsi. when reception is not executed normally, initiate boot mode again. the bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of th is lsi. therefore, the tr ansfer bit rate of the host and the system clock frequency of this lsi must be as shown in table 21.6. d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit measure low period (9 bits) (data is h'00) high period of at least 1 bit figure 21.7 automatic-bit- rate adjustment operation table 21.6 system clock frequency for automatic-bit-rate adjustment bit rate of host system clock frequency of this lsi 9,600 bps 8 to 18 mhz 19,200 bps 8 to 18 mhz section 21 flash memory rev. 1.00 sep. 13, 2007 page 851 of 1102 rej09b0365-0100 (2) state transition diagram the state transition after boot mode is initiated is shown in figure 21.8. wait for inquiry setting command wait for programming/erasing command bit rate adjustment processing of read/check command boot mode initiation (reset by boot mode) h'00, ..., h'00 reception h'00 transmission (adjustment completed) (bit rate adjustment) processing of inquiry setting command all user mat and user boot mat erasure wait for program data wait for erase-block data read/check command reception command response (erasure selection command reception) (program data transmission) (erasure selection command reception) (programming completion) (erase-block specification) (erasure completion) inquiry command reception h'55 rece ption inquiry command response 1. 2. 3. 4. figure 21.8 boot mode state transition diagram section 21 flash memory rev. 1.00 sep. 13, 2007 page 852 of 1102 rej09b0365-0100 1. after boot mode is initiated, the bit rate of the sci_4 is adjusted with that of the host. 2. inquiry information about the size, configuration, start address, and support status of the user mat is transmitted to the host. 3. after inquiries have finished, all user ma t and user boot mat are automatically erased. 4. when the program preparation notice is receiv ed, the state of waiting for program data is entered. the start address of the programming destination and program data must be transmitted after the programming command is tr ansmitted. when programming is finished, the start address of the programming destinati on must be set to h'ffffffff and transmitted. then the state of waiting for program data is returned to the state of waiting for programming/erasing command. when the erasure preparation notice is received, the state of waiting for erase block data is entered. the erase block number must be transmitted after the erasing command is transmitted. when the erasure is finished, th e erase block number must be set to h'ff and transmitted. then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. erasure must be executed when the specified block is programmed without a reset start after programming is executed in boot mode. when programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/ erasing command or another command. thus, in this case, the erasing operation is not required. the commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user mat/user boot mat and acquisition of current status information. memory read of the user mat/user boot mat can only read the data programmed after all user mat/user boot mat has automatically been erased. no other data can be read. section 21 flash memory rev. 1.00 sep. 13, 2007 page 853 of 1102 rej09b0365-0100 21.8.2 user program mode programming/erasure of the user mat is executed by downloading an on-chip program. the user boot mat cannot be programmed/erased in user program mode. the programming/erasing flow is shown in figure 21.9. since high voltage is applied to the internal flash memory during programming/erasure, a transition to the reset state or hardware standby mode must not be made during programming/erasure. a transition to the reset state or hardware standby mode during programming/erasure may damage the flash memory. if a reset is input, the reset must be released after the reset input period (period of res = 0) of at least 100 s. when programming, program data is prepared programming/erasing procedure program is transferred to the on-chip ram and executed programming/erasing start programming/erasing end exit ram emulation mode beforehand. download is not allowed in emulation mode. when the program data is adjusted in emulation mode, select the download destination specified by ftdar carefully. make sure that the download area does not overlap the emulation area. programming/erasing is executed only in the on-chip ram. after programming/erasing is finished, protect the flash memory by the hardware protection. 1. 2. 3. 4. figure 21.9 programming/erasing flow section 21 flash memory rev. 1.00 sep. 13, 2007 page 854 of 1102 rej09b0365-0100 (1) on-chip ram address map when programming/erasure is executed parts of the procedure program that is made by the user, like download request, programming/erasure procedure, and decision of the result, must be executed in the on-chip ram. since the on-chip program to be downloaded is embedded in the on-chip ram, make sure the on- chip program and procedure program do not overlap. figure 21.10 shows the area of the on-chip program to be downloaded. h'ffbfff programming/erasing program entry system use area (15 bytes) dpfr (return value: 1 byte) ftdar setting ftdar setting + 32 bytes ftdar setting + 16 bytes initialization program entry initialization + programming program or initialization + erasing program ram emulation area or area that can be used by user area that can be used by user area to be downloaded (size: 4 kbytes) unusable area during programming/erasing ftdar setting + 4 kbytes figure 21.10 ram map when pr ogramming/erasure is executed section 21 flash memory rev. 1.00 sep. 13, 2007 page 855 of 1102 rej09b0365-0100 (2) programming procedure in user program mode the procedures for download of the on-chip program, initialization, and programming are shown in figure 21.11. select on-chip program to be downloaded and specify download destination by ftdar set fkey to h'a5 set sco to 1 after initializing vbr and execute download dpfr = 0? yes no download error processing set the fpefeq parameter yes end programming procedure program fpfr = 0? no disable interrupts and bus master operation other than cpu clear fkey to 0 programming jsr ftdar setting + 16 yes fpfr = 0? no clear fkey and programming error processing yes required data programming is completed? no set fkey to h'5a clear fkey to 0 1. 2. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 3. download initialization programming initialization jsr ftdar setting + 32 initialization error processing set parameters to er1 and er0 (fmpar and fmpdr) 1 1 start programming procedure program figure 21.11 programming pr ocedure in user program mode section 21 flash memory rev. 1.00 sep. 13, 2007 page 856 of 1102 rej09b0365-0100 the procedure program must be executed in an area other than the flash memory to be programmed. setting the sco bit in fccs to 1 to request download must be executed in the on- chip ram. the area that can be executed in the steps of the procedure program (on-chip ram, user mat, and external space) is shown in section 21.8.4, on-chip program and storable area for program data. the following description assumes that the area to be programmed on the user mat is erased and that program data is prepared in the consecutive area. the program data for one programming operation is always 128 bytes. when the program data exceeds 128 bytes, the start addres s of the programming destinati on and program data parameters are updated in 128-byte units and programming is repeated. when the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. if the invalid data to be added is h'ff, the program processing time can be shortened. 1. select the on-chip program to be downloaded and the download destin ation. when the ppvs bit in fpcs is set to 1, the programming program is selected. several programming/erasing programs cannot be selected at one time. if seve ral programs are selected , a download error is returned to the ss bit in the dpfr parameter. the on-chip ram start address of the download destination is specified by ftdar. 2. write h'a5 in fkey. if h'a5 is not written to fkey, the sco bit in fccs cannot be set to 1 to request download of the on-chip program. 3. after initializing vbr to h'00000000, set the sco bit to 1 to execute download. to set the sco bit to 1, all of the following conditions must be satisfied. ? ram emulation mode has been canceled. ? h'a5 is written to fkey. ? setting the sco bit is executed in the on-chip ram. when the sco bit is set to 1, download is started automatically. since the sco bit is cleared to 0 when the procedure program is resumed, the sco bit cannot be confirmed to be 1 in the procedure program. the download result can be confirmed by the return value of the dpfr parameter. to prevent incorrect decision, before setting the sco bit to 1, set one byte of the on-chip ram start address specified by ftdar, which becomes the dpfr parameter, to a value other than the return value (e.g. h'ff). since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the vbr contents to h'00000000. dummy read of fccs must be performed twice immediately after the sco bit is set to 1. ? the user-mat space is switched to the on-chip program storage area. ? after the program to be downloaded and th e on-chip ram start ad dress specified by ftdar are checked, they are transferred to the on-chip ram. ? fpcs, fecs, and the sco bit in fccs are cleared to 0. section 21 flash memory rev. 1.00 sep. 13, 2007 page 857 of 1102 rej09b0365-0100 ? the return value is set in the dpfr parameter. ? after the on-chip program storage area is retu rned to the user-mat space, the procedure program is resumed. after that, vbr can be set again. ? the values of general registers of the cpu are held. ? during download, no interrupts can be accepted. however, since the in terrupt requests are held, when the procedure program is re sumed, the interrup ts are requested. ? to hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. ? allocate a stack area of 128 by tes at the maximum in the on-chip ram before setting the sco bit to 1. ? if access to the flash memory is requested by the dmac or dtc during download, the operation cannot be guaranteed. make sure th at an access request by the dmac or dtc is not generated. 4. fkey is cleared to h'00 for protection. 5. the download result must be confirmed by the value of the dpfr parameter. check the value of the dpfr parameter (one byte of start address of the download destination specified by ftdar). if the value of the dpfr parameter is h'00, download has been performed normally. if the value is not h'00, the source that caused download to fail can be investigated by the description below. ? if the value of the dpfr parameter is the same as that before downloading, the setting of the start address of the download destination in ftdar may be abnormal. in this case, confirm the setting of the tder bit in ftdar. ? if the value of the dpfr parameter is different from that before down loading, check the ss bit or fk bit in the dpfr parameter to confirm the download program selection and fkey setting, respectively. 6. the operating frequency of the cpu is set in the fpefeq parameter for initialization. the settable operating frequency of the fpefeq parameter ranges from 8 to 35 mhz. when the frequency is set otherwise, an error is return ed to the fpfr parameter of the initialization program and initialization is not performed. for details on setting the frequency, see section 21.7.2 (3), flash program/erase frequency parameter (fpefeq: general register er0 of cpu). section 21 flash memory rev. 1.00 sep. 13, 2007 page 858 of 1102 rej09b0365-0100 7. initialization is executed. the initialization program is downloaded together with the programming program to the on-chip ram. the entry point of the initialization program is at the address which is 32 bytes after #dltop (start address of the download destination specified by ftdar). call the subroutine to execute initialization by using the following steps. mov.l #dltop+32,er2 ; set entry address to er2 jsr @er2 ; call initialization routine nop ? the general registers other than er0 and er1 are held in the initialization program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the initializatio n program, a stack area of 128 bytes at the maximum must be allocated in ram. ? interrupts can be accepted during execution of the initialization program. make sure the program storage area and stack area in the on-chip ram and register values are not overwritten. 8. the return value in the initialization pr ogram, the fpfr parameter is determined. 9. all interrupts and the use of a bus master other than the cpu are disabled during programming/erasure. the sp ecified voltage is applied for the specified time when programming or erasing. if interrupts occur or the bus mastership is moved to other than the cpu during programming/erasure, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. therefore, interrupts are disabled by setting bit 7 (i bit) in the condition code register (ccr) to b'1 in interrupt control mode 0 and by setting bits 2 to 0 (i2 to i0 bits) in the extend register (exr) to b'111 in interrupt control mode 2. accordingly, interrupts other than nmi are held and not executed. conf igure the user system so that nmi interrupts do not occur. the interr upts that are held must be executed after all programming completes. when the bus mastership is moved to other than the cpu, such as to the dmac or dtc, the error protection state is entered. therefore, make sure the dmac does not acquire the bus. 10. fkey must be set to h'5a and the user mat must be prepared for programming. 11. the parameters required for programming are set. the start address of the programming destination on the user mat (fmpar parameter) is set in general register er1. the start address of the program data storage area (fmpdr parameter) is set in general register er0. ? example of fmpar parameter setting: when an address other than one in the user mat area is specified for the star t address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the fpfr parameter. since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be h'00 or h'80 to be aligned with the 128-byte boundary. section 21 flash memory rev. 1.00 sep. 13, 2007 page 859 of 1102 rej09b0365-0100 ? example of fmpdr parameter setting: when the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is return ed to the fpfr parameter. in this case, the program data must be transferred to the on-chip ram and then programming must be executed. 12. programming is executed. the entry point of the programming program is at the address which is 16 bytes after #dltop (start address of the download destination specified by ftdar). call the subroutine to execute programming by using the following steps. mov.l #dltop+16,er2 ; set entry address to er2 jsr @er2 ; call programming routine nop ? the general registers other than er0 and er1 are held in the programming program. ? r0l is a return value of the fpfr parameter. ? since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in ram. 13. the return value in the programming program, the fpfr parameter is determined. 14. determine whether programming of the necessary data has finished. if more than 128 bytes of data are to be programmed, update the fmpar and fmpdr parameters in 128-byte units, and repeat steps 11 to 14. increment the programming destination address by 128 bytes and update the programming data pointer correctly. if an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. after programming finishes, clear fkey and specify software protection. if this lsi is restarted by a reset immediately after programming has finished, secure the reset input period (period of res = 0) of at least 100 s. section 21 flash memory rev. 1.00 sep. 13, 2007 page 860 of 1102 rej09b0365-0100 (3) erasing procedure in user program mode the procedures for download of the on-chip program, initialization, and erasing are shown in figure 21.12. set fkey to h'a5 set sco to 1 after initializing vbr and execute download dpfr = 0? yes no download error processing set the fpefeq parameter yes end erasing procedure program fpfr = 0 ? no initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set febs parameter yes fpfr = 0? no clear fkey and erasing error processing yes required block erasing is completed? no set fkey to h'5a clear fkey to 0 1. 2. 3. 4. 5. 6. download initialization erasing initialization jsr ftdar setting + 32 erasing jsr ftdar setting + 16 select on-chip program to be downloaded and specify download destination by ftdar start erasing procedure program 1 1 figure 21.12 erasing proce dure in user program mode section 21 flash memory rev. 1.00 sep. 13, 2007 page 861 of 1102 rej09b0365-0100 the procedure program must be executed in an area other than the user mat to be erased. setting the sco bit in fccs to 1 to request download must be executed in the on-chip ram. the area that can be executed in the steps of the procedur e program (on-chip ram, user mat, and external space) is shown in section 21.8 .4, on-chip program and storable area for program data. for the downloaded on-chip program area, see figure 21.10. one erasure processing erases one block. for details on block divisions, refer to figure 21.4. to erase two or more blocks, update the erase bloc k number and repeat the erasing processing for each block. 1. select the on-chip program to be downloaded and the download destination. when the ppvs bit in fpcs is set to 1, the programming program is selected. several programming/erasing programs cannot be selected at one time. if seve ral programs are selected , a download error is returned to the ss bit in the dpfr parameter. the on-chip ram start address of the download destination is specified by ftdar. for the procedures to be carried out after setting fkey, see section 21.8.2 (2), programming procedure in user program mode. 2. set the febs parameter necessary for erasur e. set the erase block number (febs parameter) of the user mat in general register er0. if a value other than an erase block number of the user mat is set, no block is erased even thou gh the erasing program is executed, and an error is returned to the fpfr parameter. 3. erasure is executed. si milar to as in programming, the entry point of the erasing program is at the address which is 16 bytes after #dltop (start address of the download destination specified by ftdar). call the subroutine to ex ecute erasure by using the following steps. mov.l #dltop+16, er2 ; set entry address to er2 jsr @er2 ; call erasing routine nop ? the general registers other than er0 and er1 are held in the erasing program. r0l is a return value of the fpfr parameter. since the stack area is used in the erasin g program, a stack area of 128 bytes at the maximum must be allocated in ram. 4. the return value in the erasing prog ram, the fpfr parameter is determined. 5. determine whether erasure of the necessary blocks has finished. if more than one block is to be erased, update the febs parameter and repeat steps 2 to 5. 6. after erasure completes, clear fkey and specify software protection. if this lsi is restarted by a reset immediately after erasure has finished, secure the reset input period (period of res = 0) of at least 100 s. section 21 flash memory rev. 1.00 sep. 13, 2007 page 862 of 1102 rej09b0365-0100 (4) procedure of erasing, programming, and ram emulation in user program mode by changing the on-chip ram st art address of the download des tination in ftdar, the erasing program and programming program can be downloaded to separate on-chip ram areas. figure 21.13 shows a repeating procedure of erasing, programming, and ram emulation. yes no erasing program download programming program download emulation/erasing/programming start procedure program initialize erasing program set ftdar to h'02 (specify download destination h'ffb000) download programming program initialize programming program end procedure program erase relevant block (execute erasing program) set fmpdr to h'ffa000 and program relevant block (execute programming program) confirm operation end ? set ftdar to h'00 (specify download destination to h'ff9000) download erasing program exit emulation mode make a transition to ram emulation mode and tuning parameters in on-chip ram 1 1 figure 21.13 repeating procedure of erasing, programming, and ram emulation in user program mode section 21 flash memory rev. 1.00 sep. 13, 2007 page 863 of 1102 rej09b0365-0100 in figure 21.13, since ram emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip ram area (h'ffa000 to h'ff afff). download and initialization are performed only once at the beginning. note the following when executing the procedure program. ? be careful not to overwrite data in the on-chip ram with overlay settings. in addition to the programming program area, erasing program ar ea, and ram emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip ram. do not make settings that will overwrite data in these areas. ? be sure to initialize both the programming prog ram and erasing program. when the fpefeq parameter is initialized, also initialize both the erasing program and programming program. initialization must be executed for both entry addresses: #dltop (start address of download destination for erasing program) + 32 bytes, and #dltop (start address of download destination for programming program) + 32 bytes. 21.8.3 user boot mode branching to a programming/erasing program prepared by the user enables user boot mode which is a user-arbitrary boot mode to be used. only the user mat can be programmed/erased in user boot mode. programming/erasure of the user boot mat is only enabled in boot mode or programmer mode. (1) initiation in user boot mode when the reset start is executed with the mode pins set to user boot mode, the built-in check routine runs and checks the user mat and user boot mat st ates. while the check routine is running, nmi and all other interrupts cannot be accepted. next, processi ng starts from the execution start address of the reset vector in the user boot ma t. at this point, the user boot mat is selected (fmats = h'aa) as the execution memory mat. section 21 flash memory rev. 1.00 sep. 13, 2007 page 864 of 1102 rej09b0365-0100 (2) user mat programming in user boot mode figure 21.14 shows the procedure for programming the user mat in user boot mode. the difference between the programming procedures in user program mode and user boot mode is the memory mat switching as shown in figure 21.14. for programming the user mat in user boot mode, additional processing made by setting fmats is required: switching from the user boot mat to the user mat, and switching back to the user boot mat after programming completes. set fkey to h'a5 dpfr = 0 ? yes no download error processing set the fpefeq and fubra parameters initialization jsr ftdar setting + 32 yes end programming procedure program fpfr = 0 ? no initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set parameter to er0 and er1 (fmpar and fmpdr) programming jsr ftdar setting + 16 yes fpfr = 0 ? no yes required data programming is completed? no set fkey to h'a5 clear fkey to 0 download initialization programming mat switchover mat switchover set fmats to value other than h'aa to select user mat set sco to 1 after initializing vbr and execute download clear fkey and programming error processing set fmats to h'aa to select user boot mat user-boot-mat selection state user-mat selection state user-boot-mat selection state note: the mat must be switched by fmats to perform the programming error processing in the user boot mat. start programming procedure program select on-chip program to be downloaded and specify download destination by ftdar 1 1 figure 21.14 procedu re for programming user ma t in user boot mode section 21 flash memory rev. 1.00 sep. 13, 2007 page 865 of 1102 rej09b0365-0100 in user boot mode, though the user boot mat can be seen in the flash memory space, the user mat is hidden in the background. therefore, the user mat and user boot mat are switched while the user mat is being pr ogrammed. because the user boot mat is hidden while the user mat is being programmed, the procedure program mu st be executed in an area other than flash memory. after programming completes, switch the memory mats again to return to the first state. memory mat switching is enabled by setting fmats. however note that access to a memory mat is not allowed until memory mat switching is completed. during memory mat switching, the lsi is in an unstable state, e.g. if an interrupt occurs, from which memory mat the interrupt vector is read is undetermined. perform me mory mat switching in accordance with the description in section 21.11, switching between user mat and user boot mat. except for memory mat switching, the programming procedure is the same as that in user program mode. the area that can be executed in the steps of the procedure program (on-chip ram, user mat, and external space) is shown in section 21.8.4, on-chip progra m and storable area for program data. section 21 flash memory rev. 1.00 sep. 13, 2007 page 866 of 1102 rej09b0365-0100 (3) user mat erasing in user boot mode figure 21.15 shows the procedure for erasing the user mat in user boot mode. the difference between the erasing procedures in user program mode and user boot mode is the memory mat switching as shown in figure 21.15. for erasing the user mat in user boot mode, additional processing made by setting fmats is required: switching from the user boot mat to the user mat, and sw itching back to the user boot mat after erasing completes. yes no start erasing procedure program set fkey to h'a5 yes no download error processing set the fpefeq and fubra parameters end erasing procedure program fpfr = 0 ? initialization error processing disable interrupts and bus master operation other than cpu clear fkey to 0 set febs parameter yes no clear fkey and erasing error processing yes required block erasing is completed? no set fkey to h'a5 clear fkey to 0 download initialization erasing set fmats to value other than h'aa to select user mat set sco to 1 after initializing vbr and execute download set fmats to h'aa to select user boot mat user-boot-mat selection state user-mat selection state user-boot-mat selection state note: the mat must be switched by fmats to perform the erasing error processing in the user boot mat. mat switchover mat switchover dpfr = 0 ? initialization jsr ftdar setting + 32 erasing jsr ftdar setting + 16 fpfr = 0 ? select on-chip program to be downloaded and specify download destination by ftdar 1 1 figure 21.15 procedure for eras ing user mat in user boot mode section 21 flash memory rev. 1.00 sep. 13, 2007 page 867 of 1102 rej09b0365-0100 memory mat switching is enabled by setting fmats. however note that access to a memory mat is not allowed until memory mat switching is completed. during memory mat switching, the lsi is in an unstable state, e.g. if an interrupt occurs, from which memory mat the interrupt vector is read is undetermined. perform me mory mat switching in accordance with the description in section 21.11, switching between user mat and user boot mat. except for memory mat switching, the erasing proc edure is the same as that in user program mode. the area that can be executed in the steps of the procedure program (on-chip ram, user mat, and external space) is shown in section 21.8.4, on-chip progra m and storable area for program data. 21.8.4 on-chip program and storable area for program data in the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip ram. however, they can be executed from part of the flash memory which is not to be programmed or erased as lo ng as the following conditions are satisfied. ? the on-chip program is downloaded to and executed in the on-chip ram specified by ftdar. therefore, this on-chip ra m area is not available for use. ? since the on-chip program uses a stack area, allocate 128 byte s at the maximum as a stack area. ? download requested by setting the sco bit in fccs to 1 should be executed from the on-chip ram because it will require switching of the memory mats. ? in an operating mode in which the external addr ess space is not accessible, such as single-chip mode, the required procedure programs, nmi handling vector table, and nmi handling routine should be transferred to the on-chip ram before programming/erasure starts (download result is determined). ? the flash memory is not acce ssible during programming/erasu re. programming/erasure is executed by the program downloaded to the on -chip ram. therefore, the procedure program that initiates operation, the nmi handling vector table, and the nmi handling routine should be stored in the on-chip ram other than the flash memory. ? after programming/erasure starts, access to the fl ash memory should be inhibited until fkey is cleared. the reset input state (period of res = 0) must be set to at least 100 s when the operating mode is changed and the reset start ex ecuted on completion of programming/erasure. transitions to the reset state are inhibited dur ing programming/erasure. when the reset signal is input, a reset input state (period of res = 0) of at least 100 s is needed before the reset signal is released. section 21 flash memory rev. 1.00 sep. 13, 2007 page 868 of 1102 rej09b0365-0100 ? switching of the memory mats by fmats should be needed when programming/erasure of the user mat is operated in user boot mode . the program which swit ches the memory mats should be executed from the on-chip ram. for details, see section 21.11, switching between user mat and user boot mat. make sure you know which memory mat is currently selected when switching them. ? when the program data storage ar ea is within the flash memory ar ea, an error will occur even when the data stored is normal program data. therefore, the data should be transferred to the on-chip ram to place the address that the fmpd r parameter indicates in an area other than the flash memory. in consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory mats, as shown in tables 21.7 to 21.11. table 21.7 executable memory mat operating mode processing contents user pr ogram mode user boot mode * programming see table 21. 8 see table 21.10 erasing see table 21. 9 see table 21.11 note: * programming/erasure is possible to the user mat. section 21 flash memory rev. 1.00 sep. 13, 2007 page 869 of 1102 rej09b0365-0100 table 21.8 usable area for pr ogramming in user program mode storable/executable area selected mat item on-chip ram user mat user mat embedded program storage mat storage area for program data o * ? ? operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initiali zation error o o o nmi handling routine o o operation for disabling interrupts o o o operation for writing h'5a to fkey o o o operation for setting programming parameter o o execution of programming o o decision of programming result o o operation for programming error o o operation for clearing fkey o o note: * transferring the program data to the on-chip ram beforehand enables this area to be used. section 21 flash memory rev. 1.00 sep. 13, 2007 page 870 of 1102 rej09b0365-0100 table 21.9 usable area for erasure in user program mode storable/executable area selected mat item on-chip ram user mat user mat embedded program storage mat operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initiali zation error o o o nmi handling routine o o operation for disabling interrupts o o o operation for writing h'5a to fkey o o o operation for setting erasure parameter o o execution of erasure o o decision of erasure result o o operation for erasure error o o operation for clearing fkey o o section 21 flash memory rev. 1.00 sep. 13, 2007 page 871 of 1102 rej09b0365-0100 table 21.10 usable area for pr ogramming in user boot mode storable/executable area selected mat item on-chip ram user boot mat user mat user boot mat embedded program storage mat storage area for program data o * 1 ? ? ? operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initializa tion error o o o nmi handling routine o o operation for disabling interrupts o o o switching memory mats by fmats o o operation for writing h'5a to fkey o o operation for setting programming parameter o o execution of programming o o decision of programming result o o operation for programming error o * 2 o operation for clearing fkey o o switching memory mats by fmats o o notes: 1. transferring the program data to the on-chip ram beforehand enables this area to be used. 2. switching memory mats by fmats by a program in the on-chip ram enables this area to be used. section 21 flash memory rev. 1.00 sep. 13, 2007 page 872 of 1102 rej09b0365-0100 table 21.11 usable area for erasure in user boot mode storable/executable area selected mat item on-chip ram user boot mat user mat user boot mat embedded program storage mat operation for selecting on-chip program to be downloaded o o o operation for writing h'a5 to fkey o o o execution of writing 1 to sco bit in fccs (download) o o operation for clearing fkey o o o decision of download result o o o operation for download error o o o operation for setting initialization parameter o o o execution of initialization o o decision of initialization result o o o operation for initializa tion error o o o nmi handling routine o o operation for disabling interrupts o o o switching memory mats by fmats o o operation for writing h'5a to fkey o o operation for setting erasure parameter o o execution of erasure o o decision of erasure result o o operation for erasure error o * o operation for clearing fkey o o switching memory mats by fmats o o note: switching memory mats by fmats by a pr ogram in the on-chip ram enables this area to be used. section 21 flash memory rev. 1.00 sep. 13, 2007 page 873 of 1102 rej09b0365-0100 21.9 protection there are three types of protection against the flash memory programming/erasure: hardware protection, software protection, and error protection. 21.9.1 hardware protection programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. in this state, download of an on-chip program and initialization are possible. however, programming or erasure of the user mat cannot be performed even if the programming/erasing program is initiated, and the error in programming /erasure is indicated by the fpfr parameter. table 21.12 hardware protection function to be protected item description download programming/ erasing reset protection ? the programming/erasing interface registers are initialized in the reset state (including a reset by the wdt) and the programming/erasing protection state is entered. ? the reset state will not be entered by a reset using the res pin unless the res pin is held low until oscillation has settled after a power is initially supplied. in the case of a reset during operation, hold the res pin low for the res pulse width given in the ac characteristics. if a reset is input during programming or erasure, data in the flash memory is not guaranteed. in this case, execute erasure and then execute programming again. o o section 21 flash memory rev. 1.00 sep. 13, 2007 page 874 of 1102 rej09b0365-0100 21.9.2 software protection the software protection protects the flash memory against prog ramming/erasure by disabling download of the programming/erasing program, using the key code, and by the ramer setting. table 21.13 software protection function to be protected item description download programming/ erasing protection by sco bit the programming/erasing protection state is entered when the sco bit in fccs is cleared to 0 to disable download of the programming/erasing programs. o o protection by fkey the programming/erasing protection state is entered because download and programming/erasure are disabled unless the required key code is written in fkey. o o emulation protection the programming/erasing protection state is entered when the rams bit in the ram emulation register (ramer) is set to 1. o o 21.9.3 error protection error protection is a mechanism for aborting programming or erasure when a cpu runaway occurs or operations not according to the progra mming/erasing procedures are detected during programming/erasure of the flash memory. aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. if an error occurs during programming/erasure of the flash memory, the fler bit in fccs is set to 1 and the error protection state is entered. ? when an interrupt request, such as nm i, occurs during programming/erasure. ? when the flash memory is read from during programming/erasure (including a vector read or an instruction fetch). ? when a sleep instruction is executed (including software-standby mode) during programming/erasure. ? when a bus master other than the cpu, such as the dmac and dtc, obtains bus mastership during programming/erasure. section 21 flash memory rev. 1.00 sep. 13, 2007 page 875 of 1102 rej09b0365-0100 error protection is canceled by a re set. note that the reset should be released after the reset input period of at least 100 s has passed. since high voltages are applied during programming/erasure of the flash memory, some voltage may remain af ter the error protection state has been entered. for this reason, it is necessary to reduce the risk of damaging th e flash memory by extending the reset input period so that the charge is released. the state-transition diagram in figure 21.16 shows transitions to and from the error protection state. reset (hardware protection) programming/erasing mode error-protection mode error-protection mode (software standby) read disabled programming/erasing enabled fler = 0 read disabled programming/erasing disabled fler = 0 read enabled programming/erasing disabled fler = 1 read disabled programming/erasing disabled fler = 1 res = 0 error occurrence error occurred (software standby) res = 0 software standby mode cancel software standby mode res = 0 programming/erasing interface register is in its initial state. programming/erasing interface register is in its initial state. figure 21.16 transitions to error protection state section 21 flash memory rev. 1.00 sep. 13, 2007 page 876 of 1102 rej09b0365-0100 21.10 flash memory emulation using ram for realtime emulation of the data written to the flash memory using the on-chip ram, the on- chip ram area can be overlaid with several flash memory blocks (user mat) using the ram emulation register (ramer). the overlaid area can be accessed from both the user mat ar ea specified by ramer and the overlaid ram area. the emulation can be performed in user mode and user program mode. figure 21.17 shows an example of emulatin g realtime programming of the user mat. emulation program start set ramer write tuning data to overlaid ram area execute application program tuning ok? cancel setting in ramer program emulation block in user mat emulation program end ye s no figure 21.17 ram emulation flow section 21 flash memory rev. 1.00 sep. 13, 2007 page 877 of 1102 rej09b0365-0100 figure 21.18 shows an example of overlaying flash memory block area eb0. this area can be accessed via both the on-chip ram and flash memory area. flash memory user mat eb8 to eb15 * 1 on-chip ram h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 notes: 1. eb8 to eb11 in the h8sx/1642. eb8 to eb23 in the h8sx/1648. 2. h'03ffff in the h8sx/1642. h'0fffff in the h8sx/1648. h'7ffff * 2 h'ff6000 h'ffa000 h'ffafff h'ffbfff eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 figure 21.18 address map of overlaid ram area (h8sx/1644) the flash memory area that can be emulated is th e one area selected by bits ram2 to ram0 in ramer from among the eight blocks, eb0 to eb7, of the user mat. to overlay a part of the on-chip ram with block eb0 for realtime emulation, set the rams bit in ramer to 1 and bits ram2 to ram0 to b'000. for programming/erasing the user mat, the procedure programs including a download program of the on-chip program must be executed. at this time, the download area should be specified so that the overlaid ram area is not overwritten by downloading the on-chip program. since the area in which the tuned data is stored is overlaid with the download area when ftdar = h'01, the tuned data must be saved in an unused area beforehand. section 21 flash memory rev. 1.00 sep. 13, 2007 page 878 of 1102 rej09b0365-0100 figure 21.19 shows an example of the procedure to program the tuned data in block eb0 of the user mat. flash memory user mat eb8 to eb15 * 1 notes: 1. eb8 to eb11 in the h8sx/1642. eb8 to eb23 in the h8sx/1648. 2. h'03ffff in the h8sx/1642. h'0fffff in the h8sx/1648. download area tuned data area area for programming/ erasing program etc. h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'7ffff * 2 specified by ftdar h'ffa000 h'ffb000 h'ffafff h'ffbfff eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 (1) exit ram emulation mode. (2) transfer user-created programming/erasing procedure program. (3) download the on-chip programming/erasing program to the area specified by ftdar. ftdar setting should avoid the tuned data area. (4) program after erasing, if necessary. figure 21.19 programming tuned data (h8sx/1644) 1. after tuning program data is completed, clear the rams bit in ramer to 0 to cancel the overlaid ram. 2. transfer the user-c reated procedure progra m to the on-chip ram. 3. start the procedure program and download the on-chip program to the on-chip ram. the start address of the download destination should be specified by ftdar so that the tuned data area does not overlay the download area. 4. when block eb0 of the user mat has not been erased, the programming program must be downloaded after block eb0 is erased. specify the tuned data saved in the fmpar and fmpdr parameters and then execute programming. note: setting the rams bit to 1 makes all the blocks of the user mat enter the programming/erasing protection state (emulation protection state) regardless of the setting of the ram2 to ram0 bits. under this condition, the on-chip program cannot be downloaded. when data is to be actually programmed and erased, clear the rams bit to 0. section 21 flash memory rev. 1.00 sep. 13, 2007 page 879 of 1102 rej09b0365-0100 21.11 switching between user mat and user boot mat it is possible to switch between the user mat and user boot mat. however, the following procedure is required because the start addresses of these mats are allocated to the same address. switching to the user boot mat disables programming and erasing. programming of the user boot mat should take place in boot mode or programmer mode. 1. memory mat switching by fmats should always be executed from the on-chip ram. 2. when accessing the memory mat immediat ely after switching the memory mats by fmats from the on-chip ram, similarly execute the nop instruction in the on-chip ram for eight times (this prevents access to the flash memory during memory mat switching). 3. if an interrupt request has occurred during memory mat switching, there is no guarantee of which memory mat is accessed. always mask the maskable interrupts before switching memory mats. in addition, configure the system so that nmi interrupts do not occur during memory mat switching. 4. after the memory mats have been switched, take care because the interrupt vector table will also have been switched. if interrupt processing is to be the same before and after memory mat switching, transfer the interrupt processi ng routines to the on-chip ram and specify vbr to place the interrupt vector table in the on-chip ram. 5. the size of the user mat is different from that of the user boot mat. addresses which exceed the size of the 16-kbyte user bo ot mat should not be accessed. if an attempt is made, data is read as an undefined value. section 21 flash memory rev. 1.00 sep. 13, 2007 page 880 of 1102 rej09b0365-0100 21.12 programmer mode along with its on-board programming mode, this lsi also has a programmer mode as a further mode for the writing and erasing of programs and data. in programmer mode, a general-purpose prom programmer that supports the device types shown in table 21.14 can be used to write programs to the on-chip rom without any limitation. table 21.14 device types supported in programmer mode target memory mat product classif ication rom size device type h8sx/1642 256 kbytes fztat256v3a h8sx/1644 512 kbytes fztat512v3a user mat h8sx/1648 1 mbyte fztat1024v3a h8sx/1642 h8sx/1644 user boot mat h8sx/1648 16 kbytes fztatusbt16v3a 21.13 standard serial communications interface specifications for boot mode the boot program initiated in boot mode performs serial communications using the host and on- chip sci_4. the serial co mmunications interface specifi cations are shown below. the boot program has three states. 1. bit-rate-adjustment state in this state, the boot progra m adjusts the bit rate to achiev e serial communications with the host. initiating boot mode enables starting of the boot program and entry to the bit-rate- adjustment state. the program receives the command from the host to adjust the bit rate. after adjusting the bit rate, the program enters the inquiry/selection state. 2. inquiry/selection state in this state, the boot program responds to inquiry commands from the host. the device name, clock mode, and bit rate are selected. after selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. the program transfers the libraries required for erasure to the on- chip ram and erases the user mats and user boot mats before the transition. section 21 flash memory rev. 1.00 sep. 13, 2007 page 881 of 1102 rej09b0365-0100 3. programming/erasing state programming and erasure by the boot program take place in this state. the boot program is made to transfer the programming/erasing programs to the on-chip ram by commands from the host. sum checks and blank checks are executed by sendin g these commands from the host. these boot program states are shown in figure 21.21. transition to programming/erasing programming/erasing wait checking inquiry response erasing programming reset bit-rate-adjustment state operations for erasing user mats and user boot mats operations for inquiry and selection operations for programming operations for checking operations for erasing operations for response inquiry/response wait figure 21.21 boot program states section 21 flash memory rev. 1.00 sep. 13, 2007 page 882 of 1102 rej09b0365-0100 (1) bit-rate-adjustment state the bit rate is calculated by measuring the period of transfer of a low-leve l byte (h'00) from the host. the bit rate can be changed by the command for a new bit rate selection. after the bit rate has been adjusted, the boot program enters the inquiry and selection state. the bit-rate-adjustment sequence is shown in figure 21.22. host boot program h'00 (30 times maximum) h'e6 (boot response) measuring the 1-bit length h'00 (completion of adjustment) h'55 (h'ff (error)) figure 21.22 bit-rate-adjustment sequence (2) communications protocol after adjustment of the bit rate, the protocol fo r serial communications between the host and the boot program is as shown below. 1. one-byte commands and one-byte responses these one-byte commands and one-byte responses consist of the inquiries and the ack for successful completion. 2. n-byte commands or n-byte responses these commands and responses are comprised of n bytes of data. these are selections and responses to inquiries. the program data size is not included under this heading because it is determined in another command. 3. error response the error response is a response to inquiries. it consists of an error response and an error code and comes two bytes. 4. programming of 128 bytes the size is not specified in commands. the size of n is in dicated in response to the programming unit inquiry. section 21 flash memory rev. 1.00 sep. 13, 2007 page 883 of 1102 rej09b0365-0100 5. memory read response this response consists of four bytes of data. command or response size data checksum error response error code command or response error response n-byte command or n-byte response one-byte command or one-byte response address command data (n bytes) checksum 128-byte programming size response data checksum memory read response figure 21.23 communication protocol format ? command (one byte): commands including inquiries, selection, programming, erasing, and checking ? response (one byte): response to an inquiry ? size (one byte): the amount of data for transmission excluding the command, amount of data, and checksum ? checksum (one byte): th e checksum is calculated so that the total of all values from the command byte to the sum byte becomes h'00. ? data (n bytes): detailed data of a command or response ? error response (one byte): error response to a command ? error code (one byte): type of the error ? address (four bytes): address for programming ? data (n bytes): data to be programmed (the size is indicated in the response to the programming unit inquiry.) ? size (four bytes): four-byte response to a memory read section 21 flash memory rev. 1.00 sep. 13, 2007 page 884 of 1102 rej09b0365-0100 (3) inquiry and selection states the boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. table 21.15 lists the inquiry and selection commands. table 21.15 inquiry and selection commands command command name description h'20 supported device inquiry inquiry regarding device codes h'10 device selection sele ction of device code h'21 clock mode inquiry inquiry regarding numbers of clock modes and values of each mode h'11 clock mode selection indication of the selected clock mode h'22 multiplication ratio inquiry i nquiry regarding the number of frequency- multiplied clock types, the number of multiplication ratios, and the values of each multiple h'23 operating clock frequency inquiry i nquiry regarding the maximum and minimum values of the main clock and peripheral clocks h'24 user boot mat information inquiry inquiry regarding the number of user boot mats and the start and last addresses of each mat h'25 user mat information inquiry inquiry regarding the a number of user mats and the start and last addresses of each mat h'26 block for erasing information inquiry inquiry regarding the number of blocks and the start and last addresses of each block h'27 programming unit inquiry inquiry re garding the unit of program data h'3f new bit rate selection selection of new bit rate h'40 transition to programming/erasing state erasing of user mat and user boot mat, and entry to programming/erasing state h'4f boot program status inquiry inquiry into the oper ated status of the boot program section 21 flash memory rev. 1.00 sep. 13, 2007 page 885 of 1102 rej09b0365-0100 the selection commands, which are device selection (h'10), clock mode selection (h'11), and new bit rate selection (h'3f), should be sent from the host in that order. when two or more selection commands are sent at once, the last command will be valid. all of these commands, except for the boot program status inquiry command (h'4f), will be valid until the boot program receives th e programming/erasing transition (h'40). the host can choose the needed commands and make inquiries while th e above commands are being transmitted. h'4f is valid even after the boot program has received h'40. (a) supported device inquiry the boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. command h'20 ? command, h'20, (one byte): inquiry regarding supported devices response h'30 size number of devices number of characters device code product name sum ? response, h'30, (one byte): response to the supported device inquiry ? size (one byte): number of bytes to be tr ansmitted, excluding the command, size, and checksum, that is, the amount of data contribu tes by the number of devices, characters, device codes and product names ? number of devices (one byte): the number of device types supported by the boot program ? number of characters (one byt e): the number of characters in the device codes and boot program's name ? device code (four bytes): ascii code of the supporting product ? product name (n bytes): type name of the boot program in ascii-coded characters ? sum (one byte): checksum the checksum is calculated so that the total number of all values from the command byte to the sum byte becomes h'00. section 21 flash memory rev. 1.00 sep. 13, 2007 page 886 of 1102 rej09b0365-0100 (b) device selection the boot program will set the supported device to the specified device code. the program will return the selected device code in response to the inquiry after this setting has been made. command h'10 size device code sum ? command, h'10, (one byte): device selection ? size (one byte): amount of device-code data this is fixed at 4. ? device code (four bytes): device code (ascii code) returned in response to the supported device inquiry ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): respon se to the device selection command ack will be returned when the device code matches. error response h'90 error ? error response, h'90, (one byte): error response to the device selection command error : (one byte): error code h'11: sum check error h'21: device code error, that is, the device code does not match (c) clock mode inquiry the boot program will return the supported clock modes in response to the clock mode inquiry. command h'21 ? command, h'21, (one byte): inquiry regarding clock mode response h'31 size mode sum ? response, h'31, (one byte): response to the clock-mode inquiry ? size (one byte): amount of data that represents the modes ? mode (one byte): values of the supported clock modes (i.e. h'01 means clock mode 1.) ? sum (one byte): checksum section 21 flash memory rev. 1.00 sep. 13, 2007 page 887 of 1102 rej09b0365-0100 (d) clock mode selection the boot program will set the sp ecified clock mode. the program will return the selected clock- mode information after this setting has been made. the clock-mode selection command should be sent after the device-selection commands. command h'11 size mode sum ? command, h'11, (one byte): selection of clock mode ? size (one byte): amount of data that represents the modes ? mode (one byte): a clock mode returned in reply to the supported clock mode inquiry. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to the clock mode selection command ack will be returned when the clock mode matches. error response h'91 error ? error response, h'91, (one byte) : error response to the clock mode selection command ? error : (one byte): error code h'11: checksum error h'22: clock mode error, that is, the clock mode does not match. even if the clock mode numbers are h'00 and h'01 by a clock mode inquiry, the clock mode must be selected using these respective values. section 21 flash memory rev. 1.00 sep. 13, 2007 page 888 of 1102 rej09b0365-0100 (e) multiplication ratio inquiry the boot program will return the supported multiplication and division ratios. command h'22 ? command, h'22, (one byte): inquiry regarding multiplication ratio response h'32 size number of types of multipli cation number of multiplication ratios multiplica- tion ratio sum ? response, h'32, (one byte): response to the multiplication ratio inquiry ? size (one byte): the amount of data that represen ts the number of types of multiplication, the number of multiplication ratios, and the multiplication ratios ? number of types of multiplication (one byte): the number of types of multiplication to which the device can be set (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be h'02.) ? number of multiplication ratios (one byte): the number of types of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) ? multiplication ratio (one byte) multiplication ratio: the value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be h'04.) division ratio: the inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) the number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types of multiplication. ? sum (one byte): checksum section 21 flash memory rev. 1.00 sep. 13, 2007 page 889 of 1102 rej09b0365-0100 (f) operating clock frequency inquiry the boot program will return the number of operating clock frequencies, and the maximum and minimum values. command h'23 ? command, h'23, (one byte): inquiry regarding operating clock frequencies response h'33 size number of operating clock frequencies minimum value of operating clock frequency maximum value of operating clock frequency sum ? response, h'33, (one byte): response to operating clock frequency inquiry ? size (one byte): the number of bytes that re presents the minimum values, maximum values, and the number of frequencies. ? number of operating clock frequencies (one byte): the number of supported operating clock frequency types (e.g. when there are two operating clock frequen cy types, which are the main and peripheral clocks, the number of types will be h'02.) ? minimum value of operating clock frequency (two bytes): the minimum value of the multiplied or divided clock frequency. the minimum and maximum values of the operating clock frequency represent the values in mhz, valid to the hundredths place of mhz, an d multiplied by 100. (e .g. when the value is 17.00 mhz, it will be 2000, which is h'07d0.) ? maximum value (two bytes): maximum value among the multiplied or divided clock frequencies. there are as many pairs of minimum and maximum values as there are operating clock frequencies. ? sum (one byte): checksum section 21 flash memory rev. 1.00 sep. 13, 2007 page 890 of 1102 rej09b0365-0100 (g) user boot mat information inquiry the boot program will return the number of user boot mats and their addresses. command h'24 ? command, h'24, (one byte): inquiry regarding user boot mat information response h'34 size number of areas area-start address area-last address sum ? response, h'34, (one byte): response to user boot mat information inquiry ? size (one byte): the number of bytes that repr esents the number of areas, area-start addresses, and area-last address ? number of areas (one byte): the number of consecutive user boot mat areas when user boot mat areas are consecutive, the number of areas returned is h'01. ? area-start address (four byte) : start address of the area ? area-last address (four byte) : last address of the area there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (h) user mat information inquiry the boot program will return the number of user mats and their addresses. command h'25 ? command, h'25, (one byte): inquiry regarding user mat information response h'35 size number of areas start address area last address area sum ? response, h'35, (one byte): response to the user mat information inquiry ? size (one byte): the number of bytes that re presents the number of areas, area-start address and area-last address ? number of areas (one byte): the nu mber of consecutive user mat areas when the user mat areas are consecutive, the number of areas is h'01. ? area-start address (four bytes ): start address of the area section 21 flash memory rev. 1.00 sep. 13, 2007 page 891 of 1102 rej09b0365-0100 ? area-last address (four bytes): last address of the area there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (i) erased block information inquiry the boot program will return the number of erased blocks and their addresses. command h'26 ? command, h'26, (two bytes): inquiry regarding erased block information response h'36 size number of blocks block start address block last address sum ? response, h'36, (one byte): response to the number of erased blocks and addresses ? size (three bytes): the number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. ? number of blocks (one byte): the number of erased blocks ? block start address (four bytes): start address of a block ? block last address (four bytes): last address of a block there are as many groups of data representing the start and last addre sses as there are areas. ? sum (one byte): checksum (j) programming unit inquiry the boot program will return the programming unit used to program data. command h'27 ? command, h'27, (one byte): inquiry regarding programming unit response h'37 size programming unit sum ? response, h'37, (one byte): response to programming unit inquiry ? size (one byte): the number of bytes that indicate the programming unit, which is fixed to 2 ? programming unit (two bytes): a unit for programming this is the unit for reception of programming. ? sum (one byte): checksum section 21 flash memory rev. 1.00 sep. 13, 2007 page 892 of 1102 rej09b0365-0100 (k) new bit-rate selection the boot program will set a new bit rate and return the new bit rate. this selection should be sent after sending the clock mode selection command. command h'3f size bit rate input frequency number of types of multiplication multiplication ratio 1 multiplication ratio 2 sum ? command, h'3f, (one byte): selection of new bit rate ? size (one byte): the number of bytes that represents the bit rate, input frequency, number of types of multiplication, and multiplication ratio ? bit rate (two bytes): new bit rate one hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is h'00c0.) ? input frequency (two bytes): frequency of the clock input to the boot program this is valid to the hundredths place and repres ents the value in mhz mu ltiplied by 100. (e.g. when the value is 20.00 mhz, it will be 2000, which is h'07d0.) ? number of types of multiplication (one byte): the number of multiplication to which the device can be set. ? multiplication ratio 1 (one byte) : the value of multiplication or division ratios for the main operating frequency multiplication ratio (one byte): the value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be h'04.) division ratio: the inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) ? multiplication ratio 2 (one byte): the value of multiplication or division ratios for the peripheral frequency multiplication ratio (one byte): the value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be h'04.) (division ratio: the inverse of the division ratio, as a negative number (e.g. when the clock is divided by two, the value of division ratio will be h'fe. h'fe = d'-2) ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to selection of a new bit rate when it is possible to set the bit rate, the response will be ack. section 21 flash memory rev. 1.00 sep. 13, 2007 page 893 of 1102 rej09b0365-0100 error response h'bf error ? error response, h'bf, (one byte): error response to selection of new bit rate ? error: (one byte): error code h'11: sum checking error h'24: bit-rate selection error the rate is not available. h'25: error in input frequency this input frequency is not within the specified range. h'26: multiplication-ratio error the ratio does not match an available ratio. h'27: operating frequency error the frequency is not within the specified range. (4) receive data check the methods for checking of r eceive data are listed below. 1. input frequency the received value of the input fr equency is checked to ensure th at it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. when the value is out of this range, an input-frequency error is generated. 2. multiplication ratio the received value of the multipli cation ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. when the value is out of this range, an input- frequency error is generated. 3. operating frequency error operating frequency is calculated from the r eceived value of the input frequency and the multiplication or division ratio. the input frequency is input to the lsi and the lsi is operated at the operating frequency. the expression is given below. operating frequency = input frequency multiplication ratio, or operating frequency = input frequency division ratio the calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. when it is out of this range, an operating frequency error is generated. section 21 flash memory rev. 1.00 sep. 13, 2007 page 894 of 1102 rej09b0365-0100 4. bit rate to facilitate error checking, the value (n) of clock select (cks) in the serial mode register (smr), and the value (n) in the bit rate regi ster (brr), which are fo und from the peripheral operating clock frequency ( ) and bit rate (b), are used to calcu late the error rate to ensure that it is less than 4%. if the error is more than 4%, a bit rate error is generated. the error is calculated using the following expression: error (%) = {[ ] ? 1} 100 (n + 1) b 64 2 (2 n ? 1) 10 6 when the new bit rate is selectable, the rate will be set in the register after sending ack in response. the host will send an ack with the new bit rate for confirmation and the boot program will response with that rate. confirmation h'06 ? confirmation, h'06, (one byte): confirmation of a new bit rate response h'06 ? response, h'06, (one byte): response to confirmation of a new bit rate the sequence of new bit-rate selection is shown in figure 21.24. host boot program setting a new bit rate h'06 (ack) waiting for one-bit period at the specified bit rate h'06 (ack) with the new bit rate h'06 (ack) with the new bit rate setting a new bit rate setting a new bit rate figure 21.24 new bit- rate selection sequence section 21 flash memory rev. 1.00 sep. 13, 2007 page 895 of 1102 rej09b0365-0100 (5) transition to programming/erasing state the boot program will transfer the erasing program, and erase the user mats and user boot mats in that order. on completion of this erasur e, ack will be returned and will enter the programming/erasing state. the host should select the device code, clock mode, and new bit rate with device selection, clock- mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing st ate. these procedures should be carried out before sending of the programming selection command or program data. command h'40 ? command, h'40, (one byte): transition to programming/erasing state response h'06 ? response, h'06, (one byte): response to transition to programming/erasing state the boot program will send ack when the user mat and user boot mat have been erased by the transferred erasing program. error response h'c0 h'51 ? error response, h'c0, (one byte): error response for user boot mat blank check ? error code, h'51, (one byte): erasing error an error occurred and er asure was not completed. (6) command error a command error will occur when a command is un defined, the order of commands is incorrect, or a command is unacceptable. issuing a clock-mo de selection command be fore a device selection or an inquiry command after the transition to programming/erasing state command, are examples. error response h'80 h'xx ? error response, h'80, (one byte): command error ? command, h'xx, (one byte): received command section 21 flash memory rev. 1.00 sep. 13, 2007 page 896 of 1102 rej09b0365-0100 (7) command order the order for commands in the inquir y selection state is shown below. 1. a supported device inquiry (h'20) should be made to inquire about the supported devices. 2. the device should be selected from among those described by the returned information and set with a device-selection (h'10) command. 3. a clock-mode inquiry (h'21) should be made to inquire about the supported clock modes. 4. the clock mode should be selected from among those described by the returned information and set. 5. after selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (h'22) or operating frequency inquiry (h'23), which are needed for a new bit-rate selection. 6. a new bit rate should be selected with the new bit-rate selection (h'3f) command, according to the returned information on multiplication ratios and operating frequencies. 7. after selection of the device and clock mode, the information of the user boot mat and user mat should be made to inquire about the user boot mats information inquiry (h'24), user mats information inquiry (h'25), erased block information inquiry (h'26), and programming unit inquiry (h'27). 8. after making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (h'40) . the boot program will then enter the programming/erasing state. section 21 flash memory rev. 1.00 sep. 13, 2007 page 897 of 1102 rej09b0365-0100 (8) programming/erasing state a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. table 21.16 lists the programming/erasing commands. table 21.16 programming/erasing commands command command name description h'42 user boot mat programming selection t ransfers the user boot mat programming program h'43 user mat programming selection transfers the user mat programming program h'50 128-byte programming programs 128 bytes of data h'48 erasing selection trans fers the erasing program h'58 block erasing erases a block of data h'52 memory read reads the contents of memory h'4a user boot mat sum check checks the checksum of the user boot mat h'4b user mat sum check checks the checksum of the user mat h'4c user boot mat blank check checks the blank data of the user boot mat h'4d user mat blank check checks the blank data of the user mat h'4c user boot mat blank check che cks whether the cont ents of the user boot mat are blank h'4d user mat blank check checks whether the content s of the user mat are blank h'4f boot program status inquiry i nquires into the boot program's status section 21 flash memory rev. 1.00 sep. 13, 2007 page 898 of 1102 rej09b0365-0100 ? programming programming is executed by the programming selection and 128-byte programming commands. firstly, the host should send the programming selection command and select the programming method and programming mats. there are two programming selection commands, and selection is according to the ar ea and method for programming. 1. user boot mat programming selection 2. user mat programming selection after issuing the programming selection command, the host should send the 128-byte programming command. the 128-byte programming command that follows the selection command represents the data pr ogrammed according to the meth od specified by the selection command. when more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. sending a 128-byte programming command with h'ffffffff as the address will stop the programming. on completion of programming, the boot program will wait for selection of programming or erasing. where the sequence of programming operations th at is executed includes programming with another method or of another mat, the procedure must be repeated from the programming selection command. the sequence for the programming selection and 128-byte programming commands is shown in figure 21.25. transfer of the programming program host boot program programming selection (h'42, h'43) ack programming 128-byte programming (address, data) ack 128-byte programming (h'ffffffff) ack repeat figure 21.25 programming sequence section 21 flash memory rev. 1.00 sep. 13, 2007 page 899 of 1102 rej09b0365-0100 ? erasure erasure is executed by the erasure selection an d block erasure commands. firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. the command should be repeat edly executed if two or more blocks are to be erased. sending a block erasure command from the host with the block number h'ff will stop the erasure operating. on completion of erasing, the boot program will wait for selection of programming or erasing. the sequence for the erasure selection and bloc k erasure commands is shown in figure 21.26. transfer of erasure program host boot program preparation for erasure (h'48) ack erasure erasure (erasure block number) erasure (h'ff) ack ack repeat figure 21.26 erasure sequence section 21 flash memory rev. 1.00 sep. 13, 2007 page 900 of 1102 rej09b0365-0100 (a) user boot mat programming selection the boot program will transfer a programming program. the data is programmed to the user boot mats by the transferred programming program. command h'42 ? command, h'42, (one byte): user boot mat programming selection response h'06 ? response, h'06, (one byte): response to user boot mat programming selection when the programming program has been transferred, the boot program will return ack. error response h'c2 error ? error response : h'c2 (1 byte): error response to user boot mat programming selection ? error : (1 byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) (b) user mat programming selection the boot program will transfer a program for us er mat programming selection. the data is programmed to the user mats by the transferred program for programming. command h'43 ? command, h'43, (one byte): user mat programming selection response h'06 ? response, h'06, (one byte): response to user mat programming selection when the programming program has been transferred, the boot program will return ack. error response h'c3 error ? error response : h'c3 (1 byte): error response to user mat programming selection ? error : (1 byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) section 21 flash memory rev. 1.00 sep. 13, 2007 page 901 of 1102 rej09b0365-0100 (c) 128-byte programming the boot program will use the programming program transferred by the programming selection to program the user boot mats or user mats in response to 128-byte programming. command h'50 address data sum ? command, h'50, (one byte): 128-byte programming ? programming address (four bytes): start address for programming multiple of the size specified in response to the programming unit inquiry (i.e. h'00, h'01, h'00, h'00 : h'01000000) ? program data (128 bytes): data to be programmed the size is specified in the response to the programming unit inquiry. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to 128-byte programming on completion of programming, the boot program will return ack. error response h'd0 error ? error response, h'd0, (one byte): error response for 128-byte programming ? error: (one byte): error code h'11: checksum error h'2a: address error the address is not in the specified mat. h'53: programming error a programming error has occurred and programming cannot be continued. the specified address should match the unit for programming of data. fo r example, when the programming is in 128-byte units, the lower eight bits of the address should be h'00 or h'80. when there are less than 128 bytes of data to be programmed, the host should fill the rest with h'ff. sending the 128-byte programming command with the address of h'ffffffff will stop the programming operation. the boot program will interpret this as the end of the programming and wait for selection of programming or erasing. section 21 flash memory rev. 1.00 sep. 13, 2007 page 902 of 1102 rej09b0365-0100 command h'50 address sum ? command, h'50, (one byte): 128-byte programming ? programming address (four bytes): end code is h'ff, h'ff, h'ff, h'ff. ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to 128-byte programming on completion of programming, the boot program will return ack. error response h'd0 error ? error response, h'd0, (one byte): error response for 128-byte programming ? error: (one byte): error code h'11: checksum error h'53: programming error an error has occurred in programming and programming cannot be continued. (d) erasure selection the boot program will transfer th e erasure program. user mat data is erased by the transferred erasure program. command h'48 ? command, h'48, (one byte): erasure selection response h'06 ? response, h'06, (one byte): response for erasure selection after the erasure program has been transferred, the boot program will return ack. error response h'c8 error ? error response, h'c8, (one byte): error response to erasure selection ? error: (one byte): error code h'54: selection processing error (transfer error occurs and processing is not completed) section 21 flash memory rev. 1.00 sep. 13, 2007 page 903 of 1102 rej09b0365-0100 (e) block erasure the boot program will erase the contents of the specified block. command h'58 size block number sum ? command, h'58, (one byte): erasure ? size (one byte): the number of bytes th at represents the erase block number this is fixed to 1. ? block number (one byte): number of the block to be erased ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to erasure after erasure has been completed, the boot program will return ack. error response h'd8 error ? error response, h'd8, (one byte): response to erasure ? error (one byte): error code h'11: sum check error h'29: block number error block number is incorrect. h'51: erasure error an error has occurred during erasure. on receiving block number h'ff, the boot program will stop erasure and wait for a selection command. command h'58 size block number sum ? command, h'58, (one byte): erasure ? size, (one byte): the number of bytes that represents the block number this is fixed to 1. ? block number (one byte): h'ff stop code for erasure ? sum (one byte): checksum response h'06 ? response, h'06, (one byte): response to end of erasure (ack) when erasure is to be performed after the block number h'ff has been sent, the procedure should be executed from the erasure selection command. section 21 flash memory rev. 1.00 sep. 13, 2007 page 904 of 1102 rej09b0365-0100 (f) memory read the boot program will return the data in the specified address. command h'52 size area read address read size sum ? command: h'52 (1 byte): memory read ? size (1 byte): amount of data that represents th e area, read address, and read size (fixed at 9) ? area (1 byte) h'00: user boot mat h'01: user mat an address error occurs wh en the area setting is incorrect. ? read address (4 bytes): star t address to be read from ? read size (4 bytes): size of data to be read ? sum (1 byte): checksum response h'52 read size data sum ? response: h'52 (1 byte): response to memory read ? read size (4 bytes): size of data to be read ? data (n bytes): data for the read size from the read address ? sum (1 byte): checksum error response h'd2 error ? error response: h'd2 (1 byte): error response to memory read ? error: (1 byte): error code h'11: sum check error h'2a: address error the read address is not in the mat. h'2b: size error the read size exceeds the mat. section 21 flash memory rev. 1.00 sep. 13, 2007 page 905 of 1102 rej09b0365-0100 (g) user boot mat sum check the boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value. command h'4a ? command, h'4a, (one byte): sum check for user-boot program response h'5a size checksum of user boot program sum ? response, h'5a, (one byte): response to the sum check of user-boot program ? size (one byte): the number of byt es that represents the checksum this is fixed to 4. ? checksum of user boot program (four bytes): checksum of user boot mats the total of the data is obtained in byte units. ? sum (one byte): sum check for data being transmitted (h) user mat sum check the boot program will return the byte-by-byte total of the contents of the bytes of the user program. command h'4b ? command, h'4b, (one byte): sum check for user program response h'5b size checksum of user program sum ? response, h'5b, (one byte): response to the sum check of the user program ? size (one byte): the number of byt es that represents the checksum this is fixed to 4. ? checksum of user boot program (four bytes): checksum of user mats the total of the data is obtained in byte units. ? sum (one byte): sum check for data being transmitted section 21 flash memory rev. 1.00 sep. 13, 2007 page 906 of 1102 rej09b0365-0100 (i) user boot mat blank check the boot program will check whether or not all user boot mats are blank and return the result. command h'4c ? command, h'4c, (one byte): blank check for user boot mat response h'06 ? response, h'06, (one byte): response to the blank check of user boot mat if all user mats are blank (h'ff), th e boot program will return ack. error response h'cc h'52 ? error response, h'cc, (one byte): response to blank check for user boot mat ? error code, h'52, (one byte): erasure has not been completed. (j) user mat blank check the boot program will check whether or not all user mats are blank and return the result. command h'4d ? command, h'4d, (one byte): blank check for user mats response h'06 ? response, h'06, (one byte): response to the blank check for user mats if the contents of all user mats are blank (h'ff), the boot program will return ack. error response h'cd h'52 ? error response, h'cd, (one byte): error response to the blank check of user mats. ? error code, h'52, (one byte): erasure has not been completed. section 21 flash memory rev. 1.00 sep. 13, 2007 page 907 of 1102 rej09b0365-0100 (k) boot program state inquiry the boot program will return indications of its present state and error condition. this inquiry can be made in the inquiry/selection stat e or the programming/erasing state. command h'4f ? command, h'4f, (one byte): inquiry regarding boot program's state response h'5f size status error sum ? response, h'5f, (one byte): response to boot program state inquiry ? size (one byte): the number of bytes. this is fixed to 2. ? status (one byte): state of the boot program ? error (one byte): error status error = 0 indicates normal operation. error = 1 indicates error has occurred. ? sum (one byte): sum check table 21.17 status code code description h'11 device selection wait h'12 clock mode selection wait h'13 bit rate selection wait h'1f programming/erasing stat e transition wait (bit rate selection is completed) h'31 programming state for erasure h'3f programming/erasing selection wait (erasure is completed) h'4f program data receive wait h'5f erase block specification wait (erasure is completed) section 21 flash memory rev. 1.00 sep. 13, 2007 page 908 of 1102 rej09b0365-0100 table 21.18 error code code description h'00 no error h'11 sum check error h'12 program size error h'21 device code mismatch error h'22 clock mode mismatch error h'24 bit rate selection error h'25 input frequency error h'26 multiplication ratio error h'27 operating frequency error h'29 block number error h'2a address error h'2b data length error h'51 erasure error h'52 erasure incomplete error h'53 programming error h'54 selection processing error h'80 command error h'ff bit-rate-adjustment confirmation error section 21 flash memory rev. 1.00 sep. 13, 2007 page 909 of 1102 rej09b0365-0100 21.14 usage notes 1. the initial state of the product at its shipment is in the erased state. for the product whose revision of erasing is undefined, we recommend to execute automatic er asure for checking the initial state (erased state) and compensating. 2. for the prom programmer suitable for programmer mode in this lsi and its program version, refer to the instruction manual of the socket adapter. 3. if the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. use a prom programmer that supports the device with 1-mbyte on-chip flash memory and 3.3-v programming voltage. use only the specified socket adapter. 5. do not remove the chip from the prom programmer nor input a reset signal during programming/erasure in which a high voltage is applied to the flash memory. doing so may damage the flash memory permanently. if a reset is input accidentally, the reset must be released after the reset input period of at least 100 s. 6. the flash memory is not accessi ble until fkey is cleared after programming/erasure starts. if the operating mode is changed and this lsi is restarted by a reset immediately after programming/erasure has finished, secure the reset input period (period of res = 0) of at least 100 s. transition to the reset state during programming/erasure is inhibited. if a reset is input accidentally, the reset must be released afte r the reset input period of at least 100 s. 7. at powering on or off the vcc power supply, fix the res pin to low and set the flash memory to hardware protection state. this power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. in on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. perform programming in the state where the programming-unit block is fully erased. 9. when the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. to program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and h'ff must be written to all the system reserved areas in th e exception handling vector table. 11. the programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. accordingly, when the cpu clock frequency is 35 mhz, the download for each program takes approximately 60 s at the maximum. section 21 flash memory rev. 1.00 sep. 13, 2007 page 910 of 1102 rej09b0365-0100 12. a programming/erasing program for the flash memory used in a conventional f-ztat h8, h8s microcomputer which does not support download of the on-chip program by setting the sco bit in fccs to 1 cannot run in this lsi. be sure to download the on-chip program to execute programming/erasure of the flash memo ry in this f-ztat h8sx microcomputer. 13. unlike a conventional f-ztat h8 or h8s microcomputers, measures against a program crash are not taken by wdt while programming/erasing and downloading a programming/erasing program. when needed, measures should be taken by user. a periodic interrupt generated by the wdt can be used as the meas ures, as an example. in this case, the interrupt generation period should take into consideration time to program/erase the flash memory. 14. when downloading the programming/erasing program, do not clear the sco bit in fccs to 0 immediately after setting it to 1. otherwise, download cannot be performed normally. immediately after executing the in struction to set the sco bit to 1, dummy read of the fccs must be executed twice. 15. the contents of general registers er0 and er1 are not saved during download of an on-chip program, initialization, programming, or erasur e. when needed, save the general registers before a download request or before execution of initialization, programming, or erasure using the procedure program. section 22 boundary scan rev. 1.00 sep. 13, 2007 page 911 of 1102 rej09b0365-0100 section 22 boundary scan this lsi has boundary scan function, which is a serial i/o interface based on the jtag (joint test action group, ieee std.1149.1 and ieee standard test acce ss port and boundary-scan architecture). 22.1 features ? boundary scan valid single chip mode when the emle pin= 0 in mcu operating mode 3 ? p62, p63, p64, p65, and wdtovf are pins only for boundary scan when boundary scan is valid ? six test modes: bypass mode extest mode sample/preload mode clamp mode highz mode idcode mode section 22 boundary scan rev. 1.00 sep. 13, 2007 page 912 of 1102 rej09b0365-0100 22.2 block diagram of boundary scan function figure 22.1 shows the block diagram of the boundary scan function. jtbpr tdi tdo tck tms trst jtbsr shift register mux tap controller decoder jtir jtdir jtbpr: jtbsr: jtir: jtdir: bypass register boundary scan register instruction register id register [legend] figure 22.1 block diagram of boundary scan function 22.3 input/output pins table 22.1 shows the i/o pins used in the boundary scan function. table 22.1 pin configuration pin name i/o description tck input test clock input pin clock signal for boundary scan. input the clock the duty cycle of which is 50 percent when boundary scan function is used. tms input test mode select pin tdi input test data input pin tdo output test data output pin trst input test reset input pin section 22 boundary scan rev. 1.00 sep. 13, 2007 page 913 of 1102 rej09b0365-0100 22.4 register descriptions boundary scan has the following four registers. these registers cannot be accessed from the cpu. ? introduction register (jtir) ? bypass register (jtbpr) ? boundary scan register (jtbsr) ? idcode register (jtidr) instructions can be input to the instruction regist er (jtir) via the test data input pin (tdi) by serial transfer. the bypass regist er (jtbpr), which is a 1-bit register, is connected between the tdi and tdo pins in bypass mode. the boundary scan register (jtbsr), which is a t.b.d-bit register, is connected between the tdi and tdo pins when test data are being shifted in. none of the registers is accessible from the cpu. table 22.2 shows the availability of serial transfer for the registers. table 22.2 serial transfers for registers register abbreviation serial input serial output jtir available not available jtbpr available available jtbsr available available jtid not available available section 22 boundary scan rev. 1.00 sep. 13, 2007 page 914 of 1102 rej09b0365-0100 22.4.1 instruction register (jtir) jtir is a 16-bit register. jtag instructions can be transferred to jtir by serial input from the tdi pin. jtir is initialized when the trst signal is low level, when the tap controller is in the test-logic-reset state, and when this lsi is placed in hardware stan dby mode. jtir is not initialized by a reset or entry to software standby mo de. instructions must be serially transferred in 4-bit units. when an instruction with more than 4 bits is being transferred, the last four bits of the serial data are stored in jtir. bit bit name initial value r/w 15 ts3 0 ? 14 ts2 0 ? 13 ts1 0 ? 12 ts0 0 ? 11 ? 0 ? 10 ? 0 ? 9 ? 0 ? 8 ? 0 ? bit bit name initial value r/w 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 2 ? 0 ? 1 ? 0 ? 0 ? 0 ? bit bit name initial value r/w descriptions 15 to 12 ts[3:0] all 0 r/w test bit set specify an instruction as shown in table 22.3. 11 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always 0. section 22 boundary scan rev. 1.00 sep. 13, 2007 page 915 of 1102 rej09b0365-0100 table 22.3 boundary scan instructions ts3 ts2 ts1 ts0 instruction 0 0 0 0 extest 0 0 0 1 idcode (initial value) 0 0 1 0 clamp 0 0 1 1 highz 0 1 0 0 sample/preload 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 bypass 22.4.2 bypass register (jtbpr) jtbpr is a 1-bit register and is connected betw een the tdi and tdo pins when jtir is set to bypass mode. jtbpr cannot be read from or written to by the cpu. section 22 boundary scan rev. 1.00 sep. 13, 2007 page 916 of 1102 rej09b0365-0100 22.4.3 boundary scan register (jtbsr) jtbsr is a shift register to control the external input and output pins of this lsi and is distributed across the pads. the initial values are undefine d. jtbsr cannot be accessed by the cpu. the extest, sample/preload, clamp, and highz instructions are issued to apply jtbsr in boundary-scan testing conformant to the jtag standard. table 22.4 shows the correspondence between the jtbsr bits and the pins of this lsi. table 22.4 relationship between pins and jtbsr bits pin no. pin name input/output bit name from tdi 3 pb3 input output enable output 295 294 293 5 pb7 input output enable output 292 291 290 7 md2 input 289 8 pn0 input 285 9 pn1 input 281 10 pc5 input output enable output 277 276 275 11 pf7 input output enable output 274 273 272 12 pf6 input output enable output 271 270 269 13 pf5 input output enable output 268 267 266 14 pf4 input output enable output 265 264 263 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 917 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 15 pf3 input output enable output 262 261 260 17 pf2 input output enable output 259 258 257 18 pf1 input output enable output 256 255 254 19 pf0 input output enable output 253 252 251 20 pe7 input output enable output 250 249 248 21 pe6 input output enable output 247 246 245 22 pe5 input output enable output 244 243 242 24 pe4 input output enable output 241 240 239 26 pe3 input output enable output 238 237 236 27 pe2 input output enable output 235 234 233 28 pe1 input output enable output 232 231 230 29 pe0 input output enable output 229 228 227 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 918 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 30 pd7 input output enable output 226 225 224 31 pd6 input output enable output 223 222 221 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 919 of 1102 rej09b0365-0100 pin no. pin name input/output bit name to tdo 33 pd5 input output enable output 220 219 218 34 pd4 input output enable output 217 216 215 35 pd3 input output enable output 214 213 212 36 pd2 input output enable output 211 210 209 37 pd1 input output enable output 208 207 206 38 pd0 input output enable output 205 204 203 40 pn2 input 202 41 pn3 input 198 45 pc0 input output enable output 192 191 190 46 pc1 input output enable output 189 188 187 47 pc4 input output enable output 186 185 184 49 p20 input output enable output 183 182 181 51 p21 input output enable output 180 179 178 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 920 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 52 p22 input output enable output 177 176 175 53 p23 input output enable output 174 173 172 54 p24 input output enable output 171 170 169 55 p25 input output enable output 168 167 166 56 p30 input output enable output 165 164 163 57 p31 input output enable output 162 161 160 58 p32 input output enable output 159 158 157 59 p26 input output enable output 156 155 154 60 p27 input output enable output 153 152 151 61 nmi input 150 62 p33 input output enable output 149 148 147 63 p34 input output enable output 146 145 144 65 ph0 input output enable output 143 142 141 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 921 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 66 ph1 input output enable output 140 139 138 67 ph2 input output enable output 137 136 135 68 ph3 input output enable output 134 133 132 73 ph7 input output enable output 131 130 129 70 ph4 input output enable output 128 127 126 71 ph5 input output enable output 125 124 123 72 ph6 input output enable output 122 121 120 76 pi1 input output enable output 119 118 117 77 pi2 input output enable output 116 115 114 78 pi3 input output enable output 113 112 111 75 pi0 input output enable output 110 109 108 80 pi4 input output enable output 107 106 105 81 pi5 input output enable output 104 103 102 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 922 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 83 pi7 input output enable output 101 100 99 82 pi6 input output enable output 98 97 96 84 p10 input output enable output 95 94 93 85 p11 input output enable output 92 91 90 86 p12 input output enable output 89 88 87 87 p13 input output enable output 86 85 84 89 p66 input output enable output 83 82 81 90 p67 input output enable output 80 79 78 93 p14 input output enable output 77 76 75 94 p15 input output enable output 74 73 72 100 p16 input output enable output 71 70 69 101 p17 input output enable output 68 67 66 105 pb2 input output enable output 65 64 63 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 923 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 104 p35 input output enable output 62 61 60 107 p60 input output enable output 59 58 57 106 p37 input output enable output 56 55 54 108 p61 input output enable output 53 52 51 115 md0 input 50 116 pc2 input output enable output 49 48 47 117 pc3 input output enable output 46 45 44 133 md1 input 43 42 pb4 input output enable output 42 41 40 43 pb5 input output enable output 39 38 37 44 pb6 input output enable output 36 35 34 134 pa0 input output enable output 32 31 30 135 pa1 input output enable output 29 28 27 136 pa2 input output enable output 26 25 24 section 22 boundary scan rev. 1.00 sep. 13, 2007 page 924 of 1102 rej09b0365-0100 pin no. pin name input/output bit name 137 pa3 input output enable output 23 22 21 138 pa4 input output enable output 20 19 18 139 pa5 input output enable output 17 16 15 140 pa6 input output enable output 14 13 12 142 pa7 input output enable output 11 10 9 144 pb0 input output enable output 8 7 6 1 pb1 input output enable output 5 4 3 2 pb2 input output enable output 2 1 0 to tdo section 22 boundary scan rev. 1.00 sep. 13, 2007 page 925 of 1102 rej09b0365-0100 22.4.4 idcode register (jtid) jtid is a 32-bit register. jtid data is output from the tdo pin when the idcode instruction has been executed. data cannot be written to jtid from the tdi pin. bit bit name initial value r/w 31 did31 ? r/w 30 did30 ? r/w 29 did29 ? r/w 28 did28 ? r/w 27 did27 ? r/w 26 did26 ? r/w 25 did25 ? r/w 24 did24 ? r/w 23 did23 ? r/w 22 did22 ? r/w 21 did21 ? r/w 20 did20 ? r/w 19 did19 ? r/w 18 did18 ? r/w 17 did17 ? r/w 16 did16 ? r/w bit bit name initial value r/w 15 did15 ? r/w 14 did14 ? r/w 13 did13 ? r/w 12 did12 ? r/w 11 did11 ? r/w 10 did10 ? r/w 9 did9 ? r/w 8 did8 ? r/w 7 did7 ? r/w 6 did6 ? r/w 5 did5 ? r/w 4 did4 ? r/w 3 did3 ? r/w 2 did2 ? r/w 1 did1 ? r/w 0 did0 ? r/w bit bit name initial value r/w descriptions 31 to 0 did31 to did0 h?0803a447 ? jtid is a register the value showing the decide idcode is fixed. section 22 boundary scan rev. 1.00 sep. 13, 2007 page 926 of 1102 rej09b0365-0100 22.5 operations the boundary scan functionality is valid when the emle pin is set t o 0 and this lsi is in mcu operation mode 3. 22.5.1 tap controller figure 22.2 shows the state transition diagram of the tap controller. test -logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr run-test/idle 1 0 0 0 0 11 1 1 0 0 0 1 11 0 1 1 1 0 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir 0 0 1 0 0 0 1 0 1 1 10 figure 22.2 state transi tions of the tap controller section 22 boundary scan rev. 1.00 sep. 13, 2007 page 927 of 1102 rej09b0365-0100 22.5.2 commands bypass (instruction code: b'1111): the bypass instruction is an instruction that drives the bypass register (jtbpr). this instruction shortens the shift path, facilitating the transfer of serial data to other lsis on a printed-circuit board at higher speeds. while this instruction is being executed, the test circuit has no effect on the system circuits. the bypass register (jtbpr) is connected betw een the tdi and tdo pins. bypass operation is initiated from shift-dr operation. the tdo is at 0 in the first clock cycle in the shift-dr state; in the subsequent clock cycles, the tdi signal is output on the tdo pin. extest (instruction code: b'0000): the extest instruction is used to test external circuits when this lsi is installed on the printed circuit board. if this instruction is executed, output pins are used to output test data (specified by the sample/preload instruction) from the boundary scan register to the print circuit board, and input pins are used to input test result. sample/preload (instruction code: b'0100): the sample/preload instruction is used to input data from the lsi internal circuits to the boundary scan register, output data from scan path, and reload the data to the scan path. while this instruction is executed, input signals are directly input to the lsi and output signals are also directly output to the external circuits. the lsi system circuit is not affected by this function. in sample operation, the boundary scan register latches the snap shot of data transferred from input pins to internal circuit or data transferred from internal circuit to output pins. the latched data is read from the scan path. the scan register latches the snap data at the rising edge of the tck in capture-dr state. the s can register latches snap shot without affecting the lsi normal operation. in preload operation, initial value is written from th e scan path to the parallel output latch of the boundary scan register prior to the extest instruction execution. if the extest is executed without executing this preload operation, undefined values are output from the beginning to the end (transfer to the output latch) of the extest sequence. (in extes t instruction, output parallel latches are always output to the output pins.) idcode (instruction code: b'0001): when the idcode instruction is selected, idcode register value is output to the tdo in shift-dr state of the tap controller. in this case, idcode register value is output from the lsb. during this instruction execution, test circuit does not affect the system circuit. instr is initialized by the id code instruction in test-logic-reset state of the tap controller. section 22 boundary scan rev. 1.00 sep. 13, 2007 page 928 of 1102 rej09b0365-0100 clamp (instruction code: b'0010): when the clamp instruction is selected, output pins output the boundary scan register value which was specified by the sample/preload instruction in advance. while the clamp instruc tion is selected, the stat us of boundary scan register is maintained regardless of the tap co ntroller state. bypass is connected between tdi and tdo, the same operation as bypass instruction can be achieved. this instruction connects the bypass register (jtbpr) between the tdi and tdo pins, leading to the same operation as when bypa ss mode has been selected. highz (instruction code: b'0011): when the highz instruction is selected, all output pins enter high-impedance state. while the highz instruction is selected, the status of boundary scan register is maintained regardless of the state of the tap controller. bypass is connected between tdi and tdo pins, leading to the same operation as when the bypass instruction has been selected. 22.6 usage notes 1. in serial transfer, data are input or output in lsb order (see figure 22.3). from tdi pin jtir and jtidr bit 31 bit 30 bit 1 bit 0 shift register serial data input/output in lsb order notes: serial data output from jtir to tdo is not possible. serial data input from tdi to jtidr is not possible. to tdo pin . . . . . . figure 22.3 serial data input/output section 22 boundary scan rev. 1.00 sep. 13, 2007 page 929 of 1102 rej09b0365-0100 2. if a pin with open-drain function is sampleed while its open-drain function is enabled and while the corresponding out register is set to 1, the corresponding control register is cleared to 0 (the pin status is hi-z). if the pin is sampleed while the corresponding out register is cleared to 0, the corresponding control register is set to 1 (the pin status is 0) 3. pins of the boundary scan (tck, tdi, tms, and trst) have to be pulled up by pull-up resistors. 4. power supply pins (vcc, vcl, vss, avcc, avss, avref, drvcc, drvss, pllvcc, and pllvss) cannot be boundary-scanned. 5. clock pins (extal and xtal) cannot be boundary-scanned. 6. reset and standby signals (res and stby) cannot be boundary-scanned. 7. boundary scan pins (tck, tms, trst, tdi, and tdo) cannot be boundary-scanned. 8. the boundary scan function is not availabl e when this lsi are in the following states. (1) reset state (2) hardware standby mode, software standby mode, and deep software standby mode 9. jtag/h-udi-related signals (tck, tms, trst , tdi, and tdo) cannot be boundary- scanned. 22.7 supplementary information 22.7.1 notes on serial transfer (1) jtir register data in sdir are written to the 4-bit shift register upon entry to the capture-dr state, but are not output on the tdo pin. data input from the tdi pin are shifted to the shift register upon entry to th e shift-ir state and are written to sdir upon entr y to the update-ir state. if the data have been shifted by no more than thr ee bits in the shift-ir st ate, the data that have been written to the shift register upon entry to the capture-ir state are again written to sdir upon entry to the update-ir state. if the data have been shifted by four or more bits, the last four bits are written to sdir. (2) bypass mode in bypass mode, data input from the tdi pin are output on the tdo pin via the 1-bit bypass register (jtbpr) in the shift-dr state. a bit of tdi data that has been input on the falling edge of section 22 boundary scan rev. 1.00 sep. 13, 2007 page 930 of 1102 rej09b0365-0100 one tck clock pulse is output on the tdo pin on the rising edge of the subsequent tck clock pulse, i.e. half a clock cycle later. figure 22.4 shows the data flow in serial transfer. (1) modes other than bypass mode: (2) bypass mode: jtidr tdi pin update-dr capture-dr update-ir capture-ir tdi pin tdo pin tdo pin jtir 32-bit shift register 4-bit shift register 1-bit bypass register (jtbpr) figure 22.4 serial data flow section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 931 of 1102 rej09b0365-0100 section 23 clock pulse generator this lsi has an on-chip clock pulse generator (cpg) that generates the system clock (i ), peripheral module clock (p ), and external bus clock (b ). the clock pulse generator consists of a main clock oscillator, frequency divider, pll ( phase-locked loop) circuit, waveform generation circuit, and selector. figure 23.1 is a block diagram of the clock pulse generator. the frequency divider, pll circuit, and selector can change the clock frequency. software changes the frequency through the setting of the system clock control register (sckcr). this lsi supports five clocks: a system clock provided to the cpu and bus masters, a peripheral module clock provided to the peripheral modules, an external bus clock prov ided to the external bus. frequencies of the peripheral module clock, the external bus clock, and the system clock can be set independently, although the peripheral module clock and the external bus clock operate with the frequency lower than the system clock frequency. extal xtal pll circuit main clock oscillator to system clock (i ), (to the cpu and bus masters) peripheral module clock (p ) (to peripheral modules) external bus clock (b ) (to the b pin) ick2 to ick0 cks ckb ckm sckcr divider pck2 to pck0 bck2 to bck0 selector 2 1 1/2 extal 4 sckcr selector sckcr selector figure 23.1 block diagra m of clock pulse generator section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 932 of 1102 rej09b0365-0100 table 23.1 selection of clock pulse generator extal input clock frequency i /p /b 8 mhz to 18 mhz extal 4, 2, 1, 1/2 section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 933 of 1102 rej09b0365-0100 23.1 register description the clock pulse generator has the following registers. ? system clock control register (sckcr) 23.1.1 system clock control register (sckcr) sckcr controls b output control and frequencies of the system, peripheral module, and external bus clocks. bit bit name initial value r/w 15 pstop1 0 r/w 14 pstop0 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 ? 0 r/w 10 ick2 0 r/w 9 ick1 1 r/w 8 ick0 0 r/w bit bit name initial value r/w 7 ? 0 r/w 6 pck2 0 r/w 5 pck1 1 r/w 4 pck0 0 r/w 3 ? 0 r/w 2 bck2 0 r/w 1 bck1 1 r/w 0 bck0 0 r/w bit bit name initial value r/w description 15 pstop1 0 r/w b clock output enable controls output on pa7. ? normal operation 0: output 1: fixed high 14 pstop0 0 r/w reserved although this bit is readable/ writable, do not write 0 to this bit. section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 934 of 1102 rej09b0365-0100 bit bit name initial value r/w description 13 to 11 ? all 0 r/w reserved although these bits are readable/writable, only 0 should be written to. 10 9 8 ick2 ick1 ick0 0 1 0 r/w r/w r/w system clock (i ) select these bits select the frequency of the system clock provided to the cpu, dmac, and dtc. the ratio to the input clock is as follows: ick (2:0) 000: 4 001: 2 010: 1 011: 1/2 1xx: setting prohibited the frequencies of the peripheral module clock and external bus clock change to the same frequency as the system clock if the frequency of the system clock is lower than that of the two clocks. 7 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. 6 5 4 pck2 pck1 pck0 0 1 0 r/w r/w r/w peripheral module clock (p ) select these bits select the frequency of the peripheral module clock. the ratio to the input clock is as follows: pck (2:0) 000: 4 001: 2 010: 1 011: 1/2 1xx: setting prohibited the frequency of the peripheral module clock should be lower than that of the system clock. though these bits can be set so as to make the frequency of the peripheral module clock high er than that of the system clock, the clocks will have the same frequency in reality. section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 935 of 1102 rej09b0365-0100 bit bit name initial value r/w description 3 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. 2 1 0 bck2 bck1 bck0 0 1 0 r/w r/w r/w external bus clock (b ) select these bits select the fr equency of the external bus clock. the ratio to the input clock is as follows: bck (2:0) 000: 4 001: 2 010: 1 011: 1/2 1xx: setting prohibited the frequency of the external bus clock should be lower than that of the system clo ck. though these bits can be set so as to make the frequency of the external bus clock higher than that of the system clock, the clocks will have the same frequency in reality. note: x: don't care section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 936 of 1102 rej09b0365-0100 23.2 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.2.1 connecting crystal resonator a crystal resonator can be connected as the exam ple in figure 23.2. select the damping resistance r d according to table 23.2. an at-cut pa rallel-resonance type should be used. when providing the clock from the crystal resonator, the frequency should be in the range of 8 to 18 mhz. extal xtal r d c l2 c l1 c l1 = c l2 = 10 pf to 22 pf figure 23.2 connection of crystal resonator (example) table 23.2 damping resistance value frequency (mhz) 8 12 16 18 r d ( ? ) 200 0 0 0 figure 23.3 shows an equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 23.3. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 23.3 crystal reso nator equivalent circuit section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 937 of 1102 rej09b0365-0100 table 23.3 crystal resonator characteristics frequency (mhz) 8 12 16 18 r s max. ( ? ) 80 60 50 40 c 0 max. (pf) 7 7 7 7 23.2.2 external clock input an external clock signal can be input as the exam ples in figure 23.4. when the xtal pin is left open, make the parasitic capacitance less than 10 pf. when the counter clock is input to the xtal pin, put the external clock in high level during standby mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input (b) counter clock input on xtal pin figure 23.4 external clock input (examples) extal t exh t exl t exr t exf vcc 0.5 figure 23.5 external clock input timing section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 938 of 1102 rej09b0365-0100 23.3 pll circuit the pll circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 4. the frequency multiplication rate is fi xed. the phase difference is controlled so that the timing of the rising edge of the internal clock is the same as that of the extal pin signal. 23.4 frequency divider the frequency divider divides the pll clock to generate a 1/2, 1/4, or 1/8 clock. after the bits ick2 to ick0, pck 2 to pck0, and bck2 to bck0 are updated, this lsi operates with the updated frequency. 23.5 usage notes 23.5.1 notes on clock pulse generator 1. the following points should be noted since the frequency of (i : system clock, p : peripheral module clock, b : external bus clock) supplied to each module changes according to the setting of sckcr. select a clock division ratio that is within the operation guaranteed range of clock cycle time t cyc shown in the ac timing of electrical characteristics. the frequency should be set under the conditions of 8 mhz i 50 mhz, 8 mhz p 35 mhz, and 8 mhz b 50 mhz. 2. all the on-chip peripheral modules (excep t for the dmac and dt c) operate on the p . note therefore that the time processing of modules such as a timer and sci differs before and after changing the clock division ratio. in addition, wait time for clearing software standby mode differs by changing the clock division ratio. for details, see section 24.7.3, setting oscillation settling time after exit from software standby mode. 3. the relationship among the system clock, peripheral module clock, and external bus clock is i p and i b . in addition, the system clock setting has the highest priority. accordingly, p or b may have the frequency set by bits ick2 to ick0 regardless of the settings of bits pck2 to pck0 or bck2 to bck0. 4. note that the frequency of will be changed in the middle of a bus cycle when setting sckcr while executing the external bus cycle with the write-data-buffer function. 5. figure 23.6 shows the clock modification timing. after a value is written to sckcr, this lsi waits for the current bus cycle to complete. af ter the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external input clock . section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 939 of 1102 rej09b0365-0100 external clock one cycle (worst case) after the bus cycle completion operating clock specified in sckcr operating clock changed i cpu cpu cpu bus master figure 23.6 clock modification timing 23.5.2 notes on resonator since various characteristics related to the resonato r are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. as the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manu facturer. the design must ensure that a voltage exceeding the maximum rating is no t applied to the resonator pin. 23.5.3 notes on board design when using the crystal resonator, place the crystal resonator and its load capacitors as close to the xtal and extal pins as possible. other signal lines should be routed away from the oscillation circuit as shown in figure 23.7 to prevent induction from interfering with correct oscillation. c l2 signal a signal b c l1 this lsi xtal extal inhibited figure 23.7 note on board design for oscillation circuit section 23 clock pulse generator rev. 1.00 sep. 13, 2007 page 940 of 1102 rej09b0365-0100 figure 23.8 shows the external circuitry recomme nded for the pll circuit. separate pllvcc and pllvss from the other vcc and vss lines at the boar d power supply source, and be sure to insert bypass capacitors cpb and cb close to the pins. pllv cc pllv ss v cc v ss rp: 100 ? cpb: 0.1 f * cb: 0.1 f * note: * cb and cpb are laminated ceramic capacitors. figure 23.8 recommended extern al circuitry for pll circuit section 24 power-down modes rev. 1.00 sep. 13, 2007 page 941 of 1102 rej09b0365-0100 section 24 power-down modes functions for reduced power consumption by this lsi include a multi-clock function, module stop function, and a function for transition to power-down mode. 24.1 features ? multi-clock function the frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock. ? module stop function the functions for each peripheral module can be stopped to make a transition to a power-down mode. ? transition function to power-down mode transition to a power-down mode is possible to stop the cpu, peripheral modules, and oscillator. ? five power-down modes sleep mode all-module-clock-stop mode software standby mode deep software standby mode hardware standby mode table 24.1 shows conditions to shift to a powe r-down mode, states of the cpu and peripheral modules, and clearing method for each mode. after th e reset state, since this lsi operates in normal program execution state, the modules, other than the dmac and dtc, are stopped. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 942 of 1102 rej09b0365-0100 table 24.1 states of operation state of operation sleep mode all-module- clock-stop mode software standby mode deep software standby mode hardware standby mode transition condition control register + instruction control register + instruction control register + instruction control register + instruction pin input cancellation method interrupt interrupt * 2 external interrupt external interrupt oscillator operating oper ating halted halted halted cpu halted (retained) halted (retained) halted (retained) halted (undefined) halted (undefined) on-chip rams 6 to 4 (h?fee000 to h?ff3fff) operating (retained) halted (retained) halted (retained) halted (undefined) halted (undefined) on-chip rams 3 to 0 (h?ff4000 to h?ffbfff) operating (retained) halted (retained) halted (retained) halted (retained/ undefined) * 5 halted (undefined) watchdog timer operatin g operating halted (retained) halted (undefined) halted (undefined) 8-bit timer (unit 0/1) operating operating * 4 halted (retained) halted (undefined) halted (undefined) other peripheral modules operating halted * 1 halted * 1 halted * 7 (undefined) halted * 3 (undefined) i/o ports operating retained retained * 6 halted * 6 (undefined) hi-z notes: "halted (retained)" in the table means that the internal values are retained and internal operations are suspended. "halted (undefined)" in the table means t hat the internal values are undefined and the power supply for internal operations is turned off. 1. sci enters the reset state, and other peripheral modules retain their states. 2. external interrupt and some internal interrupts (8-bit timer and watchdog timer). 3. all peripheral modules enter the reset state. 4. "functioning" or "halted" is selectable through the setting of bits mstpa9 and mstpa8 in mstpcra. 5. "retained" or "undefined" of the contents of ram is select ed by the setting of the bits ramcut2 to ramcut0 in dpsbycr. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 943 of 1102 rej09b0365-0100 6. retention or high-impedance for the address bus and bus-control signals ( cs0 to cs7 , as , rd , hwr , and lwr ) is selected by the setti ng of the ope bit in sbycr. 7. some peripheral modules enter a state where the register values are retained. sleep instruction * 4 sleep instruction * 4 (ssby = 1) all interrupts sleep instruction * 4 external interrupt * 2 interrupt * 1 res pin = low stby pin = high stby pin = low ssby = 0 ssby = 0, acse = 1 mstpcr = h'f[c-f]ffffff res pin = high reset state program execution state program halted state hardware standby mode sleep mode all-module-clock- stop mode software standby mode external interrupt * 3 deep software standby mode internal reset state (dpsby = 0 and no external interrupt is generated) (dpsby = 1 and no external interrupt is generated * 5 ) notes: 1. nmi, irq0 to irq15 , 8-bit timer interrupts, and watchdog timer interrupts. note that the 8-bit timer interrupt is valid when the mstpcra9 or mstpcra8 bit is cleared to 0. 2. nmi, and irq0 to irq15 . note that irq is valid only when the corresponding bit in ssier is set to 1. 3. nmi, and irq0 -a to irq3 -a. note that irq is valid only when the corresponding bit in dpsier is set to 1. 4. the slpie bit in sbycr is cleared to 0. 5. if a conflict between a transition to deep software standby mode and generation of software standby mode clearing source occurs, a mode transition may be made from software standby mode to program execution state through execution of interrupt exception handling. in this case, a transition to deep software standby mode is not made. for details, refer to section 24.12, usage notes. from any state, a transition to hardware standby mode occurs when stby is driven low. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. transition after exception handling [legend] figure 24.1 mode transitions section 24 power-down modes rev. 1.00 sep. 13, 2007 page 944 of 1102 rej09b0365-0100 24.2 register descriptions the registers related to the power-down modes are shown below. for details on the system clock control register (sckcr), refer to section 23.1.1, system clock control register (sckcr). ? standby control register (sbycr) ? module stop control register a (mstpcra) ? module stop control register b (mstpcrb) ? module stop control register c (mstpcrc) ? deep standby control register (dpsbycr) ? deep standby wait contro l register (dpswcr) ? deep standby interrupt enable register (dpsier) ? deep standby interrupt flag register (dpsifr) ? deep standby interrupt ed ge register (dpsiegr) ? reset status register (rstsr) ? deep standby backup register (dpsbkrn) 24.2.1 standby control register (sbycr) sbycr controls software standby mode. bit bit name initial value: r/w: bit bit name initial value: r/w: 15 ssby 0 r/w 14 ope 1 r/w 13 ? 0 r/w 12 sts4 0 r/w 11 sts3 1 r/w 10 sts2 1 r/w 9 sts1 1 r/w 8 sts0 1 r/w 7 slpie 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w section 24 power-down modes rev. 1.00 sep. 13, 2007 page 945 of 1102 rej09b0365-0100 bit bit name initial value r/w description 15 ssby 0 r/w software standby specifies the transition mode after executing the sleep instruction 0: shifts to sleep mode after the sleep instruction is executed 1: shifts to software standby mode after the sleep instruction is executed this bit does not change when clearing the software standby mode by using interrupts and shifting to normal operation. for clearing, write 0 to this bit. when the wdt is used in watchdog timer mode, the setting of this bit is disabled. in this case, a transition is always made to sleep mode or all-module-clock-stop mode after the sleep instruction is executed. when the slpie bit is set to 1, this bit should be cleared to 0. 14 ope 1 r/w output port enable specifies whether the output of the address bus and bus control signals ( cs0 to cs7 , as , rd , hwr , and lwr ) is retained or these lines are set to the high-z state in software standby mode or deep software standby mode. 0: in software standby mode or deep software standby mode, address bus and bus control signal lines are high-impedance. 1: in software standby mode or deep software standby mode, output states of address bus and bus control signals are retained. 13 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 946 of 1102 rej09b0365-0100 bit bit name initial value r/w description 12 11 10 9 8 sts4 sts3 sts2 sts1 sts0 0 1 1 1 1 r/w r/w r/w r/w r/w standby timer select 4 to 0 these bits select the time the mcu waits for the clock to settle when software standby mode is cleared by an external interrupt. with a cryst al resonator, refer to table 24.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. with an external clock, a pll circuit settling time is necessa ry. refer to table 24.2 to set the standby time. while oscillation is being settled, the timer is counted on the p clock frequency. careful consideration is required in multi-clock mode. 00000: reserved 00001: reserved 00010: reserved 00011: reserved 00100: reserved 00101: standby time = 64 states 00110: standby time = 512 states 00111: standby time = 1024 states 01000: standby time = 2048 states 01001: standby time = 4096 states 01010: standby time = 16384 states 01011: standby time = 32768 states 01100: standby time = 65536 states 01101: standby time = 131072 states 01110: standby time = 262144 states 01111: standby time = 524288 states 1xxxx: reserved section 24 power-down modes rev. 1.00 sep. 13, 2007 page 947 of 1102 rej09b0365-0100 bit bit name initial value r/w description 7 slpie 0 r/w sleep instructi on exception handling enable selects whether a sleep interrupt is generated or a transition to power-down mode is made when a sleep instruction is executed. 0: a transition to power-down mode is made when a sleep instruction is executed. 1: a sleep instruction exc eption handling is generated when a sleep instruction is executed. even after a sleep instruction exception handling is executed, this bit remains set to 1. for clearing, write 0 to this bit. 6 to 0 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. notes: 1. x: don't care 2. with the f-ztat version, the flash memory settling time must be reserved. 24.2.2 module stop control registers a and b (mstpcra and mstpcrb) mstpcra and mstpcrb control module stop state. setting a bit to 1 makes the corresponding module enter module stop state, while cleari ng the bit to 0 clears module stop state. ? mstpcra bit bit name initial value: r/w: bit bit name initial value: r/w: 15 acse 0 r/w 14 mstpa14 0 r/w 13 mstpa13 0 r/w 12 mstpa12 0 r/w 11 mstpa11 1 r/w 10 mstpa10 1 r/w 9 mstpa9 1 r/w 8 mstpa8 1 r/w 7 mstpa7 1 r/w 6 mstpa6 1 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w section 24 power-down modes rev. 1.00 sep. 13, 2007 page 948 of 1102 rej09b0365-0100 ? mstpcrb bit bit name initial value: r/w: bit bit name initial value: r/w: 15 mstpb15 1 r/w 14 mstpb14 1 r/w 13 mstpb13 1 r/w 12 mstpb12 1 r/w 11 mstpb11 1 r/w 10 mstpb10 1 r/w 9 mstpb9 1 r/w 8 mstpb8 1 r/w 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w 0 mstpb0 1 r/w ? mstpcra bit bit name initial value r/w module 15 acse 0 r/w all-module-clock-stop mode enable enables/disables all-module- clock-stop state for reducing current consumption by stopping the bus controller and i/o ports operations when t he cpu executes the sleep instruction after module stop state has been set for all the on-chip peripheral modules controlled by mstpcr. 0: all-module-clock-stop mode disabled 1: all-module-clock-stop mode enabled 14 mstpa14 0 r/w reserved 13 mstpa13 0 r/w dma controller (dmac) 12 mstpa12 0 r/w data transfer controller (dtc) 11 10 mstpa11 mstpa10 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 9 mstpa9 1 r/w 8-bit timer (tmr_3 and tmr_2) 8 mstpa8 1 r/w 8-bit timer (tmr_1 and tmr_0) 7 6 mstpa7 mstpa6 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 949 of 1102 rej09b0365-0100 bit bit name initial value r/w module 5 mstpa5 1 r/w d/a converter (channels 1 and 0) 4 mstpa4 1 r/w reserved this bit is always read as 1. the write value should always be 1. 3 mstpa3 1 r/w a/d converter (unit 0) 2 mstpa2 1 r/w reserved this bit is always read as 1. the write value should always be 1. 1 mstpa1 1 r/w 16-bit timer pulse unit (tpu channels 11 to 6) 0 mstpa0 1 r/w 16-bit timer pulse unit (tpu channels 5 to 0) ? mstpcrb bit bit name initial value r/w module 15 mstpb15 1 r/w programmable pulse generator (ppg_0: po15 to po0) 14 13 mstpb14 mstpb13 1 1 r/w r/w reserved these bits are always read as 1. the write value should always be 1. 12 mstpb12 1 r/w serial communications interface_4 (sci_4) 11 mstpb11 1 r/w serial communications interface_3 (sci_3) 10 mstpb10 1 r/w serial communications interface_2 (sci_2) 9 mstpb9 1 r/w serial communications interface_1 (sci_1) 8 mstpb8 1 r/w serial communications interface_0 (sci_0) 7 mstpb7 1 r/w i 2 c bus interface 2_1 (iic2_1) 6 mstpb6 1 r/w i 2 c bus interface 2_0 (iic2_0) 5 mstpb5 1 r/w user break controller (ubc) 4 3 2 1 0 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 1 1 1 1 1 r/w r/w r/w r/w r/w reserved these bits are always read as 1. the write value should always be 1. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 950 of 1102 rej09b0365-0100 24.2.3 module stop cont rol register c (mstpcrc) when bits mstpc7 to mstpc0 are set to 1, the corresponding on-chip ram stops. do not set the corresponding mstpc7 to mstpc0 bits to 1 while accessing the on-chip ram. do not access the on-chip ram while bits ms tpc7 to mstpc0 are set to 1. the serial communications interfaces, 8-bit timers, i 2 c bus interfaces 2_3 and 2_2 (iic2_3/ iic2_2), crc calculator, a/d converter, and programmable pulse generator (ppg: po31 to po16) are placed in the module stop state by using the mstpc15 and mstpc14, mstpc13 and mstpc12, mstpc11, mstpc10, mstpc9, and mstpc8 bits, respectively. bit bit name initial value: r/w: bit bit name initial value: r/w: 15 mstpc15 1 r/w 14 mstpc14 1 r/w 13 mstpc13 1 r/w 12 mstpc12 1 r/w 11 mstpc11 1 r/w 10 mstpc10 1 r/w 9 mstpc9 1 r/w 8 mstpc8 1 r/w 7 mstpc7 0 r/w 6 mstpc6 0 r/w 5 mstpc5 0 r/w 4 mstpc4 0 r/w 3 mstpc3 0 r/w 2 mstpc2 0 r/w 1 mstpc1 0 r/w 0 mstpc0 0 r/w bit bit name initial value r/w module 15 mstpc15 1 r/w serial communicat ions interface_5 (sci_5), (irda) 14 mstpc14 1 r/w serial communications interface_6 (sci_6) 13 mstpc13 1 r/w 8-bit timer (tmr_4, tmr_5) 12 mstpc12 1 r/w 8-bit timer (tmr_6, tmr_7) 11 mstpc11 1 r/w i 2 c bus interfaces 2_3 and 2_2 (iic2_3/ iic2_2) 10 mstpc10 1 r/w cyclic redundancy check calculator 9 mstpc9 1 r/w a/d converter (unit 2/1) 8 mstpc8 1 r/w programmable pulse generator (ppg_1: po31 to po16) section 24 power-down modes rev. 1.00 sep. 13, 2007 page 951 of 1102 rej09b0365-0100 bit bit name initial value r/w module 7 6 mstpc7 mstpc6 0 0 r/w r/w with 56 kbytes of on-chip ram: on-chip ram 6 (h'fee000 to h'feffff) with 40 kbytes of on-chip ram: reserved always set the mstpc7 and mstpc6 bits to the same value. 5 4 mstpc5 mstpc4 0 0 r/w r/w with 56 kbytes of on-chip ram: on-chip ram 5, 4 (h'ff0000 to h'ff3fff) with 40 kbytes of on-chip ram: on-chip ram 4 (h'ff2000 to h'ff3fff) always set the mstpc5 and mstpc4 bits to the same value. 3 2 mstpc3 mstpc2 0 0 r/w r/w on-chip ram_3, 2 (h'ff4000 to h'ff7fff) always set the mstpc3 and mstpc2 bits to the same value. 1 0 mstpc1 mstpc0 0 0 r/w r/w on-chip ram_1, 0 (h'ff8000 to h'ffbfff) always set the mstpc1 and mstpc0 bits to the same value. 24.2.4 deep standby co ntrol register (dpsbycr) dpsbycr controls deep software standby mode. dpsbycr is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dpsby 0 r/w 6 iokeep 0 r/w 5 ramcut2 0 r/w 4 ramcut1 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ramcut0 1 r/w section 24 power-down modes rev. 1.00 sep. 13, 2007 page 952 of 1102 rej09b0365-0100 bit bit name initial value r/w module 7 dpsby 0 r/w deep software standby when the ssby bit in sbycr has been set to 1, executing the sleep instructi on causes a transition to software standby mode. at this time, if there is no source to clear software standby mode and this bit is set to 1, a transition to deep software standby mode is made. ssby dpsby entry to 0 x enters sleep mode after execution of a sleep instruction. 1 0 enters software standby mode after execution of a sleep instruction. 1 1 enters deep software standby mode after execution of a sleep instruction. when deep software standby mode is canceled due to an external interrupt, th is bit remains at 1. write a 0 here to clear it. setting of this bit has no effect when the wdt is used in watchdog timer mode. in this case, executing the sleep instruction always initiates entry to sleep mode or all-module-clock-stop mode. be sure to clear this bit to 0 when setting the slpie bit to 1. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 953 of 1102 rej09b0365-0100 bit bit name initial value r/w module 6 iokeep 0 r/w i/o port retention in deep software standby mode, the ports retain the states that were held in software standby mode. this bit specifies whether or not the state that has been held in deep software standby mode is retained after exit from deep software standby mode. iokeep pin state 0 the retained port states are released simultaneously with exit from deep software standby mode. 1 the retained port states are released when a 0 is written to this bit following exit from deep software standby mode. in operation in external extended mode, however, the address bus, bus control signals ( cs0 , as , rd , hwr , and lwr ), and data bus are set to the initial state upon exit from deep software standby mode. 5 ramcut2 0 r/w on-chip ram power off 2 controls the internal power supply to the on-chip ram in deep software standby mode. for details, see descriptions of the ramcut0 bit. 4 ramcut1 0 r/w on-chip ram power off 1 controls the internal power supply to the on-chip ram in deep software standby mode. for details, see descriptions of the ramcut0 bit. 3 to 1 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 0 ramcut0 1 r/w on-chip ram power off 0 controls the internal power supply to the on-chip ram in deep software standby mode, in combination with ramcut2 and ramcut 1. 000: power is supplied to the on-chip ram. 111: power is not supplied to the on-chip ram. settings other than above are prohibited. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 954 of 1102 rej09b0365-0100 24.2.5 deep standby wait control register (dpswcr) dpswcr selects the time for which the mcu waits until the clock settles when deep software standby mode is canceled by an external interrupt. dpswcr is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 ? 0 r/w 6 ? 0 r/w 5 wtsts5 0 r/w 4 wtsts4 0 r/w 3 wtsts3 0 r/w 2 wtsts2 0 r/w 1 wtsts1 0 r/w 0 wtsts0 0 r/w bit bit name initial value r/w module 7, 6 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 955 of 1102 rej09b0365-0100 bit bit name initial value r/w module 5 to 0 wtsts [5:0] 0 r/w deep software standby wait time setting these bits select the time for which the mcu waits until the clock settles when deep software standby mode is canceled by an external interrupt. when using a crystal resonator, see table 24.3 and select the wait time greater than the oscillation settling time for each operating frequency. when using an external clock, settling time for the pll circuit should be considered. see table 24.3 to select the wait time. during the oscillation settling period, counting is performed with the clock frequency input to the extal. 000000: reserved 000001: reserved 000010: reserved 000011: reserved 000100: reserved 000101: wait time = 64 states 000110: wait time = 512 states 000111: wait time = 1024 states 001000: wait time = 2048 states 001001: wait time = 4096 states 001010: wait time = 16384 states 001011: wait time = 32768 states 001100: wait time = 65536 states 001101: wait time = 131072 states 001110: wait time = 262144 states 001111: wait time = 524288 states 01xxxx: reserved section 24 power-down modes rev. 1.00 sep. 13, 2007 page 956 of 1102 rej09b0365-0100 24.2.6 deep standby interrup t enable register (dpsier) dpsier enables or disables interrupts to clear deep software standby mode. dpsier is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 dirq3e 0 r/w 2 dirq2e 0 r/w 1 dirq1e 0 r/w 0 dirq0e 0 r/w bit bit name initial value r/w module 7 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 6 to 4 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 3 dirq3e 0 r/w irq3 interrupt enable enables or disables exit from deep software standby mode by irq3. 0: disables exit from deep software standby mode by irq3. 1: enables exit from deep software standby mode by irq3 . section 24 power-down modes rev. 1.00 sep. 13, 2007 page 957 of 1102 rej09b0365-0100 bit bit name initial value r/w module 2 dirq2e 0 r/w irq2 interrupt enable enables or disables exit from deep software standby mode by irq2. 0: disables exit from deep software standby mode by irq2. 1: enables exit from deep software standby mode by irq2 . 1 dirq1e 0 r/w irq1 interrupt enable enables or disables exit from deep software standby mode by irq1. 0: disables exit from deep software standby mode by irq1. 1: enables exit from deep software standby mode by irq1 . 0 dirq0e 0 r/w irq0 interrupt enable enables or disables exit from deep software standby mode by irq0. 0: disables exit from deep software standby mode by irq0. 1: enables exit from deep software standby mode by irq0. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 958 of 1102 rej09b0365-0100 24.2.7 deep standby interr upt flag register (dpsifr) dpsifr is used to request an exit from deep so ftware standby mode. when the interrupt specified in dpsiegr is generated, the applicable bit in dpsifr is set to 1. the bit is set to 1 even when an interrupt is generated in the modes other than deep software standby. therefore, a transition to deep software standby should be made after this regi ster bits are cleared to 0. dpsifr is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dnmif 0 r/(w) * 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 dirq3f 0 r/(w) * 2 dirq2f 0 r/(w) * 1 dirq1f 0 r/(w) * 0 dirq0f 0 r/(w) * note: * only 0 can be written to clear the flag. bit bit name initial value r/w module 7 dnmif 0 r/(w) * nmi flag [setting condition] nmi input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 6 to 4 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 959 of 1102 rej09b0365-0100 bit bit name initial value r/w module 3 dirq3f 0 r/(w) * irq3 interrupt flag [setting condition] irq3 input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 2 dirq2f 0 r/(w) * irq2 interrupt flag [setting condition] irq2 input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 1 dirq1f 0 r/(w) * irq1 interrupt flag [setting condition] * irq1 input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. 0 dirq0f 0 r/(w) * irq0 interrupt flag [setting condition] * irq0 input specified in dpsiegr is generated. [clearing condition] writing a 0 to this bit after reading it as 1. note: * only 0 can be written to clear the flag. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 960 of 1102 rej09b0365-0100 24.2.8 deep standby interr upt edge register (dpsiegr) dpsiegr selects the rising or falling edge to clear deep software standby mode. dpsiegr is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dnmieg 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 dirq3eg 0 r/w 2 dirq2eg 0 r/w 1 dirq1eg 0 r/w 0 dirq0eg 0 r/w bit bit name initial value r/w module 7 dnmieg 0 r/w nmi edge select selects the active edge for nmi pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 6 to 4 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 3 dirq3eg 0 r/w irq3 interrupt edge select selects the active edge for irq3 pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 2 dirq2eg 0 r/w irq2 interrupt edge select selects the active edge for irq2 pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 961 of 1102 rej09b0365-0100 bit bit name initial value r/w module 1 dirq1eg 0 r/w irq1 interrupt edge select selects the active edge for irq1 pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 0 dirq0eg 0 r/w irq0 interrupt edge select selects the active edge for irq0 pin input. 0: the interrupt request is generated by a falling edge. 1: the interrupt request is generated by a rising edge. 24.2.9 reset status register (rstsr) the dpsrstf bit in rstsr indicates that deep software standby mo de has been canceled by an interrupt. rstsr is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. bit bit name initial value: r/w: 7 dpsrstf 0 r/(w) * 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w 0 ? 0 r/w note: * only 0 can be written to clear the flag. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 962 of 1102 rej09b0365-0100 bit bit name initial value r/w module 7 dpsrstf 0 r/(w) * deep software standby reset flag indicates that deep software standby mode has been canceled by an external interrupt source specified in dpsier or dpsiegr and an internal reset is generated. [setting condition] deep software standby mode is canceled by an external interrupt source. [clearing condition] writing a 0 to this bit after reading it as 1. 6 to 0 ? 0 r/w reserved these bits are always read as 0. the write value should always be 0. note: * only 0 can be written to clear the flag. 24.2.10 deep standby ba ckup register (dpsbkrn) dpsbkrn (n = 15 to 0) is a 16-bit readable/writabl e register to store data during deep software standby mode. although data in on-chip ram is not retained in de ep software standby mode, data in this register is retained. dpsbkrn is initialized by input of the reset signal on the res pin, but is not initialized by the internal reset signal upon exit from deep software standby mode. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 963 of 1102 rej09b0365-0100 24.3 multi-clock function when bits ick2 to ick0, pck2 to pck0, and bck2 to bck0 in sckcr are set, the clock frequency is changed at the end of the bus cy cle. the cpu and bus ma sters operate on the operating clock specified by bits ick2 to ick0. the peripheral modules op erate on the operating clock specified by bits pck2 to pck0. the extern al bus operates on the operating clock specified by bits bck2 to bck0. even if the frequencies specified by bits pck2 to pck0 and bck2 to bck0 are higher than the frequency specified by bits ick2 to ick0, the specified values are not reflected in the peripheral module and external bus clocks. the peripheral module and external bus clocks are restricted to the operating clock specified by bits ick2 to ick0. 24.4 module stop state module stop functionality can be set for individual on-chip peripheral modules. when the corresponding mstp bit in mstpcra , mstpcrb, or mstpcrc is set to 1, module operation stops at the end of the bus cycle and a transition is made to a module stop state. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, a module stop state is cleared and the module starts operating at the end of the bus cycle. in a module stop state, the internal states of modules other than the sci are retained. after the reset state is cleared, all modules ot her than the dmac, dtc, and on-chip ram are placed in a module stop state. the registers of the module for which the module stop state is selected cannot be read from or written to. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 964 of 1102 rej09b0365-0100 24.5 sleep mode 24.5.1 entry to sleep mode when the sleep instruction is executed when th e ssby bit in sbycr is 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpu's internal registers are retained. other peripheral functions do not stop. 24.5.2 exit from sleep mode sleep mode is exited by any interrupt, signals on the res or stby pin, and a reset caused by a watchdog timer overflow. ? exit from sleep mode by interrupt when an interrupt occurs, sleep mode is exited and interrupt exception pr ocessing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. ? exit from sleep mode by res pin setting the res pin level low selects the reset state. after the stipulated reset input duration, driving the res pin high makes the cpu start the reset exception processing. ? exit from sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. ? exit from sleep mode by reset caused by watchdog timer overflow sleep mode is exited by an internal re set caused by a watchdog timer overflow. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 965 of 1102 rej09b0365-0100 24.6 all-module-clock-stop mode when the acse bit is set to 1 and all mo dules controlled by mstpcra and mstpcrb are stopped (mstpcra, mstpcrb = h'ff ffffff), or all modules except for the 8-bit timer (units 0 and 1) are stopped (mstpcra, mstpcrb = h'f[c to f]ffffff), executing a sleep instruction with the ssby bit in sbycr cleared to 0 will cause all modules (except for the 8-bit timer* and watchdog timer), the bus controller, and the i/o ports to stop operating, and to make a transition to all-module-clock-stop mode at the end of the bus cycle. when power consumption should be reduced ever more in all-module-clock-stop mode, stop modules controlled by mstp crc (mstpcrc[15:8] = h'ffff). all-module-clock-stop mode is cleared by an external interrupt (nmi or irq0 to irq15 pins), res pin input, or an internal interrupt (8-bit timer* or watchdog timer), and the cpu returns to the normal program execution state via the exception handling state. all-module-clock-stop mode is not cleared if interrupts are disabled, if interrupts other than nmi are masked on the cpu side, or if the relevant interrupt is designated as a dtc activation source. when the stby pin is driven low, a transition is made to hardware standby mode. note: * operation or halting of the 8-bit timer ca n be selected by bits mstpa9 and mstpa8 in mstpcra. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 966 of 1102 rej09b0365-0100 24.7 software standby mode 24.7.1 entry to software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1 and the dpsby bit in dpsbycr is cleared to 0, software standby mode is entered. in this mode, the cpu, on-chip peripheral functions, and oscillator all stop. however, the contents of the cpu's internal registers, on-chip ram data, and the states of on-chip peripheral functions other than the sci, and the states of the i/o ports, are retained. whether the addr ess bus and bus control si gnals are placed in the high-impedance state or retain th e output state can be specified by the ope bit in sbycr. in this mode the oscillator stops, allowing power consumption to be significantly reduced. if the wdt is used in watchdog timer mode, it is impossible to make a transition to software standby mode. the wdt should be stopped before the sleep instruction execution. 24.7.2 exit from software standby mode software standby mode is cleared by an external interrupt (nmi, or irq0 to irq15 *) or by means of the res pin or stby pin. 1. exit from software standby mode by interrupt when an nmi, or irq0 to irq15* interrupt re quest signal is input, clock oscillation starts, and after the elapse of the time set in bits sts4 to sts0 in sbycr, stable clocks are supplied to the entire lsi, software standby mode is clear ed, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq11* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq11* is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. note: * by setting the ssin bit in ssier to 1, irq0 to irq15 can be used as a software standby mode clearing source. 2. exit from software standby mode by res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire lsi. note that the res pin must be held low until clock oscillation settles. when the res pin goes high, the cpu begins reset exception handling. 3. exit from software standby mode by stby pin when the stby pin is driven low, a transition is made to hardware standby mode. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 967 of 1102 rej09b0365-0100 24.7.3 setting oscillation settling time after exit from software standby mode bits sts4 to sts0 in sbycr should be set as described below. 1. using a crystal resonator set bits sts4 to sts0 so that the standby time is at least equal to the oscillation settling time. table 24.2 shows the standby times for operating frequencies and settings of bits sts4 to sts0. 2. using an external clock a pll circuit settling time is necessary. refer to table 24.2 to set the standby time. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 968 of 1102 rej09b0365-0100 table 24.2 oscillation settling time setting p * (mhz) sts4 sts3 sts2 sts1 sts0 standby time 35 25 20 13 10 8 unit 0 reserved ? ? ? ? ? ? 0 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 64 1.8 2.6 3. 2 4.9 6.4 8.0 0 512 14.6 20.5 25. 6 39.4 51.2 64.0 0 1 1 1 1024 29.3 41.0 51. 2 78.8 102.4 128.0 0 2048 58.5 81.9 102. 4 157.5 204.8 256.0 s 0 1 4096 0.12 0.16 0. 20 0.32 0.41 0.51 0 16384 0.47 0.66 0.82 1.26 1.64 2.05 0 1 1 32768 0.94 1.31 1.64 2.52 3.28 4.10 0 65536 1.87 2.62 3.28 5.04 6.55 8.19 0 1 131072 3.74 5.24 6.55 10.08 13.11 16.38 0 262144 7.49 10.49 13.11 20.16 26.21 32.77 0 1 1 1 1 524288 14.98 20.97 26.21 40.33 52.43 65.54 1 0 0 0 0 reserved ? ? ? ? ? ? ms [legend] : recommended setting when external clock is in use : recommended setting when crystal oscillator is in use note: * p is the output from the peripheral module frequency divider. the oscillation settling time, which includes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. the above figures are for reference. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 969 of 1102 rej09b0365-0100 24.7.4 software standby mode application example figure 24.2 shows an example in which a transiti on is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interr upt is accepted with the nmieg bit in intcr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, cau sing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. oscillator i nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation settling time t osc2 nmi exception handling figure 24.2 software standby mode application example section 24 power-down modes rev. 1.00 sep. 13, 2007 page 970 of 1102 rej09b0365-0100 24.8 deep software standby mode 24.8.1 entry to deep software standby mode if a sleep instruction is executed when the ssby bit in sbycr has been set to 1, a transition to software standby mode is made. in this state, if the dpsby bit in dpsbycr is set to 1, a transition to deep software standby mode is made. if a software standby mode clearing source (an nmi, or irq0 to irq15) occu rs when a transition to software standby mode is made, software standby mode will be cleared regardless of the dpsby bit setting, and the interrupt exception handling starts after the oscillation settling time for software standby mode specified by the b its sts4 to sts0 in sbycr has elapsed. when both of the ssby bit in sbycr and the dpsby bit in dpsbycr are set to 1 and no software standby mode clearing source occurs, a transition to deep software standby mode will be made immediately after software standby mode is entered. in deep software standby mode, the cpu, on-chip peripheral functions, on-chip rams 6 to 4, and oscillator functionality are all halted. in addition, the internal power supply to these modules stops, resulting in a significant reduction in power consumption. at this time, the contents of all the registers of the cpu, on-chip peripheral functions, and on-chip rams 6 to 4 become undefined. contents of the on-chip rams 3 to 0 can be retained when all the bits ramcut2 to ramcut0 in dpsbycr have been cleared to 0. if these bits are set to all 1, the internal power supply to the on-chip rams 3 to 0 stops and the power consumption is further reduced. at this time, the contents of the on-chip rams 3 to 0 become undefined. the i/o ports can be retained in the sa me state as in soft ware standby mode. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 971 of 1102 rej09b0365-0100 24.8.2 exit from deep software standby mode exit from deep software standby mode is initiated by signals on the external interrupt pins (nmi and irq0 -a to irq3 -a), res pin, or stby pin. 1. exit from deep software standby mode by external interrupt pins deep software standby mode is canceled when any of the dnmif and dirqnf (n = 3 to 0) bits in dpsifr is set to 1. the dnmif or dirqnf (n = 3 to 0) bit is set to 1 when a specified edge is generated in the nmi or irq0 -a to irq3 -a pins, that has been enabled by the dirqne (n = 3 to 0) bit in dpsier. the rising or falling edge of the signals can be specified with dpsiegr. when deep software standby mode clearing source is generated, internal power supply starts simultaneously with the start of clock oscillation, and internal reset signal is generated for the entire lsi. once the time specified by the wtst s5 to wtsts0 bits in dpswcr has elapsed, a stable clock signal is being supplied throughout the lsi and the internal reset is cleared. deep software standby mode is canceled on clear ing of the internal reset, and then the reset exception handling starts. when deep software standby mode is canceled by an external interrupt pin, the dpsrstf bit in rstsr is set to 1. 2. exit from deep software standby mode by the signal on the res pin clock oscillation and internal power supply start as soon as the signal on the res pin is driven low. at the same time, clock signals are supplied to the lsi. in this case, the res pin has to be held low until the clock oscillation has become stable. once the signal on the res pin is driven high, the cpu starts reset exception handling. 3. exit from deep software standby mode by the signal on the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 972 of 1102 rej09b0365-0100 24.8.3 pin state on exit from deep software standby mode in deep software standby mode, the ports retain th e states that were held during software standby mode. the internal of the lsi is initialized by an internal reset caused by deep software standby mode, and the reset exception handling starts as soon as deep software standby mode is canceled. the following shows the port states at this time. (1) pins for address bus, bus control and data bus pins for the address bus, bus control signals ( cs0 , as , hwr and lwr ), and data bus operate depending on the cpu. (2) pins other than address bus, bus control and data bus pins whether the ports are initialized or retain the states that were held during software standby mode can be selected by the iokeep bit. ? when iokeep = 0 ports are initialized by an internal rese t caused by deep software standby mode. ? when iokeep = 1 the port states that were held in deep software standby mode are retained regardless of the lsi internal state though the internal of the lsi is initialized by an internal reset caused by deep software standby mode. at this time, the port st ates that were held in software standby mode are retained even if settings of i/o ports or peripheral modules are set. subsequently, the retained port states are released when the iokeep bit is cleared to 0 and operation is performed according to the internal settings. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 973 of 1102 rej09b0365-0100 24.8.4 b operation after exit from deep software standby mode when the iokeep bit is 0, b output is undefined for a maximum of one cycle immediately after exit from deep software standby mode. at this time, the output state cannot be guaranteed. even when the iokeep bit is set to 1, b output is undefined for a maximum of one cycle immediately after the iokeep bit is cleared to 0 after de ep software standby mode was canceled, and the output state cannot be guaranteed. (see figure 24.3) however, clock can be normally output by canceling deep software standby mode with the iokeep bit set to 1 and then controlling the b output with the iokeep and pstop1 bits. use the following procedure. 1. change the value of the pstop1 bit from 0 to 1 to fix the b output at the high level (given that the b output was already fixed high). 2. clear the iokeep bit to 0 to end retention of the b state. 3. clear the pstop1 bit to 0 to enable b output. for the port state when the iokeep bit is set to 1, see section 24.8.3, pin state on exit from deep software standby mode. deep software standby mode oscillator nmi internal reset i clock is undefined iokeep cleared pstop1 set iokeep cleared pstop1 cleared when iokeep = 1, the clock can be normally output by using the pstop1 bit. b when iokeep = 0 when iokeep = 1 (iokeep=1) b (1) b output cannot be guaranteed. (2) the procedure to guarantee b output is used. figure 24.3 b operation after exit from deep software standby mode section 24 power-down modes rev. 1.00 sep. 13, 2007 page 974 of 1102 rej09b0365-0100 24.8.5 setting oscillation settling time aft er exit from deep so ftware standby mode the wtsts5 to wtsts0 bits in dpswcr should be set as follows: 1. using a crystal resonator specify the wtsts5 to wtsts0 bits so that the standby time is at least equal to the oscillation settling time. table 24.3 shows extal input clock frequencies and the standby time according to wtsts5 to wtsts0 settings. 2. using an external clock the pll circuit settling time should be considered. see table 24.3 to set the standby time. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 975 of 1102 rej09b0365-0100 table 24.3 oscillation settling time settings extal input clock frequency * (mhz) wt sts5 wt sts4 wt sts3 wt sts2 wt sts1 wt sts0 standby time 18 16 14 12 10 8 unit 0 reserved ? ? ? ? ? ? 0 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 1 reserved ? ? ? ? ? ? 0 reserved ? ? ? ? ? ? 0 1 64 3.6 4.0 4. 6 5.3 6.4 8.0 0 512 28.4 32.0 36. 6 42.7 51.2 64.0 0 1 1 1 1024 56.9 64.0 73.1 85.3 102.4 128.0 0 2048 113.8 128.0 146.3 170.7 204.8 256.0 s 0 1 4096 0.23 0.26 0. 29 0.34 0.41 0.51 0 16384 0.91 1.02 1.17 1.37 1.64 2.05 0 1 1 32768 1.82 2.05 2. 34 2.73 3.28 4.10 0 65536 3.64 4.10 4.68 5.46 6.55 8.19 0 1 131072 7.28 8.19 9.36 10.92 13.11 16.38 0 262144 14.56 16.38 18.72 21.85 26.21 32.77 0 1 1 1 1 524288 29.13 32.77 37.45 43.69 52.43 65.54 0 1 0 0 0 0 reserved ? ? ? ? ? ? ms [legend] : recommended setting when external clock is in use : recommended setting when crystal oscillator is in use note: * the oscillation settling time, which incl udes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. the above figures are for reference. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 976 of 1102 rej09b0365-0100 24.8.6 deep software standb y mode application example (1) transition to and exit from deep software standby mode figure 24.4 shows an example where the transition to deep software standby mode is initiated by a falling edge on the nmi pin and exit from deep software standby mode is initiated by a rising edge on the nmi pin. in this example, falling-edge sensing of nmi interrupts has been specified by clearing the nmieg bit in intcr to 0 (not shown). after an nmi interrupt has been sensed, rising-edge sensing is specified by setting the dnmieg bit to 1, the ssby and dpsby bits are set to 1, and the transition to deep software standby mode is triggered by execution of a sleep instruction. after that, deep software standby mode is ca nceled at the rising edge on the nmi pin. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 977 of 1102 rej09b0365-0100 oscillator i nmi dnmieg bit dpsby bit nmi exception handling dnmieg = 1 ssby = 1 dpsby = 1 sleep instruction deep software standby mode (power-down mode) reset exception handling internal reset oscillation settling time iokeep bit dpsrstf flag operated retained operated i/o port cleared cleared cleared set nmi interrupt set dnmi interrupt becomes invalid by an internal reset set set set figure 24.4 deep software standby mode application example (iokeep = 1) section 24 power-down modes rev. 1.00 sep. 13, 2007 page 978 of 1102 rej09b0365-0100 (2) deep software standby mode in ex ternal extended mode (iokeep = 1) figure 24.5 shows an example of operations in deep standby mode when the iokeep and ope bits are set to 1 in external extended mode. in this example, deep software standby mode is entered with the iokeep and ope bits set to 1, and then exited at the rising edge of the nmi pi n. in external extended mode, while the iokeep bit is set to 1, retention of the states of pins for the address bus, bus-control signals ( cs0 , as , rd , hwr , and lwr ), data bus is released after the oscillation settling time has elapsed. for other pins, including the b output pin, retention is released when the iokeep bit is cleared to 0, and then they are set according to the i/ o port or peripher al module settings. oscillator i nmi sleep instruction deep software standby mode (power-down mode) program execution state program execution state reset exception handling oscillation settling time internal reset operated retained address retained bus control retained data b retained pstop1 set pstop1 cleared iokeep cleared retained i/o other than above started from h'00000 operated operated operated operated operated figure 24.5 example of deep so ftware standby mode operation in external extended mode (iokeep = ope = 1) section 24 power-down modes rev. 1.00 sep. 13, 2007 page 979 of 1102 rej09b0365-0100 (3) deep software standby mode in ex ternal extended mode (iokeep = 0) figure 24.6 shows an example of operations in deep software standby mode with the iokeep bit is cleared to 0 and the ope bit is set to 1 in external extended mode. when the iokeep bit is cleared to 0, retention of the states of pins including the address bus, bus-control signals ( cs0 , as , rd , hwr , and lwr ), data bus, and other pins including b output is released after the oscillation settling time has elapsed. sleep instruction deep software standby mode (power-down mode) program execution state program execution state reset exception handling oscillator i nmi internal reset operated retained address retained bus control retained data b retained retained i/o other than above started from h'00000 operated operated operated operated operated oscillation settling time figure 24.6 example of deep so ftware standby mode operation in external extended mode (iokeep = 0, ope = 1) section 24 power-down modes rev. 1.00 sep. 13, 2007 page 980 of 1102 rej09b0365-0100 24.8.7 flowchart of deep software standby mode operation figure 24.7 shows an example of flowchart of deep software standby mode operation. in this example, reading the dpsrst f bit determines whether a reset was generated by the res pin or exit from deep software standby mode, after the reset exception handling was performed. when a reset was caused by the res pin, deep software standby mode is entered after required register settings. when a reset was caused by exit from deep software standby mode, the iokeep bit is cleared after the i/o ports setting. when the iokeep bit is cleared, the setting to avoid an undefined state in b output is also set. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 981 of 1102 rej09b0365-0100 clear a reset by res set oscillation setting time no yes select deep software standby mode set pin state in deep software standby mode and after exit from deep software standby mode set deep software standby mode clearing interrupt an interrupt is generated by exit from deep software standby mode. identify deep software standby mode clearing source (1) set pin state after clearing iokeep to 0 releases pin states that were retained during deep software standby mode start b output reset exception handling read dpsifr set pnddr,pndr set sckcr.pstop1 to 1 set dpsbycr.iokeep to 0 set sckcr.pstop1 to 0 execute a program corresponding to the clearing source that was identified in (1) program start set dpswcr.wtsts5-0 set sbycr.ssby to 1 dpsbycr.dpsby to 1 dpsbycr.ramcut2-0 set pnddr,pndr set sbycr.ope set dpsbycr.iokeep to 1 set dpsiegr set dpsier clear dpsifr execute sleep instruction deep software standby mode rstsr. dpsrstf = 0 figure 24.7 flowchart of deep software standby mode operation section 24 power-down modes rev. 1.00 sep. 13, 2007 page 982 of 1102 rej09b0365-0100 24.9 hardware standby mode 24.9.1 transition to hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. data in the on-chip ram is not retained because the internal power supply to the on-chip ram stops. i/o ports are set to the high-impedance state. do not change the states of mode pins (md2 to md0) while this lsi is in hardware standby mode. 24.9.2 clearing ha rdware standby mode hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is entered and clock oscillation is started. ensure that the res pin is held low until clock oscillation settles (for details on the oscillation settling time, refer to table 24.2). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 24.9.3 hardware standby mode timing figure 24.8 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation settling time, then changing the res pin from low to high. oscillator res stby oscillation settling time reset exception handling figure 24.8 hardware standby mode timing section 24 power-down modes rev. 1.00 sep. 13, 2007 page 983 of 1102 rej09b0365-0100 24.9.4 timing sequence at power-on figure 24.9 shows the timing sequence at power-on. at power-on, the res pin must be driven low with the stby pin driven high for a given time in order to clear the reset state. to enter hardware standby mode immediately after power-on, drive the stby pin low after exiting the reset state. for details on clearing hardware standby mode, see section 24.9.3, hardware standby mode timing. res stby power supply reset state hardware standby mode 1 2 2 figure 24.9 timing sequence at power-on section 24 power-down modes rev. 1.00 sep. 13, 2007 page 984 of 1102 rej09b0365-0100 24.10 sleep instruction exception handling sleep instruction exception handling is the ex ception handling initiated by the execution of a sleep instruction. sleep instru ction exception handling is alwa ys accepted while the program is in execution. when the slpie bit is set to 0, the execution of a sleep instruction does not initiate sleep instruction exception handling. instead, the cpu enters the power-down state. after this, generation of an exception handling request th at cancels the power-down state causes the powerdown state to be canceled, after which the cpu starts to handle the exception. when the slpie bit is set to 1, sleep instruction excepti on handling starts after the execution of a sleep instruction. transitions to the power-down state are inhibited when sleep instruction exception handling is initiated, and the cpu immediately starts sleep instruction exception handling. when a sleep instruction is executed while the slpi e bit is cleared to 0, a transition is made to the power-down state. the power- down state is canceled by a cancel ing factor interrupt (see figure 24.10). when a canceling factor interrupt is generated immediately before the execution of a sleep instruction, exception handling for the interrupt st arts. when execution retu rns from the exception service routine, the sleep instruction is executed to enter the power-down state. in this case, the power-down state is not canceled until the next can celing factor interrupt is generated (see figure 24.11). when the slpie bit is set to 1 in the service routine for a canceling factor interrupt so that the execution of a sleep instruction will produce sleep instruction exception handling, the operation of the system is as shown in figure 24.12. even if a canceling factor interrupt is generated immediately before the sleep instruction is ex ecuted, sleep instructio n exception handling is initiated by execution of the sleep instruction. therefore, the cpu executes the instruction that follows the sleep instruction af ter sleep instruction exception and exception service routine without shifting to the power-down state. when the slpie bit is set to 1 to start sleep exception handling, clear the ssby bit in sbycr to 0. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 985 of 1102 rej09b0365-0100 slpie = 0 yes no instruction before sleep instruction instruction after sleep instruction sleep instruction executed (slpie = 0) canceling factor interrupt transition by interrupt exception handling interrupt handling routine rte instruction executed power-down state figure 24.10 when canceling factor interrupt is generated after sleep instruction execution slpie = 0 yes no instruction before sleep instruction instruction after sleep instruction sleep instruction executed (slpie = 0) canceling factor interrupt canceling factor interrupt transition by interrupt exception handling return from the power- down state after the next canceling factor interrupt is generated interrupt handling routine rte instruction executed power-down state yes no transition by interrupt exception handling interrupt handling routine rte instruction executed figure 24.11 when canceling factor interrupt is generated before sleep instruction execution (sleep instruction exceptio n handling not initiated) section 24 power-down modes rev. 1.00 sep. 13, 2007 page 986 of 1102 rej09b0365-0100 slpie = 0 slpie = 1 ssby = 0 instruction before sleep instruction instruction after sleep instruction sleep instruction executed (slpie = 1) sleep instruction exceotion handling canceling factor interrupt transition by interrupt exception handling vector number 18 exception service routine rte instruction executed yes no transition by interrupt exception handling interrupt handling routine rte instruction executed figure 24.12 when canceling factor interrupt is generated before sleep instruction execution (sleep inst ruction exception handling initiated) section 24 power-down modes rev. 1.00 sep. 13, 2007 page 987 of 1102 rej09b0365-0100 24.11 | clock output control output of the b clock can be controlled by the psto p1 bit in sckcr, and ddr for the corresponding pa7 pin. clearing the pstop1 bit to 0 enables the b clock output on the pa7 pin. when bit pstop1 is set to 1, the b clock output stops at the en d of the bus cycle, and the b clock output goes high. when ddr for the pa7 pin is cleared to 0, the b clock output is disabled and the pin becomes an input port. tables 24.4 shows the states of the b pin in each processing state. table 24.4 pin (pa7) state in each processing state register setting value software standby mode deep software standby mode ddr pstop1 normal operating mode sleep mode all-module- clock-stop mode ope = 0 ope = 1 iokeep = 0 iokeep = 1 hardware standby mode 0 x hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z 1 0 b output b output b output high high high high hi-z 1 1 high high high high high high high hi-z [legend] x = don't care section 24 power-down modes rev. 1.00 sep. 13, 2007 page 988 of 1102 rej09b0365-0100 24.12 usage notes 24.12.1 i/o port status in software standby mode or deep software st andby mode, the i/o port states are retained. therefore, there is no reduction in current drawn due to output currents when high-level signals are being output. 24.12.2 current consumptio n during oscillation sett ling standby period current consumption increases during the oscillation settling standby period. 24.12.3 module stop state of dmac or dtc depending on the operating state of the dmac and dtc, bits mstpa13 and mstpa12 may not be set to 1, respectively. the module stop state setting for the dmac or dtc should be carried out only when the dmac or dtc is not activated. for details, refer to section 9, dma controller (d mac), and section 10, data transfer controller (dtc). 24.12.4 on-chip peripheral module interrupts relevant interrupt operations cannot be performed in a module stop state. consequently, if module stop state is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dmac or dtc activation source. interrupts should therefore be disabled before entering a module stop state. 24.12.5 writing to mstpcra, mstpcrb, and mstpcrc mstpcra, mstpcrb, and mstpcrc should onl y be written to by the cpu. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 989 of 1102 rej09b0365-0100 24.12.6 control of input buffers by dirqne (n = 3 to 0) when the input buffers for the p10/ irq0 -a to p13/ irq3 -a pins are enabled by setting the dirqne bits (n = 3 to 0) in dspier to 1, the pnicr settings corresponding to these pins are invalid. therefore, note that external inputs to these pins, of which stat es are reflected on the dirqnf bits, are also input to the interrupt contro ller, peripheral modules and i/o ports, after the dirqne bits (n = 3 to 0) are set to 1 24.12.7 input buffer control by dirqne (n = 3 to 0) if a conflict between a transition to deep software standby mode and generation of software standby mode clearing source occurs, a transition to deep software standby mode is not made but the software standby mode clearing sequence is ex ecuted. in this case, an interrupt exception handling for the input interrupt starts after the oscillation settling time for software standby mode (set by the sts4 to sts0 b its in sbycr) has elapsed. note that if a conflict between a deep software standby mode transition and nmi interrupt occurs, the nmi interrupt exception ha ndling routine is required. if a conflict between a deep software standby mode transition and irq0 to irq15 interrupts occurs, a transition to deep software standby mode can be made without executing the interrupt execution handling by clearing the ssin bits in ssier to 0 beforehand. 24.12.8 b output state b output is undefined for a maximum of one cycle immediately after deep software standby mode is canceled with the iokeep bit cleared to 0 or immediately after the iokeep bit is cleared after cancellation of deep software standby mode with the iokeep bit set to 1. however, b can be normally output by setting the iokeep and pstop1 bits. for details, see section 24.8.4, b operation after exit from deep software standby mode. section 24 power-down modes rev. 1.00 sep. 13, 2007 page 990 of 1102 rej09b0365-0100 section 25 list of registers rev. 1.00 sep. 13, 2007 page 991 of 1102 rej09b0365-0100 section 25 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified accordi ng to functional modules. ? the number of acces s cycles indicates the number of stat es based on the specified reference clock. for details, refer to secti on 8.5.4, external bus interface. ? among the internal i/o register area, addresses not listed in th e list of registers are undefined or reserved addresses. undefi ned and reserved addresses cannot be accessed. do not access these addresses; otherwise, the operation when accessing these bi ts and subsequent operations cannot be guaranteed. 2. register bits ? bit configurations of the registers are listed in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? space in the bit name field indicates that the entire register is allo cated to either the counter or data. ? for the registers of 16 or 32 bits, the msb is listed first. ? byte configuration description order is subject to big endian. 3. register states in each operating mode ? register states are listed in the same order as the register addresses. ? for the initialized state of each bit, refer to the register description in the corresponding section. ? the register states shown here ar e for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. section 25 list of registers rev. 1.00 sep. 13, 2007 page 992 of 1102 rej09b0365-0100 25.1 register addresses (address order) register name abbreviation number of bits address module data width access cycles (read/write) timer control register_4 t cr_4 8 h'fea40 tmr_4 16 3p /3p timer control register_5 t cr_5 8 h'fea41 tmr_5 16 3p /3p timer control/status register _4 tcsr_4 8 h'fea42 tmr_4 16 3p /3p timer control/status register _5 tcsr_5 8 h'fea43 tmr_5 16 3p /3p time constant register a_4 tcora_4 8 h'fea44 tmr_4 16 3p /3p time constant register a_5 tcora_5 8 h'fea45 tmr_5 16 3p /3p time constant register b_4 tcorb_4 8 h'fea46 tmr_4 16 3p /3p time constant register b_5 tcorb_5 8 h'fea47 tmr_5 16 3p /3p timer counter_4 tcnt_4 8 h'fea48 tmr_4 16 3p /3p timer counter_5 tcnt_5 8 h'fea49 tmr_5 16 3p /3p timer counter control register_4 tccr_4 8 h'fea4a tmr_4 16 3p /3p timer counter control register_5 tccr_5 8 h'fea4b tmr_5 16 3p /3p crc control register crccr 8 h'fea4c crc 16 3p /3p crc data input register crcdir 8 h'fea4d crc 16 3p /3p crc data output register crcdor 16 h'fea4e crc 16 3p /3p timer control register_6 t cr_6 8 h'fea50 tmr_6 16 3p /3p timer control register_7 t cr_7 8 h'fea51 tmr_7 16 3p /3p timer control/status register _6 tcsr_6 8 h'fea52 tmr_6 16 3p /3p timer control/status register _7 tcsr_7 8 h'fea53 tmr_7 16 3p /3p time constant register a_6 tcora_6 8 h'fea54 tmr_6 16 3p /3p time constant register a_7 tcora_7 8 h'fea55 tmr_7 16 3p /3p time constant register b_6 tcorb_6 8 h'fea56 tmr_6 16 3p /3p time constant register b_7 tcorb_7 8 h'fea57 tmr_7 16 3p /3p timer counter_6 tcnt_6 8 h'fea58 tmr_6 16 3p /3p timer counter_7 tcnt_7 8 h'fea59 tmr_7 16 3p /3p timer counter control register_6 tccr_6 8 h'fea5a tmr_6 16 3p /3p timer counter control register_7 tccr_7 8 h'fea5b tmr_7 16 3p /3p a/d data register a_1 a ddra_1 16 h'fea80 a/d_1 16 3p /3p a/d data register b_1 a ddrb_1 16 h'fea82 a/d_1 16 3p /3p a/d data register c_1 addrc_1 16 h'fea84 a/d_1 16 3p /3p a/d data register d_1 addrd_1 16 h'fea86 a/d_1 16 3p /3p a/d data register e_2 a ddre_2 16 h'fea88 a/d_2 16 3p /3p section 25 list of registers rev. 1.00 sep. 13, 2007 page 993 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) a/d data register f_2 addrf_2 16 h'fea8a a/d_2 16 3p /3p a/d data register g_2 a ddrg_2 16 h'fea8c a/d_2 16 3p /3p a/d data register h_2 addrh_2 16 h'fea8e a/d_2 16 3p /3p a/d data register e_1 a ddre_1 16 h'fea90 a/d_1 16 3p /3p a/d data register f_1 addrf_1 16 h'fea92 a/d_1 16 3p /3p a/d data register g_1 a ddrg_1 16 h'fea94 a/d_1 16 3p /3p a/d data register h_1 addrh_1 16 h'fea96 a/d_1 16 3p /3p a/d data register a_2 a ddra_2 16 h'fea98 a/d_2 16 3p /3p a/d data register b_2 a ddrb_2 16 h'fea9a a/d_2 16 3p /3p a/d data register c_2 addrc_2 16 h'fea9c a/d_2 16 3p /3p a/d data register d_2 addrd_2 16 h'fea9e a/d_2 16 3p /3p a/d control/status register_1 adcsr_1 8 h'feaa0 a/d_1 16 3p /3p a/d control register_1 adcr_1 8 h'feaa1 a/d_1 16 3p /3p a/d control/status register_2 adcsr_2 8 h'feab0 a/d_2 16 3p /3p a/d control register_2 adcr_2 8 h'feab1 a/d_2 16 3p /3p port n register portn 8 h'fee56 i/o port 8 3p /3p port n input buffer control regi ster pnicr 8 h'fee57 i/o port 8 3p /3p serial mode register_5 smr_5 8 h'ff600 sci_5 8 3p /3p bit rate register_5 brr_5 8 h'ff601 sci_5 8 3p /3p serial control register_5 scr_5 8 h'ff602 sci_5 8 3p /3p transmit data register_5 tdr_5 8 h'ff603 sci_5 8 3p /3p serial status register_5 ssr_5 8 h'ff604 sci_5 8 3p /3p receive data register_5 rdr_5 8 h'ff605 sci_5 8 3p /3p smart card mode register _5 scmr_5 8 h'ff606 sci_5 8 3p /3p serial extended mode register_5 semr_5 8 h'ff608 sci_5 8 3p /3p irda control register ircr 8 h'ff60c sci_5 8 3p /3p serial mode register_6 smr_6 8 h'ff610 sci_6 8 3p /3p bit rate register_6 brr_6 8 h'ff611 sci_6 8 3p /3p serial control register_6 scr_6 8 h'ff612 sci_6 8 3p /3p transmit data register_6 tdr_6 8 h'ff613 sci_6 8 3p /3p serial status register_6 ssr_6 8 h'ff614 sci_6 8 3p /3p receive data register_6 rdr_6 8 h'ff615 sci_6 8 3p /3p section 25 list of registers rev. 1.00 sep. 13, 2007 page 994 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) smart card mode register _6 scmr_6 8 h'ff616 sci_6 8 3p /3p serial extended mode register_6 semr_6 8 h'ff618 sci_6 8 3p /3p ppg output control register_1 pcr_1 8 h'ff636 ppg_1 8 3p /3p ppg output mode register_1 pmr_1 8 h'ff637 ppg_1 8 3p /3p next data enable register h_1 nderh_1 8 h'ff638 ppg_1 8 3p /3p next data enable register l_1 nderl_1 8 h'ff639 ppg_1 8 3p /3p output data register h_1 podrh_1 8 h'ff63a ppg_1 8 3p /3p output data register l_1 podrl_1 8 h'ff63b ppg_1 8 3p /3p next data register h_1 * ndrh_1 8 h'ff63c ppg_1 8 3p /3p next data register l_1 * ndrl_1 8 h'ff63d ppg_1 8 3p /3p next data register h_1 * ndrh_1 8 h'ff63e ppg_1 8 3p /3p next data register l_1 * ndrl_1 8 h'ff63f ppg_1 8 3p /3p i 2 c bus control register a_2 iccra_2 8 h'ff640 iic2_2 8 3p /3p i 2 c bus control register b_2 iccrb_2 8 h'ff641 iic2_2 8 3p /3p i 2 cbus mode register_2 ic mr_2 8 h'ff642 iic2_2 8 3p /3p i 2 c bus interrupt enable regist er_2 icier_2 8 h'ff643 iic2_2 8 3p /3p i 2 c bus status register_2 icsr_2 8 h'ff644 iic2_2 8 3p /3p slave address register_2 sar_2 8 h'ff645 iic2_2 8 3p /3p i 2 c bus transmit data register_2 icdrt_2 8 h'ff646 iic2_2 8 3p /3p i 2 c bus receive data register_2 icdrr_2 8 h'ff647 iic2_2 8 3p /3p i 2 c bus control register a_3 iccra_3 8 h'ff648 iic2_3 8 3p /3p i 2 c bus control register b_3 iccrb_3 8 h'ff649 iic2_3 8 3p /3p i 2 c bus mode register_3 ic mr_3 8 h'ff64a iic2_3 8 3p /3p i 2 c bus interrupt enable register _3 icier_3 8 h'ff64b iic2_3 8 3p /3p i 2 c bus status register_3 icsr_3 8 h'ff64c iic2_3 8 3p /3p slave address register_3 sar_3 8 h'ff64d iic2_3 8 3p /3p i 2 c bus transmit data register_3 icdrt_3 8 h'ff64e iic2_3 8 3p /3p i 2 c bus receive data register _3 icdrr_3 8 h'ff64f iic2_3 8 3p /3p timer start register tstrb 8 h'ffb00 tpu (unit 1) 16 2p /2p timer synchronous register tsyr b 8 h'ffb01 tpu (unit 1) 16 2p /2p timer control register_6 tcr_6 8 h'ffb10 tpu_6 16 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 995 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) timer mode register_6 tmdr_6 8 h'ffb11 tpu_6 16 2p /2p timer i/o control register h _6 tiorh_6 8 h'ffb12 tpu_6 16 2p /2p timer i/o control register l_6 tiorl_6 8 h'ffb13 tpu_6 16 2p /2p timer interrupt enable register_6 tier_6 8 h'ffb14 tpu_6 16 2p /2p timer status register_6 tsr_6 8 h'ffb15 tpu_6 16 2p /2p timer counter_6 tcnt_6 16 h'ffb16 tpu_6 16 2p /2p timer general register a_6 tgra_6 16 h'ffb18 tpu_6 16 2p /2p timer general register b_6 tgrb_6 16 h'ffb1a tpu_6 16 2p /2p timer general register c_6 tgrc_6 16 h'ffb1c tpu_6 16 2p /2p timer general register d_6 tgrd_6 16 h'ffb1e tpu_6 16 2p /2p timer control register_7 tcr_7 8 h'ffb20 tpu_7 16 2p /2p timer mode register_7 tmdr_7 8 h'ffb21 tpu_7 16 2p /2p timer i/o control register _7 tior_7 8 h'ffb22 tpu_7 16 2p /2p timer interrupt enable register_7 tier_7 8 h'ffb24 tpu_7 16 2p /2p timer status register_7 tsr_7 8 h'ffb25 tpu_7 16 2p /2p timer counter_7 tcnt_7 16 h'ffb26 tpu_7 16 2p /2p timer general register a_7 tgra_7 16 h'ffb28 tpu_7 16 2p /2p timer general register b_7 tgrb_7 16 h'ffb2a tpu_7 16 2p /2p timer control register_8 tcr_8 8 h'ffb30 tpu_8 16 2p /2p timer mode register_8 tmdr_8 8 h'ffb31 tpu_8 16 2p /2p timer i/o control register _8 tior_8 8 h'ffb32 tpu_8 16 2p /2p timer interrupt enable register_8 tier_8 8 h'ffb34 tpu_8 16 2p /2p timer status register_8 tsr_8 8 h'ffb35 tpu_8 16 2p /2p timer counter_8 tcnt_8 16 h'ffb36 tpu_8 16 2p /2p timer general register a_8 tgra_8 16 h'ffb38 tpu_8 16 2p /2p timer general register b_8 tgrb_8 16 h'ffb3a tpu_8 16 2p /2p timer control register_9 tcr_9 8 h'ffb40 tpu_9 16 2p /2p timer mode register_9 tmdr_9 8 h'ffb41 tpu_9 16 2p /2p timer i/o control register h _9 tiorh_9 8 h'ffb42 tpu_9 16 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 996 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) timer i/o control register l _9 tiorl_9 8 h'ffb43 tpu_9 16 2p /2p timer interrupt enable register_9 tier_9 8 h'ffb44 tpu_9 16 2p /2p timer status register_9 tsr_9 8 h'ffb45 tpu_9 16 2p /2p timer counter_9 tcnt_9 16 h'ffb46 tpu_9 16 2p /2p timer general register a_9 tgra_9 16 h'ffb48 tpu_9 16 2p /2p timer general register b_9 tgrb_9 16 h'ffb4a tpu_9 16 2p /2p timer general register c_9 tgrc_9 16 h'ffb4c tpu_9 16 2p /2p timer general register d_9 tgrd_9 16 h'ffb4e tpu_9 16 2p /2p timer control register_10 tcr_10 8 h'ffb50 tpu_10 16 2p /2p timer mode register_10 tmdr_10 8 h'ffb51 tpu_10 16 2p /2p timer i/o control register_10 tior_10 8 h'ffb52 tpu_10 16 2p /2p timer interrupt enable register_10 tier_10 8 h'ffb54 tpu_10 16 2p /2p timer status register_10 tsr_10 8 h'ffb55 tpu_10 16 2p /2p timer counter_10 tcnt_10 16 h'ffb56 tpu_10 16 2p /2p timer general register a_10 tgra_10 16 h'ffb58 tpu_10 16 2p /2p timer general register b_10 tgrb_10 16 h'ffb5a tpu_10 16 2p /2p timer control register_11 tcr_11 8 h'ffb60 tpu_11 16 2p /2p timer mode register_11 tmdr_11 8 h'ffb61 tpu_11 16 2p /2p timer i/o control register_11 tior_11 8 h'ffb62 tpu_11 16 2p /2p timer interrupt enable register_11 tier_11 8 h'ffb64 tpu_11 16 2p /2p timer status register_11 tsr_11 8 h'ffb65 tpu_11 16 2p /2p timer counter_11 tcnt_11 16 h'ffb66 tpu_11 16 2p /2p timer general register a_11 tgra_11 16 h'ffb68 tpu_11 16 2p /2p timer general register b_11 tgrb_11 16 h'ffb6a tpu_11 16 2p /2p port 1 data direction register p1ddr 8 h'ffb80 i/o port 8 2p /2p port 2 data direction register p2ddr 8 h'ffb81 i/o port 8 2p /2p port 3 data direction register p3ddr 8 h'ffb82 i/o port 8 2p /2p port 6 data direction register p6ddr 8 h'ffb85 i/o port 8 2p /2p port a data direction register paddr 8 h'ffb89 i/o port 8 2p /2p port b data direction register pbddr 8 h'ffb8a i/o port 8 2p /2p port c data direction regist er pcddr 8 h'ffb8b i/o port 8 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 997 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) port d data direction register pdddr 8 h'ffb8c i/o port 8 2p /2p port e data direction register peddr 8 h'ffb8d i/o port 8 2p /2p port f data direction register pfddr 8 h'ffb8e i/o port 8 2p /2p port 1 input buffer control register p1icr 8 h'ffb90 i/o port 8 2p /2p port 2 input buffer control register p2icr 8 h'ffb91 i/o port 8 2p /2p port 3 input buffer control register p3icr 8 h'ffb92 i/o port 8 2p /2p port 4 input buffer control register p4icr 8 h'ffb93 i/o port 8 2p /2p port 5 input buffer control register p5icr 8 h'ffb94 i/o port 8 2p /2p port 6 input buffer control register p6icr 8 h'ffb95 i/o port 8 2p /2p port a input buffer control r egister paicr 8 h'ffb99 i/o port 8 2p /2p port b input buffer control regi ster pbicr 8 h'ffb9a i/o port 8 2p /2p port c input buffer control register pcicr 8 h'ffb9b i/o port 8 2p /2p port d input buffer control regist er pdicr 8 h'ffb9c i/o port 8 2p /2p port e input buffer control regi ster peicr 8 h'ffb9d i/o port 8 2p /2p port f input buffer control register pficr 8 h'ffb9e i/o port 8 2p /2p port h register porth 8 h'ffba0 i/o port 8 2p /2p port i register porti 8 h'ffba1 i/o port 8 2p /2p port j register portj 8 h'ffba2 i/o port 8 2p /2p port k register portk 8 h'ffba3 i/o port 8 2p /2p port h data register p hdr 8 h'ffba4 i/o port 8 2p /2p port i data register pidr 8 h'ffba5 i/o port 8 2p /2p port j data register pjdr 8 h'ffba6 i/o port 8 2p /2p port k data register pkdr 8 h'ffba7 i/o port 8 2p /2p port h data direction register phddr 8 h'ffba8 i/o port 8 2p /2p port i data direction register piddr 8 h'ffba9 i/o port 8 2p /2p port j data direction regist er pjddr 8 h'ffbaa i/o port 8 2p /2p port k data direction register pkddr 8 h'ffbab i/o port 8 2p /2p port h input buffer control regist er phicr 8 h'ffbac i/o port 8 2p /2p port i input buffer control regist er piicr 8 h'ffbad i/o port 8 2p /2p port j input buffer control regi ster pjicr 8 h'ffbae i/o port 8 2p /2p port k input buffer control regi ster pkicr 8 h'ffbaf i/o port 8 2p /2p port d pull-up mos control register pdpcr 8 h'ffbb4 i/o port 8 2p /2p port e pull-up mos control register pepcr 8 h'ffbb5 i/o port 8 2p /2p port f pull-up mos control regist er pfpcr 8 h'ffbb6 i/o port 8 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 998 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) port h pull-up mos control regist er phpcr 8 h'ffbb8 i/o port 8 2p /2p port i pull-up mos control regist er pipcr 8 h'ffbb9 i/o port 8 2p /2p port j pull-up mos control register pjpcr 8 h'ffbba i/o port 8 2p /2p port k pull-up mos control register pkpcr 8 h'ffbbb i/o port 8 2p /2p port 2 open-drain control register p2odr 8 h'ffbbc i/o port 8 2p /2p port f open-drain control regist er pfodr 8 h'ffbbd i/o port 8 2p /2p port function control register 0 pfcr0 8 h'ffbc0 i/o port 8 2p /3p port function control register 1 pfcr1 8 h'ffbc1 i/o port 8 2p /3p port function control register 2 pfcr2 8 h'ffbc2 i/o port 8 2p /3p port function control register 4 pfcr4 8 h'ffbc4 i/o port 8 2p /3p port function control register 6 pfcr6 8 h'ffbc6 i/o port 8 2p /3p port function control register 7 pfcr7 8 h'ffbc7 i/o port 8 2p /3p port function control register 9 pfcr9 8 h'ffbc9 i/o port 8 2p /3p port function control register a pfcra 8 h'ffbca i/o port 8 2p /3p port function control register b pfcrb 8 h'ffbcb i/o port 8 2p /3p port function control regist er c pfcrc 8 h'ffbcc i/o port 8 2p /3p port function control regist er d pfcrd 8 h'ffbcd i/o port 8 2p /3p software standby release irq enable register ssier 16 h'ffbce intc 8 2p /3p deep standby backup register 0 dpsbkr0 8 h'ffbf0 system 8 2i /3i deep standby backup register 1 dpsbkr1 8 h'ffbf1 system 8 2i /3i deep standby backup register 2 dpsbkr2 8 h'ffbf2 system 8 2i /3i deep standby backup register 3 dpsbkr3 8 h'ffbf3 system 8 2i /3i deep standby backup register 4 dpsbkr4 8 h'ffbf4 system 8 2i /3i deep standby backup register 5 dpsbkr5 8 h'ffbf5 system 8 2i /3i deep standby backup register 6 dpsbkr6 8 h'ffbf6 system 8 2i /3i deep standby backup register 7 dpsbkr7 8 h'ffbf7 system 8 2i /3i deep standby backup register 8 dpsbkr8 8 h'ffbf8 system 8 2i /3i deep standby backup register 9 dpsbkr9 8 h'ffbf9 system 8 2i /3i deep standby backup register 10 dpsbkr10 8 h'ffbfa system 8 2i /3i deep standby backup register 11 dpsbkr11 8 h'ffbfb system 8 2i /3i deep standby backup register 12 dpsbkr12 8 h'ffbfc system 8 2i /3i deep standby backup register 13 dpsbkr13 8 h'ffbfd system 8 2i /3i deep standby backup register 14 dpsbkr14 8 h'ffbfe system 8 2i /3i deep standby backup register 15 dpsbkr15 8 h'ffbff system 8 2i /3i section 25 list of registers rev. 1.00 sep. 13, 2007 page 999 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) dma source address register _0 dsar_0 32 h'ffc00 dmac_0 16 2i /2i dma destination address register_0 ddar_0 32 h'ffc04 dmac_0 16 2i /2i dma offset register_0 do fr_0 32 h'ffc08 dmac_0 16 2i /2i dma transfer count register_0 dtcr_0 32 h'ffc0c dmac_0 16 2i /2i dma block size register_0 dbsr_0 32 h'ffc10 dmac_0 16 2i /2i dma mode control register_0 dmdr_0 32 h'ffc14 dmac_0 16 2i /2i dma address control register_0 dacr_0 32 h'ffc18 dmac_0 16 2i /2i dma source address register _1 dsar_1 32 h'ffc20 dmac_1 16 2i /2i dma destination address register_1 ddar_1 32 h'ffc24 dmac_1 16 2i /2i dma offset register_1 do fr_1 32 h'ffc28 dmac_1 16 2i /2i dma transfer count register_1 dtcr_1 32 h'ffc2c dmac_1 16 2i /2i dma block size register_1 dbsr_1 32 h'ffc30 dmac_1 16 2i /2i dma mode control register_1 dmdr_1 32 h'ffc34 dmac_1 16 2i /2i dma address control register_1 dacr_1 32 h'ffc38 dmac_1 16 2i /2i dma source address register _2 dsar_2 32 h'ffc40 dmac_2 16 2i /2i dma destination address register_2 ddar_2 32 h'ffc44 dmac_2 16 2i /2i dma offset register_2 do fr_2 32 h'ffc48 dmac_2 16 2i /2i dma transfer count register_2 dtcr_2 32 h'ffc4c dmac_2 16 2i /2i dma block size register_2 dbsr_2 32 h'ffc50 dmac_2 16 2i /2i dma mode control register_2 dmdr_2 32 h'ffc54 dmac_2 16 2i /2i dma address control register_2 dacr_2 32 h'ffc58 dmac_2 16 2i /2i dma source address register _3 dsar_3 32 h'ffc60 dmac_3 16 2i /2i dma destination address register_3 ddar_3 32 h'ffc64 dmac_3 16 2i /2i dma offset register_3 do fr_3 32 h'ffc68 dmac_3 16 2i /2i dma transfer count register_3 dtcr_3 32 h'ffc6c dmac_3 16 2i /2i dma block size register_3 dbsr_3 32 h'ffc70 dmac_3 16 2i /2i dma mode control register_3 dmdr_3 32 h'ffc74 dmac_3 16 2i /2i dma address control register_3 dacr_3 32 h'ffc78 dmac_3 16 2i /2i dma module request select regist er_0 dmrsr_0 8 h'ffd20 dmac_0 16 2i /2i dma module request select regist er_1 dmrsr_1 8 h'ffd21 dmac_1 16 2i /2i dma module request select regist er_2 dmrsr_2 8 h'ffd22 dmac_2 16 2i /2i dma module request select regist er_3 dmrsr_3 8 h'ffd23 dmac_3 16 2i /2i interrupt priority register a ipra 16 h'ffd40 intc 16 2i /3i interrupt priority register b iprb 16 h'ffd42 intc 16 2i /3i interrupt priority register c iprc 16 h'ffd44 intc 16 2i /3i section 25 list of registers rev. 1.00 sep. 13, 2007 page 1000 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) interrupt priority register d iprd 16 h'ffd46 intc 16 2i /3i interrupt priority register e ipre 16 h'ffd48 intc 16 2i /3i interrupt priority register f iprf 16 h'ffd4a intc 16 2i /3i interrupt priority register g iprg 16 h'ffd4c intc 16 2i /3i interrupt priority register h iprh 16 h'ffd4e intc 16 2i /3i interrupt priority register i ipri 16 h'ffd50 intc 16 2i /3i interrupt priority register k iprk 16 h'ffd54 intc 16 2i /3i interrupt priority register l iprl 16 h'ffd56 intc 16 2i /3i interrupt priority register m iprm 16 h'ffd58 intc 16 2i /3i interrupt priority register n iprn 16 h'ffd5a intc 16 2i /3i interrupt priority register o ipro 16 h'ffd5c intc 16 2i /3i interrupt priority register q iprq 16 h'ffd60 intc 16 2i /3i interrupt priority register r iprr 16 h'ffd62 intc 16 2i /3i irq sense control register h iscrh 16 h'ffd68 intc 16 2i /3i irq sense control register l iscrl 16 h'ffd6a intc 16 2i /3i dtc vector base register dtcvbr 32 h'ffd80 bsc 16 2i /3i bus width control register abwcr 16 h'ffd84 bsc 16 2i /3i access state control register astcr 16 h'ffd86 bsc 16 2i /3i wait control register a wtcra 16 h'ffd88 bsc 16 2i /3i wait control register b wtcrb 16 h'ffd8a bsc 16 2i /3i read strobe timing control register rdncr 16 h'ffd8c bsc 16 2i /3i cs assertion period control regi ster csacr 16 h'ffd8e bsc 16 2i /3i idle control register idlcr 16 h'ffd90 bsc 16 2i /3i bus control register1 bcr1 16 h'ffd92 bsc 16 2i /3i bus control register2 bcr2 8 h'ffd94 bsc 16 2i /3i endian control register endiancr 8 h'ffd95 bsc 16 2i /3i sram mode control register sramcr 16 h'ffd98 bsc 16 2i /3i burst rom interface control regi ster bromcr 16 h'ffd9a bsc 16 2i /3i address/data multiplexed i/o control register mpxcr 16 h'ffd9c bsc 16 2i /3i ram emulation register ramer 8 h'ffd9e bsc 16 2i /3i mode control register mdcr 16 h'ffdc0 system 16 2i /3i system control register syscr 16 h'ffdc2 system 16 2i /3i system clock control register sckcr 16 h'ffdc4 system 16 2i /3i standby control register sbycr 16 h'ffdc6 system 16 2i /3i section 25 list of registers rev. 1.00 sep. 13, 2007 page 1001 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) module stop control register a mstpcra 16 h?ffdc8 system 16 2i /3i module stop control register b mstpcrb 16 h?ffdca system 16 2i /3i module stop control register c mstpcrc 16 h?ffdcc system 16 2i /3i flash code control/status regist er fccs 8 h?ffde8 flash 16 2i /2i flash program code select register fpcs 8 h?ffde9 flash 16 2i /2i flash erase code select register fecs 8 h?ffdea flash 16 2i /2i flash key code register fkey 8 h?ffdec flash 16 2i /2i flash mat select register fmats 8 h?ffded flash 16 2i /2i flash transfer destination address register ftdar 8 h?ffdee flash 16 2i /2i deep standby control register dpsbycr 8 h?ffe70 system 8 2i /3i deep standby wait control regi ster dpswcr 8 h?ffe71 system 8 2i /3i deep standby interrupt enable regist er dpsier 8 h?ffe72 system 8 2i /3i deep standby interrupt flag regi ster dpsifr 8 h?ffe73 system 8 2i /3i deep standby interrupt edge regist er dpsiegr 8 h?ffe74 system 8 2i /3i reset status register rstsr 8 h?ffe75 system 8 2i /3i serial extended mode register_2 semr_2 8 h?ffe84 sci_2 8 2p /2p serial mode register_3 smr_3 8 h?ffe88 sci_3 8 2p /2p bit rate register_3 brr_3 8 h?ffe89 sci_3 8 2p /2p serial control register_3 scr_3 8 h?ffe8a sci_3 8 2p /2p transmit data register_3 tdr_3 8 h?ffe8b sci_3 8 2p /2p serial status register_3 ssr_3 8 h?ffe8c sci_3 8 2p /2p receive data register_3 rdr_3 8 h?ffe8d sci_3 8 2p /2p smart card mode register_3 scmr_3 8 h?ffe8e sci_3 8 2p /2p serial mode register_4 smr_4 8 h?ffe90 sci_4 8 2p /2p bit rate register_4 brr_4 8 h?ffe91 sci_4 8 2p /2p serial control register_4 scr_4 8 h?ffe92 sci_4 8 2p /2p transmit data register_4 tdr_4 8 h?ffe93 sci_4 8 2p /2p serial status register_4 ssr_4 8 h?ffe94 sci_4 8 2p /2p receive data register_4 rdr_4 8 h?ffe95 sci_4 8 2p /2p smart card mode register_4 scmr_4 8 h?ffe96 sci_4 8 2p /2p i 2 c bus control register a_0 iccra_0 8 h?ffeb0 iic2_0 8 2p /2p i 2 c bus control register b_0 iccrb_0 8 h?ffeb1 iic2_0 8 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 1002 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) i 2 c bus mode register_0 ic mr_0 8 h'ffeb2 iic2_0 8 2p /2p i 2 c bus interrupt enable register _0 icier_0 8 h'ffeb3 iic2_0 8 2p /2p i 2 c bus status register_0 icsr_0 8 h'ffeb4 iic2_0 8 2p /2p slave address register_0 sar_0 8 h'ffeb5 iic2_0 8 2p /2p i 2 c bus transmit data register _0 icdrt_0 8 h'ffeb6 iic2_0 8 2p /2p i 2 c bus receive data register _0 icdrr_0 8 h'ffeb7 iic2_0 8 2p /2p i 2 c bus control register a_1 iccra_1 8 h'ffeb8 iic2_1 8 2p /2p i 2 c bus control register b_1 iccrb_1 8 h'ffeb9 iic2_1 8 2p /2p i 2 c bus mode register_1 icmr_1 8 h'ffeba iic2_1 8 2p /2p i 2 c bus interrupt enable regist er_1 icier_1 8 h'ffebb iic2_1 8 2p /2p i 2 c bus status register_1 icsr_1 8 h'ffebc iic2_1 8 2p /2p slave address register_1 sar_1 8 h'ffebd iic2_1 8 2p /2p i 2 c bus transmit data regist er_1 icdrt_1 8 h'ffebe iic2_1 8 2p /2p i 2 c bus receive data register _1 icdrr_1 8 h'ffebf iic2_1 8 2p /2p timer control register_2 tcr_2 8 h'ffec0 tmr_2 16 2p /2p timer control register_3 tcr_3 8 h'ffec1 tmr_3 16 2p /2p timer control/status register _2 tcsr_2 8 h'ffec2 tmr_2 16 2p /2p timer control/status register _3 tcsr_3 8 h'ffec3 tmr_3 16 2p /2p time constant register a_2 tcora_2 8 h'ffec4 tmr_2 16 2p /2p time constant register a_3 tcora_3 8 h'ffec5 tmr_3 16 2p /2p time constant register b_2 tcorb_2 8 h'ffec6 tmr_2 16 2p /2p time constant register b_3 tcorb_3 8 h'ffec7 tmr_3 16 2p /2p timer counter_2 tcnt_2 8 h'ffec8 tmr_2 16 2p /2p timer counter_3 tcnt_3 8 h'ffec9 tmr_3 16 2p /2p timer counter control register_2 tccr_2 8 h'ffeca tmr_2 16 2p /2p timer counter control register_3 tccr_3 8 h'ffecb tmr_3 16 2p /2p timer control register_4 tcr_4 8 h'ffee0 tpu_4 16 2p /2p timer mode register_4 tmdr_4 8 h'ffee1 tpu_4 16 2p /2p timer i/o control register_4 tior_4 8 h'ffee2 tpu_4 16 2p /2p timer interrupt enable register_4 tier_4 8 h'ffee4 tpu_4 16 2p /2p timer status register_4 tsr_4 8 h'ffee5 tpu_4 16 2p /2p timer counter_4 tcnt_4 16 h'ffee6 tpu_4 16 2p /2p timer general register a_4 tgra_4 16 h'ffee8 tpu_4 16 2p /2p timer general register b_4 tgrb_4 16 h'ffeea tpu_4 16 2p /2p timer control register_5 tcr_5 8 h'ffef0 tpu_5 16 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 1003 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) timer mode register_5 tmdr_5 8 h'ffef1 tpu_5 16 2p /2p timer i/o control register_5 tior_5 8 h'ffef2 tpu_5 16 2p /2p timer interrupt enable register_5 tier_5 8 h'ffef4 tpu_5 16 2p /2p timer status register_5 tsr_5 8 h'ffef5 tpu_5 16 2p /2p timer counter_5 tcnt_5 16 h'ffef6 tpu_5 16 2p /2p timer general register a_5 tgra_5 16 h'ffef8 tpu_5 16 2p /2p timer general register b_5 tgrb_5 16 h'ffefa tpu_5 16 2p /2p dtc enable register a dtcera 16 h'fff20 intc 16 2i /3i dtc enable register b dtcerb 16 h'fff22 intc 16 2i /3i dtc enable register c dtcerc 16 h'fff24 intc 16 2i /3i dtc enable register d dtcerd 16 h'fff26 intc 16 2i /3i dtc enable register e dtcere 16 h'fff28 intc 16 2i /3i dtc enable register f dtcerf 16 h'fff2a intc 16 2i /3i dtc control register dtccr 8 h'fff30 intc 16 2i /3i interrupt control register intcr 8 h'fff32 intc 16 2i /3i cpu priority control register cpupcr 8 h'fff33 intc 16 2i /3i irq enable register ier 16 h'fff34 intc 16 2i /3i irq status register isr 16 h'fff36 intc 16 2i /3i port 1 register port1 8 h'fff40 i/o port 8 2p /? port 2 register port2 8 h'fff41 i/o port 8 2p /? port 3 register port3 8 h'fff42 i/o port 8 2p /? port 4 register port4 8 h'fff43 i/o port 8 2p /? port 5 register port5 8 h'fff44 i/o port 8 2p /? port 6 register port6 8 h'fff45 i/o port 8 2p /? port a register porta 8 h'fff49 i/o port 8 2p /? port b register portb 8 h'fff4a i/o port 8 2p /? port c register portc 8 h'fff4b i/o port 8 2p /? port d register portd 8 h'fff4c i/o port 8 2p /? port e register porte 8 h'fff4d i/o port 8 2p /? port f register portf 8 h'fff4e i/o port 8 2p /? port 1 data register p1dr 8 h'fff50 i/o port 8 2p /2p port 2 data register p2dr 8 h'fff51 i/o port 8 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 1004 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) port 3 data register p3dr 8 h'fff52 i/o port 8 2p /2p port 6 data register p6dr 8 h'fff55 i/o port 8 2p /2p port a data register padr 8 h'fff59 i/o port 8 2p /2p port b data register pbdr 8 h'fff5a i/o port 8 2p /2p port c data register pcdr 8 h'fff5b i/o port 8 2p /2p port d data register pddr 8 h'fff5c i/o port 8 2p /2p port e data register pedr 8 h'fff5d i/o port 8 2p /2p port f data register pfdr 8 h'fff5e i/o port 8 2p /2p serial mode register_2 smr_2 8 h'fff60 sci_2 8 2p /2p bit rate register_2 brr_2 8 h'fff61 sci_2 8 2p /2p serial control register_2 scr_2 8 h'fff62 sci_2 8 2p /2p transmit data register_2 tdr_2 8 h'fff63 sci_2 8 2p /2p serial status register_2 ssr_2 8 h'fff64 sci_2 8 2p /2p receive data register_2 rdr_2 8 h'fff65 sci_2 8 2p /2p smart card mode register _2 scmr_2 8 h'fff66 sci_2 8 2p /2p d/a data register 0 dadr0 8 h'fff68 d/a 8 2p /2p d/a data register 1 dadr1 8 h'fff69 d/a 8 2p /2p d/a control register 01 dacr01 8 h'fff6a d/a 8 2p /2p ppg output control register pcr 8 h'fff76 ppg_0 8 2p /2p ppg output mode register pmr 8 h'fff77 ppg_0 8 2p /2p next data enable register h nderh 8 h'fff78 ppg_0 8 2p /2p next data enable register l nderl 8 h'fff79 ppg_0 8 2p /2p output data register h podrh 8 h'fff7a ppg_0 8 2p /2p output data register l podrl 8 h'fff7b ppg_0 8 2p /2p next data register h * ndrh 8 h'fff7c ppg_0 8 2p /2p next data register l * ndrl 8 h'fff7d ppg_0 8 2p /2p next data register h * ndrh 8 h'fff7e ppg_0 8 2p /2p next data register l * ndrl 8 h'fff7f ppg_0 8 2p /2p serial mode register_0 smr_0 8 h'fff80 sci_0 8 2p /2p bit rate register_0 brr_0 8 h'fff81 sci_0 8 2p /2p serial control register_0 scr_0 8 h'fff82 sci_0 8 2p /2p transmit data register_0 tdr_0 8 h'fff83 sci_0 8 2p /2p serial status register_0 ssr_0 8 h'fff84 sci_0 8 2p /2p receive data register_0 rdr_0 8 h'fff85 sci_0 8 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 1005 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) smart card mode register _0 scmr_0 8 h'fff86 sci_0 8 2p /2p serial mode register_1 smr_1 8 h'fff88 sci_1 8 2p /2p bit rate register_1 brr_1 8 h'fff89 sci_1 8 2p /2p serial control register_1 scr_1 8 h'fff8a sci_1 8 2p /2p transmit data register_1 tdr_1 8 h'fff8b sci_1 8 2p /2p serial status register_1 ssr_1 8 h'fff8c sci_1 8 2p /2p receive data register_1 rdr_1 8 h'fff8d sci_1 8 2p /2p smart card mode register _1 scmr_1 8 h'fff8e sci_1 8 2p /2p a/d data register a_0 addra_0 16 h'fff90 a/d_0 16 2p /2p a/d data register b_0 addrb_0 16 h'fff92 a/d_0 16 2p /2p a/d data register c_0 addrc_0 16 h'fff94 a/d_0 16 2p /2p a/d data register d_0 addrd_0 16 h'fff96 a/d_0 16 2p /2p a/d data register e_0 addre_0 16 h'fff98 a/d_0 16 2p /2p a/d data register f_0 addrf_0 16 h'fff9a a/d_0 16 2p /2p a/d data register g_0 addrg_0 16 h'fff9c a/d_0 16 2p /2p a/d data register h_0 addrh_0 16 h'fff9e a/d_0 16 2p /2p a/d control/status register_0 adcsr_0 8 h'fffa0 a/d_0 16 2p /2p a/d control register_0 adcr_0 8 h'fffa1 a/d_0 16 2p /2p timer control/status register tcsr 8 h'fffa4 wdt 16 2p /3p timer counter tcnt 8 h'fffa5 wdt 16 2p /3p reset control/status register rstcsr 8 h'fffa7 wdt 16 2p /3p timer control register_0 tcr_0 8 h'fffb0 tmr_0 16 2p /2p timer control register_1 tcr_1 8 h'fffb1 tmr_1 16 2p /2p timer control/status register_0 tcsr_0 8 h'fffb2 tmr_0 16 2p /2p timer control/status register_1 tcsr_1 8 h'fffb3 tmr_1 16 2p /2p time constant register a_0 tcora_0 8 h'fffb4 tmr_0 16 2p /2p time constant register a_1 tcora_1 8 h'fffb5 tmr_1 16 2p /2p time constant register b_0 tcorb_0 8 h'fffb6 tmr_0 16 2p /2p time constant register b_1 tcorb_1 8 h'fffb7 tmr_1 16 2p /2p timer counter_0 tcnt_0 8 h'fffb8 tmr_0 16 2p /2p timer counter_1 tcnt_1 8 h'fffb9 tmr_1 16 2p /2p timer counter control register_0 tccr_0 8 h'fffba tmr_0 16 2p /2p timer counter control register_1 tccr_1 8 h'fffbb tmr_1 16 2p /2p timer start register tstr 8 h'fffbc tpu 16 2p /2p timer synchronous register tsyr 8 h'fffbd tpu 16 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 1006 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) timer control register_0 tcr_0 8 h'fffc0 tpu_0 16 2p /2p timer mode register_0 tmdr_0 8 h'fffc1 tpu_0 16 2p /2p timer i/o control register h _0 tiorh_0 8 h'fffc2 tpu_0 16 2p /2p timer i/o control register l _0 tiorl_0 8 h'fffc3 tpu_0 16 2p /2p timer interrupt enable register_0 tier_0 8 h'fffc4 tpu_0 16 2p /2p timer status register_0 tsr_0 8 h'fffc5 tpu_0 16 2p /2p timer counter_0 tcnt_0 16 h'fffc6 tpu_0 16 2p /2p timer general register a_0 tgra_0 16 h'fffc8 tpu_0 16 2p /2p timer general register b_0 tgrb_0 16 h'fffca tpu_0 16 2p /2p timer general register c_0 tgrc_0 16 h'fffcc tpu_0 16 2p /2p timer general register d_0 tgrd_0 16 h'fffce tpu_0 16 2p /2p timer control register_1 tcr_1 8 h'fffd0 tpu_1 16 2p /2p timer mode register_1 tmdr_1 8 h'fffd1 tpu_1 16 2p /2p timer i/o control register_1 tior_1 8 h'fffd2 tpu_1 16 2p /2p timer interrupt enable register_1 tier_1 8 h'fffd4 tpu_1 16 2p /2p timer status register_1 tsr_1 8 h'fffd5 tpu_1 16 2p /2p timer counter_1 tcnt_1 16 h'fffd6 tpu_1 16 2p /2p timer general register a_1 tgra_1 16 h'fffd8 tpu_1 16 2p /2p timer general register b_1 tgrb_1 16 h'fffda tpu_1 16 2p /2p timer control register_2 tcr_2 8 h'fffe0 tpu_2 16 2p /2p timer mode register_2 tmdr_2 8 h'fffe1 tpu_2 16 2p /2p timer i/o control register_2 tior_2 8 h'fffe2 tpu_2 16 2p /2p timer interrupt enab le register_2 tier_2 8 h'fffe4 tpu_2 16 2p /2p timer status register_2 tsr_2 8 h'fffe5 tpu_2 16 2p /2p timer counter_2 tcnt_2 16 h'fffe6 tpu_2 16 2p /2p timer general register a_2 tgra_2 16 h'fffe8 tpu_2 16 2p /2p timer general register b_2 tgrb_2 16 h'fffea tpu_2 16 2p /2p timer control register_3 tcr_3 8 h'ffff0 tpu_3 16 2p /2p timer mode register_3 tmdr_3 8 h'ffff1 tpu_3 16 2p /2p timer i/o control register h _3 tiorh_3 8 h'ffff2 tpu_3 16 2p /2p timer i/o control register l _3 tiorl_3 8 h'ffff3 tpu_3 16 2p /2p timer interrupt enable register_3 tier_3 8 h'ffff4 tpu_3 16 2p /2p timer status register_3 tsr_3 8 h'ffff5 tpu_3 16 2p /2p timer counter_3 tcnt_3 16 h'ffff6 tpu_3 16 2p /2p timer general register a_3 tgra_3 16 h'ffff8 tpu_3 16 2p /2p section 25 list of registers rev. 1.00 sep. 13, 2007 page 1007 of 1102 rej09b0365-0100 register name abbreviation number of bits address module data width access cycles (read/write) timer general register b_3 tgrb_3 16 h'ffffa tpu_3 16 2p /2p timer general register c_3 tgrc_3 16 h'ffffc tpu_3 16 2p /2p timer general register d_3 tgrd_3 16 h'ffffe tpu_3 16 2p /2p note: * when the same output trigger is specified for pulse output groups 2 and 3 by the pcr setting, the ndrh address is h'fff7c. when di fferent output triggers are specified, the ndrh addresses for pulse output groups 2 and 3 are h'fff7e and h'fff7c, respectively. similarly, when the same output trigger is specified for pulse output groups 0 and 1 by the pcr setting, the ndrl addr ess is h'fff7d. when different output triggers are specified, the ndrl addre sses for pulse output groups 0 and 1 are h'fff7f and h'fff7d, respectively. when the same output trigger is specified for pulse output groups 6 and 7 by the pcr setting, the ndrh address is h'ff63c. when diffe rent output triggers are specified, the ndrh addresses for pulse output groups 6 and 7 are h'ff63e and h'ff63c, respectively. when the same output trigger is specified fo r pulse output groups 4 and 5 by the pcr setting, the ndrl address is h'ff63d. when di fferent output triggers are specified, the ndrl addresses for pulse output groups 4 and 5 are h'ff63f and h'ff63d, respectively. section 25 list of registers rev. 1.00 sep. 13, 2007 page 1008 of 1102 rej09b0365-0100 25.2 register bits register addresses and bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcr_4 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_4 tcr_5 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_5 tcsr_4 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_4 tcsr_5 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_5 tcora_4 tmr_4 tcora_5 tmr_5 tcorb_4 tmr_4 tcorb_5 tmr_5 tcnt_4 tmr_4 tcnt_5 tmr_5 tccr_4 ? ? ? ? tmris ? icks1 icks0 tmr_4 tccr_5 ? ? ? ? tmris ? icks1 icks0 tmr_5 crccr dorclr ? ? ? ? lms g1 g0 crc crcdir crcdor tcr_6 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_6 tcr_7 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_7 tcsr_6 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_6 tcsr_7 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_7 tcora_6 tmr_6 tcora_7 tmr_7 tcorb_6 tmr_6 tcorb_7 tmr_7 tcnt_6 tmr_6 tcnt_7 tmr_7 tccr_6 ? ? ? ? tmris ? icks1 icks0 tmr_6 tccr_7 ? ? ? ? tmris ? icks1 icks0 tmr_7 a/d_1 addra_1 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1009 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module a/d_1 addrb_1 addrc_1 addrd_1 a/d_2 addre_2 addrf_2 addrg_2 addrh_2 a/d_1 addre_1 addrf_1 addrg_1 addrh_1 a/d_2 addra_2 addrb_2 addrc_2 addrd_2 adcsr_1 adf adie adst excks ch3 ch2 ch1 ch0 a/d_1 adcr_1 trgs1 trgs0 scane scans cks1 cks0 adstclr extrgs adcsr_2 adf adie adst excks ch3 ch2 ch1 ch0 adcr_2 trgs1 trgs0 scane scan s cks1 cks0 adstclr extrgs a/d_2 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1010 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module portn ? ? ? ? pn3 pn2 pn1 pn0 pnicr ? ? ? ? pn3icr pn2icr pn1icr pn0icr i/o port smr_5 * c/ a chr pe o/ e stop mp cks1 cks0 sci_5 (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) brr_5 scr_5 * tie rie te re mpie teie cke1 cke0 tdr_5 ssr_5 * tdre rdrf orer fer per tend mpb mpbt (ers) rdr_5 scmr_5 ? ? ? ? sdir sinv ? smif semr_5 ? ? ? abcs acs3 acs2 acs1 acs0 ircr ire ircks2 ircks1 irc ks0 irtxinv irrxinv ? ? c/ a chr pe o/ e stop mp cks1 cks0 sci_6 smr_6 * (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) brr_6 scr_6 * tie rie te re mpie teie cke1 cke0 tdr_6 tdre rdrf orer fer per tend mpb mpbt ssr_6 * (ers) rdr_6 scmr_6 ? ? ? ? sdir sinv ? smif semr_6 ? ? ? abcs acs3 acs2 acs1 acs0 pcr_1 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 ppg_1 pmr_1 g3inv g2inv g1inv g0in v g3nov g2nov g1nov g0nov nderh_1 nder31 nder30 nder29 nder 28 nder27 nder26 nder25 nder24 nderl_1 nder23 nder22 nder21 nder 20 nder19 nder18 nder17 nder16 podrh_1 pod31 pod30 pod29 pod 28 pod27 pod26 pod25 pod24 podrl_1 pod23 pod22 pod21 pod 20 pod19 pod18 pod17 pod16 ndrh_1 * 2 ndr31 ndr30 ndr29 ndr 28 ndr27 ndr26 ndr25 ndr24 ndrl_1 * 2 ndr23 ndr22 ndr21 ndr 20 ndr19 ndr18 ndr17 ndr16 ndrh_1 * 2 ? ? ? ? ndr27 ndr26 ndr25 ndr24 ndrl_1 * 2 ? ? ? ? ndr19 ndr18 ndr17 ndr16 iccra_2 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2_2 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1011 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module iccrb_2 bbsy scp sdao ? sclo ? iicrst ? iic2_2 icmr_2 ? wait ? ? bc wp bc2 bc1 bc0 icier_2 tie teie rie naki e stie acke ackbr ackbt icsr_2 tdre tend rdrf nackf stop al aas adz sar_2 sva6 sva5 sva4 sva3 sva2 sva1 sva0 ? icdrt_2 icdrr_2 iccra_3 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2_3 iccrb_3 bbsy scp sdao ? sclo ? iicrst ? icmr_3 ? wait ? ? bc wp bc2 bc1 bc0 icier_3 tie teie rie naki e stie acke ackbr ackbt icsr_3 tdre tend rdrf nackf stop al aas adz sar_3 sva6 sva5 sva4 sva3 sva2 sva1 sva0 ? icdrt_3 icdrr_3 tstrb ? ? cst5 cst4 cs t3 cst2 cst1 cst0 tsyrb ? ? sync5 sync4 sync3 sync2 sync1 sync0 tpu (unit 1) tcr_6 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_6 tmdr_6 ? ? bfb bfa md3 md2 md1 md0 tiorh_6 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_6 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_6 ? ? ? tciev tgied tgiec tgieb tgiea tsr_6 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_6 tgra_6 tgrb_6 tgrc_6 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1012 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tpu_6 tgrd_6 tcr_7 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_7 tmdr_7 ? ? ? ? md3 md2 md1 md0 tior_7 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_7 ? ? tcieu tci ev ? ? tgieb tgiea tsr_7 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_7 tgra_7 tgrb_7 tcr_8 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_8 tmdr_8 ? ? ? ? md3 md2 md1 md0 tior_8 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_8 ? ? tcieu tci ev ? ? tgieb tgiea tsr_8 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_8 tgra_8 tgrb_8 tcr_9 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_9 tmdr_9 ? ? bfb bfa md3 md2 md1 md0 tiorh_9 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_9 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_9 ? ? ? tciev tgied tgiec tgieb tgiea tsr_9 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_9 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1013 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tpu_9 tgra_9 tgrb_9 tgrc_9 tgrd_9 tcr_10 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_10 tmdr_10 ? ? ? ? md3 md2 md1 md0 tior_10 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_10 ? ? tcieu tci ev ? ? tgieb tgiea tsr_10 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_10 tgra_10 tgrb_10 tcr_11 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_11 tmdr_11 ? ? ? ? md3 md2 md1 md0 tior_11 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_11 ? ? tcieu tci ev ? ? tgieb tgiea tsr_11 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_11 tgra_11 tgrb_11 p1ddr p17ddr p16ddr p15ddr p14ddr p13 ddr p12ddr p11ddr p10ddr i/o port p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr p3ddr p37ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p320ddr section 25 list of registers rev. 1.00 sep. 13, 2007 page 1014 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module p6ddr p67ddr p66ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr i/o port paddr pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr pcddr ? ? pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr pfddr pf7ddr pf6ddr pf5iddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr p1icr p17icr p16icr p15i cr p14icr p13i cr p12icr p11icr p10icr p2icr p27icr p26icr p25i cr p24icr p23i cr p22icr p21icr p20icr p3icr p37icr p36icr p35i cr p34icr p33i cr p32icr p31icr p30icr p4icr p47icr p46icr p45i cr p44icr ? ? ? ? p5icr p57icr p56icr p55i cr p54icr p53i cr p52icr p51icr p50icr p6icr p67icr p66icr p65icr p64icr p63icr p62i cr p61icr p60icr paicr pa7icr pa6icr pa5 icr pa4icr pa3icr pa2icr pa1icr pa0icr pbicr pb7icr pb6icr pb5 icr pb4icr pb3icr pb2icr pb1icr pb0icr pcicr ? ? pc5icr pc4icr pc3icr pc2icr pc1icr pc0icr pdicr pd7icr pd6icr pd5icr pd4icr pd3icr pd2icr pd1icr pd0icr peicr pe7icr pe6icr pe5 icr pe4icr pe3icr pe2icr pe1icr pe0icr pficr pf7icr pf6icr pf5icr pf4icr pf3icr pf2icr pf1icr pf0icr porth ph7 ph6 ph5 ph 4 ph3 ph2 ph1 ph0 porti pi7 pi6 pi5 pi 4 pi3 pi2 pi1 pi0 portj pj7 pj6 pj5 pj 4 pj3 pj2 pj1 pj0 portk pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 phdr ph7dr ph6dr ph5dr ph4dr ph3dr ph2dr ph1dr ph0dr pidr pi7dr pi6dr pi5dr pi4dr pi3dr pi2dr pi1dr pi0dr pjdr pj7dr pj6dr pj5dr pj4dr pj3dr pj2dr pj1dr pj0dr pkdr pk7dr pk6dr pk5dr pk4dr pk3dr pk2dr pk1dr pk0dr phddr ph7ddr ph6ddr ph5ddr ph4ddr ph3ddr ph2ddr ph1ddr ph0ddr piddr pi7ddr pi6ddr pi5ddr pi4ddr pi3ddr pi2ddr pi1ddr pi0ddr pjddr pj7ddr pj6ddr pj5ddr pj4ddr pj3ddr pj2ddr pj1ddr pj0ddr pkddr pk7ddr pk6ddr pk5ddr pk4ddr pk3ddr pk2ddr pk1ddr pk0ddr phicr ph7icr ph6icr ph5icr ph4icr ph3icr ph2icr ph1icr ph0icr piicr pi7icr pi6icr pi5icr pi4icr pi3icr pi2icr pi1icr pi0icr pjicr pj7icr pj6icr pj5icr pj4icr pj3icr pj2icr pj1icr pj0icr pkicr pk7icr pk6icr pk5 icr pk4icr pk3icr pk2icr pk1icr pk0icr section 25 list of registers rev. 1.00 sep. 13, 2007 page 1015 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3p cr pd2pcr pd1pcr pd0pcr i/o port pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr pfpcr pf7pcr pf6pcr pf5pcr pf4pcr pf3pcr pf2pcr pf1pcr pf0pcr phpcr ph7pcr ph6pcr ph5pcr ph4pcr ph3pcr ph2pcr ph1pcr ph0pcr pipcr pi7pcr pi6pcr pi5pcr pi4pcr pi3pcr pi2pcr pi1pcr pi0pcr pjpcr pj7pcr pj6pcr pj5pcr pj4pcr pj3pcr pj2pcr pj1pcr pj0pcr pkpcr pk7pcr pk6pcr pk5pcr pk4pcr pk3pcr pk2pcr pk1pcr pk0pcr p2odr p27odr p26odr p25odr p24o dr p23odr p22odr p21odr p20odr pfodr pf7odr pf6odr pf5odr pf4odr pf3odr pf2odr pf1odr pf0odr pfcr0 cs7e cs6e cs5e cs4e cs3e cs2e cs1e cs0e pfcr1 cs7sa cs7sb cs6sa cs6sb cs5sa cs5sb cs4sa cs4sb pfcr2 cs3s cs2s bss bse rdwrs rdwre asoe waits pfcr4 a23e a22e a21e a20e a19e a18e a17e a16e pfcr6 ? lhwroe ? ? tclks ? ? ? pfcr7 dmas3a dmas3b dmas2a dmas2 b dmas1a dmas1b dmas0a dmas0b pfcr9 tpums5 tpums4 tpums3a tpums3 b tpums2 tpums1 tpums0a tpums0b pfcra tpums11 tpums10 tpums9a tpums9 b tpums8 tpums7 tpums6a tpums6b pfcrb its15 its14 its13 its12 its11 its10 its9 its8 pfcrc its7 its6 its5 its4 its3 its2 its1 its0 pfcrd pcjke ? ? ? ? ? ? ? ssier ssi15 ssi14 ssi13 ssi12 ssi11 ssi10 ssi9 ssi8 intc ssi7 ssi6 ssi5 ssi4 ssi3 ssi2 ssi1 ssi0 dpsbkr0 dkup07 dkup06 dkup05 dkup04 dkup03 dkup02 dkup01 dkup00 system dpsbkr1 dkup17 dkup16 dkup15 dkup14 dkup13 dkup12 dkup11 dkup10 dpsbkr2 dkup27 dkup26 dkup25 dkup24 dkup23 dkup22 dkup21 dkup20 dpsbkr3 dkup37 dkup36 dkup35 dkup34 dkup33 dkup32 dkup31 dkup30 dpsbkr4 dkup47 dkup46 dkup45 dkup44 dkup43 dkup42 dkup41 dkup40 dpsbkr5 dkup57 dkup56 dkup55 dkup54 dkup53 dkup52 dkup51 dkup50 dpsbkr6 dkup67 dkup66 dkup65 dkup64 dkup63 dkup62 dkup61 dkup60 dpsbkr7 dkup77 dkup76 dkup75 dkup74 dkup73 dkup72 dkup71 dkup70 dpsbkr8 dkup87 dkup86 dkup85 dkup84 dkup83 dkup82 dkup81 dkup80 dpsbkr9 dkup97 dkup96 dkup95 dkup94 dkup93 dkup92 dkup91 dkup90 dpsbkr10 dkup107 dkup106 dkup105 dkup104 dkup103 dkup102 dkup101 dkup100 dpsbkr11 dkup117 dkup116 dkup115 dkup114 dkup113 dkup112 dkup111 dkup110 dpsbkr12 dkup127 dkup126 dkup125 dkup124 dkup123 dkup122 dkup121 dkup120 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1016 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dpsbkr13 dkup137 dkup136 dkup135 dkup134 dkup133 dkup132 dkup131 dkup130 system dpsbkr14 dkup147 dkup146 dkup145 dkup144 dkup143 dkup142 dkup141 dkup140 dpsbkr15 dkup157 dkup156 dkup155 dkup154 dkup153 dkup152 dkup151 dkup150 dsar_0 dmac_0 ddar_0 dofr_0 dtcr_0 dbsr_0 bkszh31 bkszh30 bkszh29 bkszh28 bkszh27 bkszh26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bksz h18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dmdr_0 dte dacke tende ? dreqs nrd ? ? act ? ? ? errf ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dacr_0 ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 darie ? ? dara4 dara3 dara2 dara1 dara0 dsar_1 dmac_1 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1017 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ddar_1 dmac_1 dofr_1 dtcr_1 dbsr_1 bkszh31 bkszh30 bksz h29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bkszh 18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dmdr_1 dte dacke tende ? dreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 md s0 tseie ? esie dtie dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dacr_1 ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 darie ? ? dara4 dara3 dara2 dara1 dara0 dsar_2 dmac_2 ddar_2 dofr_2 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1018 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dtcr_2 dmac_2 dbsr_2 bkszh31 bkszh30 bksz h29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bkszh 18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 dmdr_2 dte dacke tende ? dreqs nrd ? ? act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dacr_2 ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 darie ? ? dara4 dara3 dara2 dara1 dara0 dsar_3 dmac_3 ddar_3 dofr_3 dtcr_3 dbsr_3 bkszh31 bkszh30 bksz h29 bkszh28 bkszh27 bksz h26 bkszh25 bkszh24 bkszh23 bkszh22 bkszh 21 bkszh20 bkszh19 bkszh 18 bkszh17 bkszh16 bksz15 bksz14 bksz13 bksz12 bksz11 bksz10 bksz9 bksz8 bksz7 bksz6 bksz5 bksz4 bksz3 bksz2 bksz1 bksz0 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1019 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dmdr_3 dte dacke tende ? dreqs nrd ? ? dmac_3 act ? ? ? ? ? esif dtif dtsz1 dtsz0 mds1 mds0 tseie ? esie dtie dtf1 dtf0 dta ? ? dmap2 dmap1 dmap0 dacr_3 ams dirs ? ? ? rptie ars1 ars0 ? ? sat1 sat0 ? ? dat1 dat0 sarie ? ? sara4 sara3 sara2 sara1 sara0 darie ? ? dara4 dara3 dara2 dara1 dara0 dmrsr_0 dmac_0 dmrsr_1 dmac_1 dmrsr_2 dmac_2 dmrsr_3 dmac_3 ipra ? ipra14 ipra13 ipra12 ? ipra10 ipra9 ipra8 intc ? ipra6 ipra5 ipra4 ? ipra2 ipra1 ipra0 iprb ? iprb14 iprb13 iprb12 ? iprb10 iprb9 iprb8 ? iprb6 iprb5 iprb4 ? iprb2 iprb1 iprb0 iprc ? iprc14 iprc13 iprc 12 ? iprc10 iprc9 iprc8 ? iprc6 iprc5 iprc4 ? iprc2 iprc1 iprc0 iprd ? iprd14 iprd13 iprd 12 ? iprd10 iprd9 iprd8 ? iprd6 iprd5 iprd4 ? iprd2 iprd1 iprd0 ipre ? ? ? ? ? ipre10 ipre9 ipre8 ? ? ? ? ? ? ? ? iprf ? ? ? ? ? iprf10 iprf9 iprf8 ? iprf6 iprf5 iprf4 ? iprf2 iprf1 iprf0 iprg ? iprg14 iprg13 iprg12 ? iprg10 iprg9 iprg8 ? iprg6 iprg5 iprg4 ? iprg2 iprg1 iprg0 iprh ? iprh14 iprh13 iprh 12 ? iprh10 iprh9 iprh8 ? iprh6 iprh5 iprh4 ? iprh2 iprh1 iprh0 ipri ? ipri14 ipri13 ipri 12 ? ipri10 ipri9 ipri8 ? ipri6 ipri5 ipri4 ? ipri2 ipri1 ipri0 iprk ? iprk14 iprk13 iprk12 ? ? ? ? ? iprk6 iprk5 iprk4 ? iprk2 iprk1 iprk0 iprl ? iprl14 iprl13 ipr l12 ? iprl10 iprl9 iprl8 ? iprl6 iprl5 iprl4 ? iprl2 iprl1 iprl0 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1020 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ? iprm14 iprm13 iprm12 ? ip rm10 iprm9 iprm8 intc iprm ? iprm6 iprm5 iprm4 ? iprm2 iprm1 iprm0 ? iprn14 iprn13 iprn12 ? iprn10 iprn9 iprn8 iprn ? iprn6 iprn5 iprn4 ? iprn2 iprn1 iprn0 ? ipro14 ipro13 ipro12 ? ipro10 ipro9 ipro8 ipro ? ipro6 ipro5 ipro4 ? ? ? ? iprq ? ? ? ? ? ? ? ? ? iprq6 iprq5 iprq4 ? iprq2 iprq1 iprq0 iprr ? iprr14 iprr13 iprr12 ? iprr10 iprr9 iprr8 ? iprr6 iprr5 iprr4 ? iprr2 iprr1 iprr0 iscrh irq15sr irq15sf irq14sr irq14s f irq13sr irq13sf irq12sr irq12sf irq11sr irq11sf irq10sr irq10sf irq9sr irq9sf ir q8sr irq8sf iscrl irq7sr irq7sf irq6sr irq6sf irq5sr irq5sf irq4sr irq4sf irq3sr irq3sf irq2sr irq2sf irq1sr irq1 sf irq0sr irq0sf dtcvbr bsc abwcr abwh7 abwh6 abwh5 abwh4 abwh3 abwh2 abwh1 abwh0 abwl7 abwl6 abwl5 abwl4 abw l3 abwl2 abwl1 abwl0 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 ? ? ? ? ? ? ? ? wtcra ? w72 w71 w70 ? w62 w61 w60 ? w52 w51 w50 ? w42 w41 w40 wtcrb ? w32 w31 w30 ? w22 w21 w20 ? w12 w11 w10 ? w02 w01 w00 rdncr rdn7 rdn6 rdn5 rdn4 rdn3 rdn2 rdn1 rdn0 ? ? ? ? ? ? ? ? csacr csxh7 csxh6 csxh5 csxh 4 csxh3 csxh2 csxh1 csxh0 csxt7 csxt6 csxt 5 csxt4 csxt3 csxt 2 csxt1 csxt0 idlcr idls3 idls2 idls 1 idls0 idlcb1 idlcb0 idlca1 idlca0 idlsel7 idlsel6 idlsel5 idlsel4 idlsel3 idlsel2 idlsel1 idlsel0 bcr1 brle breqoe ? ? ? ? wdbe waite dkc ? ? ? ? ? ? ? bcr2 ? ? ? ibccs ? ? ? pwdbe section 25 list of registers rev. 1.00 sep. 13, 2007 page 1021 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module endiancr le7 le6 le5 le4 le3 le2 ? ? bsc sramcr bcsel7 bcsel6 bcsel5 bcse l4 bcsel3 bcsel2 bcsel1 bcsel0 ? ? ? ? ? ? ? ? bromcr bsrm0 bsts02 bsts01 bsts00 ? ? bswd01 bswd00 bsrm1 bsts12 bsts11 bst s10 ? ? bswd11 bswd10 mpxcr mpxe7 mpxe6 mpxe5 mpxe4 mpxe3 ? ? ? ? ? ? ? ? ? ? addex ramer ? ? ? ? rams ram2 ram1 ram0 mdcr ? ? ? ? mds3 mds2 mds1 mds0 system ? ? ? ? ? ? ? ? syscr ? ? macs ? fetchmd ? expe rame ? ? ? ? ? ? dtcmd ? sckcr pstop1 ? posel1 ? ? ick2 ick1 ick0 ? pck2 pck1 pck0 ? bck2 bck1 bck0 sbycr ssby ope ? sts4 sts3 sts2 sts1 sts0 slpie ? ? ? ? ? ? ? mstpcra acse mstpa14 mstpa13 mstpa12 mstpa11 mstpa10 mstpa9 mstpa8 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 mstpcrb mstpb15 mstpb14 mstpb13 mstpb 12 mstpb11 mstpb10 mstpb9 mstpb8 mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 mstpcrc mstpc15 mstpc14 mstpc13 mstpc 12 mstpc11 mstpc10 mstpc9 mstpc8 mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstp c2 mstpc1 mstpc0 fccs ? ? ? fler ? ? ? sco flash fpcs ? ? ? ? ? ? ? ppvs fecs ? ? ? ? ? ? ? epvb fkey k7 k6 k5 k4 k3 k2 k1 k0 fmats ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 ftdar tder tda6 tda5 tda4 tda3 tda2 tda1 tda0 dpsbycr dpsby iokeep ramcut2 ramcut1 ? ? ? ramcut0 system dpswcr ? ? wtsts5 wtsts4 wtst s3 wtsts2 wtsts1 wtsts0 dpsier ? ? ? ? dirq3e dirq2e dirq1e dirq0e dpsifr dnmif ? ? ? dirq3f dirq2f dirq1f dirq0f dpsiegr dnmieg ? ? ? dirq3eg dirq2eg dirq1eg dirq0eg rstsr dpsrstf ? ? ? ? ? ? ? section 25 list of registers rev. 1.00 sep. 13, 2007 page 1022 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module semr_2 ? ? ? ? abcs acs2 acs1 acs0 sci_2 smr_3 * c/ a (gm) chr (blk) pe (pe) o/ e (o/e) stop (bcp1) mp (bcp0) cks1 cks0 sci_3 brr_3 scr_3* tie rie te re mpie teie cke1 cke0 tdr_3 ssr_3* tdre rdrf orer fer (ers) per tend mpb mpbt rdr_3 scmr_3 ? ? ? ? sdir sinv ? smif smr_4 * c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 sci_4 brr_4 scr_4 * tie rie te re mpie teie cke1 cke0 tdr_4 ssr_4 * tdre rdrf orer fer (ers) per tend mpb mpbt rdr_4 scmr_4 ? ? ? ? sdir sinv ? smif iccra_0 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2_0 iccrb_0 bbsy scp sdao ? sclo ? iicrst ? icmr_0 ? wait ? ? bc wp bc2 bc1 bc0 icier_0 tie teie rie naki e stie acke ackbr ackbt icsr_0 tdre tend rdrf nackf stop al aas adz sar_0 sva6 sva5 sva4 sva3 sva2 sva1 sva0 ? icdrt_0 icdrr_0 iccra_1 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2_1 iccrb_1 bbsy scp sdao ? sclo ? iicrst ? icmr_1 ? wait ? ? bc wp bc2 bc1 bc0 icier_1 tie teie rie naki e stie acke ackbr ackbt icsr_1 tdre tend rdrf nackf stop al aas adz sar_1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 ? icdrt_1 icdrr_1 tcr_2 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_2 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1023 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcr_3 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_3 tcsr_2 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_2 tcsr_3 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_3 tcora_2 tmr_2 tcora_3 tmr_3 tcorb_2 tmr_2 tcorb_3 tmr_3 tcnt_2 tmr_2 tcnt_3 tmr_3 tccr_2 ? ? ? ? tmris ? icks1 icks0 tmr_2 tccr_3 ? ? ? ? tmris ? icks1 icks0 tmr_3 tcr_4 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_4 tmdr_4 ? ? ? ? md3 md2 md1 md0 tior_4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_4 ttge ? tcieu tciev ? ? tgieb tgiea tsr_4 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_4 tgra_4 tgrb_4 tcr_5 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_5 tmdr_5 ? ? ? ? md3 md2 md1 md0 tior_5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_5 ttge ? tcieu tciev ? ? tgieb tgiea tsr_5 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_5 tgra_5 tgrb_5 dtcera dtcea15 dtcea14 dt cea13 dtcea12 dtcea11 dtc ea10 dtcea9 dtcea8 intc dtcea7 dtcea6 dtcea5 dtcea4 dtcea3 dtcea2 dtcea1 dtcea0 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1024 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dtcerb dtceb15 ? dtceb13 dtceb12 dt ceb11 dtceb10 dtceb9 dtceb8 intc dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 dtcerc dtcec15 dtcec14 dtcec13 dtcec 12 dtcec11 dtcec10 dtcec9 dtcec8 dtcec7 dtcec6 dtcec5 dt cec4 dtcec3 dtcec2 ? ? dtcerd ? ? dtced13 dtced12 dtced11 dtced10 ? ? ? ? dtced5 dtced4 dtced3 dtced2 dtced1 dtced0 dtcere dtcee15 dtcee14 dtcee13 dtcee 12 dtcee11 dtcee10 dtcee9 dtcee8 dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 dtcef15 dtcef14 ? ? dtcef11 dtcef10 dtcef9 ? dtcerf ? ? ? ? ? ? ? ? dtccr ? ? ? rrs rchne ? ? err intcr ? ? intm1 in tm0 nmieg ? ? ? cpupcr cpupce dtcp2 dtcp1 dtcp 0 ipsete cpup2 cpup1 cpup0 ier irq15e irq14e irq13e irq12e irq11e irq10e irq9e irq8e irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e isr irq15f irq14f irq13f irq12f irq11f irq10f irq9f irq8f irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f port1 p17 p16 p15 p14 p13 p12 p11 p10 i/o port port2 p27 p26 p25 p24 p23 p22 p21 p20 port3 p37 p36 p35 p34 p33 p32 p31 p30 port4 p47 p46 p45 p44 ? ? ? ? port5 p57 p56 p55 p54 p53 p52 p51 p50 port6 p67 p66 p65 p64 p63 p62 p61 p60 porta pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portc ? ? pc5 pc4 pc3 pc2 pc1 pc0 portd pd7 pd6 pd5 pd 4 pd3 pd2 pd1 pd0 porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 portf pf7 pf6 pf5 pf 4 pf3 pf2 pf1 pf0 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr p3dr p37dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr p6dr p67dr p66dr p65dr p64dr p63dr p62dr p61dr p60dr padr pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr section 25 list of registers rev. 1.00 sep. 13, 2007 page 1025 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr i/o port pcdr ? ? pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr smr_2 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 sci_2 brr_2 scr_2 * 1 tie rie te re mpie teie cke1 cke0 tdr_2 ssr_2 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt rdr_2 scmr_2 ? ? ? ? sdir sinv ? smif dadr0 d/a dadr1 dacr01 daoe1 daoe0 dae ? ? ? ? ? pcr g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 ppg_0 pmr g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov nderh nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 nderl nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 podrh pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 podrl pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 ndrh * 2 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 ndrl * 2 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 ndrh * 2 ? ? ? ? ndr11 ndr10 ndr9 ndr8 ndrl * 2 ? ? ? ? ndr3 ndr2 ndr1 ndr0 smr_0 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 sci_0 brr_0 scr_0 * 1 tie rie te re mpie teie cke1 cke0 tdr_0 ssr_0 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt rdr_0 scmr_0 ? ? ? ? sdir sinv ? smif section 25 list of registers rev. 1.00 sep. 13, 2007 page 1026 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module smr_1 * 1 c/ a (gm) chr (blk) pe (pe) o/ e (o/ e ) stop (bcp1) mp (bcp0) cks1 cks0 sci_1 brr_1 scr_1 * 1 tie rie te re mpie teie cke1 cke0 tdr_1 ssr_1 * 1 tdre rdrf orer fer (ers) per tend mpb mpbt rdr_1 scmr_1 ? ? ? ? sdir sinv ? smif addra_0 a/d_0 addrb_0 addrc_0 addrd_0 addre_0 addrf_0 addrg_0 addrh_0 adcsr_0 adf adie adst ? ch3 ch2 ch1 ch0 adcr_0 trgs1 trgs0 scane sc ans cks1 cks0 ? extrgs tcsr ovf wt/ it tme ? ? cks2 cks1 cks0 wdt tcnt rstcsr wovf rste ? ? ? ? ? ? tcr_0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_0 tcr_1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr_1 tcsr_0 cmfb cmfa ovf adte os3 os2 os1 os0 tmr_0 tcsr_1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr_1 tcora_0 tmr_0 tcora_1 tmr_1 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1027 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcorb_0 tmr_0 tcorb_1 tmr_1 tcnt_0 tmr_0 tcnt_1 tmr_1 tccr_0 ? ? ? ? tmris ? icks1 icks0 tmr_0 tccr_1 ? ? ? ? tmris ? icks1 icks0 tmr_1 tstr ? ? cst5 cst4 cst3 cst2 cst1 cst0 tpu tsyr ? ? sync5 sync4 sync3 sync2 sync1 sync0 tcr_0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_0 tmdr_0 ? ? bfb bfa md3 md2 md1 md0 tiorh_0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_0 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 tgra_0 tgrb_0 tgrc_0 tgrd_0 tcr_1 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_1 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu tciev ? ? tgieb tgiea tsr_1 tcfd ? tcfu tcfv tgfd ? tgfb tgfa tcnt_1 tgra_1 tgrb_1 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1028 of 1102 rej09b0365-0100 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcr_2 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 tpu_2 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu tciev ? ? tgieb tgiea tsr_2 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_2 tgra_2 tgrb_2 tcr_3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_3 tmdr_3 ? ? bfb bfa md3 md2 md1 md0 tiorh_3 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_3 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_3 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_3 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_3 tgra_3 tgrb_3 tgrc_3 tgrd_3 section 25 list of registers rev. 1.00 sep. 13, 2007 page 1029 of 1102 rej09b0365-0100 notes: 1. parts of the bit functions differ in normal mode and the smart card interface. 2. when the same output trigger is specifie d for pulse output groups 2 and 3 by the pcr setting, the ndrh address is h'fff7c. when di fferent output triggers are specified, the ndrh addresses for pulse output groups 2 and 3 are h'fff7e and h'fff7c, respectively. similarly, when the same output trigger is specified for pulse output groups 0 and 1 by the pcr setting, the ndrl addr ess is h'fff7d. when different output triggers are specified, the ndrl addre sses for pulse output groups 0 and 1 are h'fff7f and h'fff7d, respectively. when the same output trigger is specified for pulse output groups 6 and 7 by the pcr setting, the ndrh address is h'ff63c. when diffe rent output triggers are specified, the ndrh addresses for pulse output groups 6 and 7 are h'ff63e and h'ff63c, respectively. when the same output trigger is specified fo r pulse output groups 4 and 5 by the pcr setting, the ndrl address is h'ff63d. when di fferent output triggers are specified, the ndrl addresses for pulse output groups 4 and 5 are h'ff63f and h'ff63d, respectively. section 25 list of registers rev. 1.00 sep. 13, 2007 page 1030 of 1102 rej09b0365-0100 25.3 register states in each operating mode register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module tcr_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcr_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcsr_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcsr_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcora_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcora_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcorb_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcorb_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tcnt_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tcnt_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 tccr_4 initialized ? ? ? ? initialized * 1 initialized tmr_4 tccr_5 initialized ? ? ? ? initialized * 1 initialized tmr_5 crccr initialized ? ? ? ? initialized * 1 initialized crc crcdir initialized ? ? ? ? initialized * 1 initialized crcdor initialized ? ? ? ? initialized * 1 initialized tcr_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcr_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcsr_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcsr_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcora_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcora_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcorb_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcorb_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tcnt_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tcnt_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 tccr_6 initialized ? ? ? ? initialized * 1 initialized tmr_6 tccr_7 initialized ? ? ? ? initialized * 1 initialized tmr_7 addra_1 initialized ? ? ? ? initialized * 1 initialized a/d_1 addrb_1 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1031 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module addrc_1 initialized ? ? ? ? initialized * 1 initialized a/d_1 addrd_1 initialized ? ? ? ? initialized * 1 initialized addre_2 initialized ? ? ? ? initialized * 1 initialized a/d_2 addrf_2 initialized ? ? ? ? initialized * 1 initialized addrg_2 initialized ? ? ? ? initialized * 1 initialized addrh_2 initialized ? ? ? ? initialized * 1 initialized addre_1 initialized ? ? ? ? initialized * 1 initialized a/d_1 addrf_1 initialized ? ? ? ? initialized * 1 initialized addrg_1 initialized ? ? ? ? initialized * 1 initialized addrh_1 initialized ? ? ? ? initialized * 1 initialized addra_2 initialized ? ? ? ? initialized * 1 initialized a/d_2 addrb_2 initialized ? ? ? ? initialized * 1 initialized addrc_2 initialized ? ? ? ? initialized * 1 initialized addrd_2 initialized ? ? ? ? initialized * 1 initialized adcsr_1 initialized ? ? ? ? initialized * 1 initialized a/d_1 adcr_1 initialized ? ? ? ? initialized * 1 initialized adcsr_2 initialized ? ? ? ? initialized * 1 initialized a/d_2 adcr_2 initialized ? ? ? ? initialized * 1 initialized portn ? ? ? ? ? ? ? i/o port pnicr initialized ? ? ? ? initialized * 1 initialized smr_5 initialized ? ? ? ? initialized * 1 initialized sci_5 brr_5 initialized ? ? ? ? initialized * 1 initialized scr_5 initialized ? ? ? ? initialized * 1 initialized tdr_5 initialized initialized ? in itialized initialized initialized * 1 initialized ssr_5 initialized initialized ? in itialized initialized initialized * 1 initialized rdr_5 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_5 initialized ? ? ? ? initialized * 1 initialized semr_5 initialized ? ? ? ? initialized * 1 initialized ircr initialized ? ? ? ? initialized * 1 initialized smr_6 initialized ? ? ? ? initialized * 1 initialized sci_6 brr_6 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1032 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module scr_6 initialized ? ? ? ? initialized * 1 initialized sci_6 tdr_6 initialized initialized ? in itialized initialized initialized * 1 initialized ssr_6 initialized initialized ? in itialized initialized initialized * 1 initialized rdr_6 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_6 initialized ? ? ? ? initialized * 1 initialized semr_6 initialized ? ? ? ? initialized * 1 initialized pcr_1 initialized ? ? ? ? initialized * 1 initialized ppg pmr_1 initialized ? ? ? ? initialized * 1 initialized nderh_1 initialized ? ? ? ? initialized * 1 initialized nderl_1 initialized ? ? ? ? initialized * 1 initialized podrh_1 initialized ? ? ? ? initialized * 1 initialized podrl_1 initialized ? ? ? ? initialized * 1 initialized ndrh_1 initialized ? ? ? ? initialized * 1 initialized ndrl_1 initialized ? ? ? ? initialized * 1 initialized iccra_2 initialized ? ? ? ? initialized * 1 initialized iic2_2 iccrb_2 initialized ? ? ? ? initialized * 1 initialized icmr_2 initialized ? ? ? ? initialized * 1 initialized icier_2 initialized ? ? ? ? initialized * 1 initialized icsr_2 initialized ? ? ? ? initialized * 1 initialized sar_2 initialized ? ? ? ? initialized * 1 initialized icdrt_2 initialized ? ? ? ? initialized * 1 initialized icdrr_2 initialized ? ? ? ? initialized * 1 initialized iccra_3 initialized ? ? ? ? initialized * 1 initialized iic2_3 iccrb_3 initialized ? ? ? ? initialized * 1 initialized icmr_3 initialized ? ? ? ? initialized * 1 initialized icier_3 initialized ? ? ? ? initialized * 1 initialized icsr_3 initialized ? ? ? ? initialized * 1 initialized sar_3 initialized ? ? ? ? initialized * 1 initialized icdrt_3 initialized ? ? ? ? initialized * 1 initialized icdrr_3 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1033 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module tstrb initialized ? ? ? ? initialized * 1 initialized tpu (unit 1) tsyrb initialized ? ? ? ? initialized * 1 initialized tcr_6 initialized ? ? ? ? initialized * 1 initialized tpu_6 tmdr_6 initialized ? ? ? ? initialized * 1 initialized tiorh_6 initialized ? ? ? ? initialized * 1 initialized tiorl_6 initialized ? ? ? ? initialized * 1 initialized tier_6 initialized ? ? ? ? initialized * 1 initialized tsr_6 initialized ? ? ? ? initialized * 1 initialized tcnt_6 initialized ? ? ? ? initialized * 1 initialized tgra_6 initialized ? ? ? ? initialized * 1 initialized tgrb_6 initialized ? ? ? ? initialized * 1 initialized tgrc_6 initialized ? ? ? ? initialized * 1 initialized tgrd_6 initialized ? ? ? ? initialized * 1 initialized tcr_7 initialized ? ? ? ? initialized * 1 initialized tpu_7 tmdr_7 initialized ? ? ? ? initialized * 1 initialized tior_7 initialized ? ? ? ? initialized * 1 initialized tier_7 initialized ? ? ? ? initialized * 1 initialized tsr_7 initialized ? ? ? ? initialized * 1 initialized tcnt_7 initialized ? ? ? ? initialized * 1 initialized tgra_7 initialized ? ? ? ? initialized * 1 initialized tgrb_7 initialized ? ? ? ? initialized * 1 initialized tcr_8 initialized ? ? ? ? initialized * 1 initialized tpu_8 tmdr_8 initialized ? ? ? ? initialized * 1 initialized tior_8 initialized ? ? ? ? initialized * 1 initialized tier_8 initialized ? ? ? ? initialized * 1 initialized tsr_8 initialized ? ? ? ? initialized * 1 initialized tcnt_8 initialized ? ? ? ? initialized * 1 initialized tgra_8 initialized ? ? ? ? initialized * 1 initialized tgrb_8 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1034 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module tcr_9 initialized ? ? ? ? initialized * 1 initialized tpu_9 tmdr_9 initialized ? ? ? ? initialized * 1 initialized tiorh_9 initialized ? ? ? ? initialized * 1 initialized tiorl_9 initialized ? ? ? ? initialized * 1 initialized tier_9 initialized ? ? ? ? initialized * 1 initialized tsr_9 initialized ? ? ? ? initialized * 1 initialized tcnt_9 initialized ? ? ? ? initialized * 1 initialized tgra_9 initialized ? ? ? ? initialized * 1 initialized tgrb_9 initialized ? ? ? ? initialized * 1 initialized tgrc_9 initialized ? ? ? ? initialized * 1 initialized tgrd_9 initialized ? ? ? ? initialized * 1 initialized tcr_10 initialized ? ? ? ? initialized * 1 initialized tpu_10 tmdr_10 initialized ? ? ? ? initialized * 1 initialized tior_10 initialized ? ? ? ? initialized * 1 initialized tier_10 initialized ? ? ? ? initialized * 1 initialized tsr_10 initialized ? ? ? ? initialized * 1 initialized tcnt_10 initialized ? ? ? ? initialized * 1 initialized tgra_10 initialized ? ? ? ? initialized * 1 initialized tgrb_10 initialized ? ? ? ? initialized * 1 initialized tcr_11 initialized ? ? ? ? initialized * 1 initialized tpu_11 tmdr_11 initialized ? ? ? ? initialized * 1 initialized tior_11 initialized ? ? ? ? initialized * 1 initialized tier_11 initialized ? ? ? ? initialized * 1 initialized tsr_11 initialized ? ? ? ? initialized * 1 initialized tcnt_11 initialized ? ? ? ? initialized * 1 initialized tgra_11 initialized ? ? ? ? initialized * 1 initialized tgrb_11 initialized ? ? ? ? initialized * 1 initialized p1ddr initialized ? ? ? ? initialized * 1 initialized i/o port p2ddr initialized ? ? ? ? initialized * 1 initialized p3ddr initialized ? ? ? ? initialized * 1 initialized p6ddr initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1035 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module paddr initialized ? ? ? ? initialized * 1 initialized i/o port pbddr initialized ? ? ? ? initialized * 1 initialized pcddr initialized ? ? ? ? initialized * 1 initialized pdddr initialized ? ? ? ? initialized * 1 initialized peddr initialized ? ? ? ? initialized * 1 initialized pfddr initialized ? ? ? ? initialized * 1 initialized p1icr initialized ? ? ? ? initialized * 1 initialized p2icr initialized ? ? ? ? initialized * 1 initialized p3icr initialized ? ? ? ? initialized * 1 initialized p4icr initialized ? ? ? ? initialized * 1 initialized p5icr initialized ? ? ? ? initialized * 1 initialized p6icr initialized ? ? ? ? initialized * 1 initialized paicr initialized ? ? ? ? initialized * 1 initialized pbicr initialized ? ? ? ? initialized * 1 initialized pcicr initialized ? ? ? ? initialized * 1 initialized pdicr initialized ? ? ? ? initialized * 1 initialized peicr initialized ? ? ? ? initialized * 1 initialized pficr initialized ? ? ? ? initialized * 1 initialized porth ? ? ? ? ? ? ? porti ? ? ? ? ? ? ? portj ? ? ? ? ? ? ? portk ? ? ? ? ? ? ? phdr initialized ? ? ? ? initialized * 1 initialized pidr initialized ? ? ? ? initialized * 1 initialized pjdr initialized ? ? ? ? initialized * 1 initialized pkdr initialized ? ? ? ? initialized * 1 initialized phddr initialized ? ? ? ? initialized * 1 initialized piddr initialized ? ? ? ? initialized * 1 initialized pjddr initialized ? ? ? ? initialized * 1 initialized pkddr initialized ? ? ? ? initialized * 1 initialized phicr initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1036 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module piicr initialized ? ? ? ? initialized * 1 initialized i/o port pjicr initialized ? ? ? ? initialized * 1 initialized pkicr initialized ? ? ? ? initialized * 1 initialized pdpcr initialized ? ? ? ? initialized * 1 initialized pepcr initialized ? ? ? ? initialized * 1 initialized pfpcr initialized ? ? ? ? initialized * 1 initialized phpcr initialized ? ? ? ? initialized * 1 initialized pipcr initialized ? ? ? ? initialized * 1 initialized pjpcr initialized ? ? ? ? initialized * 1 initialized pkpcr initialized ? ? ? ? initialized * 1 initialized p2odr initialized ? ? ? ? initialized * 1 initialized pfodr initialized ? ? ? ? initialized * 1 initialized pfcr0 initialized ? ? ? ? initialized * 1 initialized pfcr1 initialized ? ? ? ? initialized * 1 initialized pfcr2 initialized ? ? ? ? initialized * 1 initialized pfcr4 initialized ? ? ? ? initialized * 1 initialized pfcr6 initialized ? ? ? ? initialized * 1 initialized pfcr7 initialized ? ? ? ? initialized * 1 initialized pfcr9 initialized ? ? ? ? initialized * 1 initialized pfcra initialized ? ? ? ? initialized * 1 initialized pfcrb initialized ? ? ? ? initialized * 1 initialized pfcrc initialized ? ? ? ? initialized * 1 initialized pfcrd initialized ? ? ? ? initialized * 1 initialized ssier initialized ? ? ? ? initialized * 1 initialized intc dpsbkr0 initialized ? ? ? ? ? initialized system dpsbkr1 initialized ? ? ? ? ? initialized dpsbkr2 initialized ? ? ? ? ? initialized dpsbkr3 initialized ? ? ? ? ? initialized dpsbkr4 initialized ? ? ? ? ? initialized dpsbkr5 initialized ? ? ? ? ? initialized dpsbkr6 initialized ? ? ? ? ? initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1037 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module dpsbkr7 initialized ? ? ? ? ? initialized system dpsbkr8 initialized ? ? ? ? ? initialized dpsbkr9 initialized ? ? ? ? ? initialized dpsbkr10 initialized ? ? ? ? ? initialized dpsbkr11 initialized ? ? ? ? ? initialized dpsbkr12 initialized ? ? ? ? ? initialized dpsbkr13 initialized ? ? ? ? ? initialized dpsbkr14 initialized ? ? ? ? ? initialized dpsbkr15 initialized ? ? ? ? ? initialized dsar_0 initialized ? ? ? ? initialized * 1 initialized dmac_0 ddar_0 initialized ? ? ? ? initialized * 1 initialized dofr_0 initialized ? ? ? ? initialized * 1 initialized dtcr_0 initialized ? ? ? ? initialized * 1 initialized dbsr_0 initialized ? ? ? ? initialized * 1 initialized dmdr_0 initialized ? ? ? ? initialized * 1 initialized dacr_0 initialized ? ? ? ? initialized * 1 initialized dsar_1 initialized ? ? ? ? initialized * 1 initialized dmac_1 ddar_1 initialized ? ? ? ? initialized * 1 initialized dofr_1 initialized ? ? ? ? initialized * 1 initialized dtcr_1 initialized ? ? ? ? initialized * 1 initialized dbsr_1 initialized ? ? ? ? initialized * 1 initialized dmdr_1 initialized ? ? ? ? initialized * 1 initialized dacr_1 initialized ? ? ? ? initialized * 1 initialized dsar_2 initialized ? ? ? ? initialized * 1 initialized dmac_2 ddar_2 initialized ? ? ? ? initialized * 1 initialized dofr_2 initialized ? ? ? ? initialized * 1 initialized dtcr_2 initialized ? ? ? ? initialized * 1 initialized dbsr_2 initialized ? ? ? ? initialized * 1 initialized dmdr_2 initialized ? ? ? ? initialized * 1 initialized dacr_2 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1038 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module dsar_3 initialized ? ? ? ? initialized * 1 initialized dmac_3 ddar_3 initialized ? ? ? ? initialized * 1 initialized dofr_3 initialized ? ? ? ? initialized * 1 initialized dtcr_3 initialized ? ? ? ? initialized * 1 initialized dbsr_3 initialized ? ? ? ? initialized * 1 initialized dmdr_3 initialized ? ? ? ? initialized * 1 initialized dacr_3 initialized ? ? ? ? initialized * 1 initialized dmrsr_0 initialized ? ? ? ? initialized * 1 initialized dmac_0 dmrsr_1 initialized ? ? ? ? initialized * 1 initialized dmac_1 dmrsr_2 initialized ? ? ? ? initialized * 1 initialized dmac_2 dmrsr_3 initialized ? ? ? ? initialized * 1 initialized dmac_3 ipra initialized ? ? ? ? initialized * 1 initialized intc iprb initialized ? ? ? ? initialized * 1 initialized iprc initialized ? ? ? ? initialized * 1 initialized iprd initialized ? ? ? ? initialized * 1 initialized ipre initialized ? ? ? ? initialized * 1 initialized iprf initialized ? ? ? ? initialized * 1 initialized iprg initialized ? ? ? ? initialized * 1 initialized iprh initialized ? ? ? ? initialized * 1 initialized ipri initialized ? ? ? ? initialized * 1 initialized iprk initialized ? ? ? ? initialized * 1 initialized iprl initialized ? ? ? ? initialized * 1 initialized iprm initialized ? ? ? ? initialized * 1 initialized iprn initialized ? ? ? ? initialized * 1 initialized ipro initialized ? ? ? ? initialized * 1 initialized iprq initialized ? ? ? ? initialized * 1 initialized iprr initialized ? ? ? ? initialized * 1 initialized iscrh initialized ? ? ? ? initialized * 1 initialized iscrl initialized ? ? ? ? initialized * 1 initialized dtcvbr initialized ? ? ? ? initialized * 1 initialized bsc abwcr initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1039 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module astcr initialized ? ? ? ? initialized * 1 initialized bsc wtcra initialized ? ? ? ? initialized * 1 initialized wtcrb initialized ? ? ? ? initialized * 1 initialized rdncr initialized ? ? ? ? initialized * 1 initialized csacr initialized ? ? ? ? initialized * 1 initialized idlcr initialized ? ? ? ? initialized * 1 initialized bcr1 initialized ? ? ? ? initialized * 1 initialized bcr2 initialized ? ? ? ? initialized * 1 initialized endiancr initialized ? ? ? ? initialized * 1 initialized sramcr initialized ? ? ? ? initialized * 1 initialized bromcr initialized ? ? ? ? initialized * 1 initialized mpxcr initialized ? ? ? ? initialized * 1 initialized ramer initialized ? ? ? ? initialized * 1 initialized mdcr initialized ? ? ? ? initialized * 1 initialized system syscr initialized ? ? ? ? initialized * 1 initialized sckcr initialized ? ? ? ? initialized * 1 initialized sbycr initialized ? ? ? ? initialized * 1 initialized mstpcra initialized ? ? ? ? initialized * 1 initialized mstpcrb initialized ? ? ? ? initialized * 1 initialized mstpcrc initialized ? ? ? ? initialized * 1 initialized fccs initialized ? ? ? ? initialized * 1 initialized flash fpcs initialized ? ? ? ? initialized * 1 initialized fecs initialized ? ? ? ? initialized * 1 initialized fkey initialized ? ? ? ? initialized * 1 initialized fmats initialized ? ? ? ? initialized * 1 initialized ftdar initialized ? ? ? ? initialized * 1 initialized dpsbycr initialized ? ? ? ? ? initialized system dpswcr initialized ? ? ? ? ? initialized dpsier initialized ? ? ? ? ? initialized dpsifr initialized ? ? ? ? ? initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1040 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module dpsiegr initialized ? ? ? ? ? initialized system rstsr initialized ? ? ? ? ? initialized semr_2 initialized ? ? ? ? initialized * 1 initialized sci_2 smr_3 initialized ? ? ? ? initialized * 1 initialized sci_3 brr_3 initialized ? ? ? ? initialized * 1 initialized scr_3 initialized ? ? ? ? initialized * 1 initialized tdr_3 initialized initialized ? in itialized initialized initialized * 1 initialized ssr_3 initialized initialized ? in itialized initialized initialized * 1 initialized rdr_3 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_3 initialized ? ? ? ? initialized * 1 initialized smr_4 initialized ? ? ? ? initialized * 1 initialized sci_4 brr_4 initialized ? ? ? ? initialized * 1 initialized scr_4 initialized ? ? ? ? initialized * 1 initialized tdr_4 initialized initialized ? in itialized initialized initialized * 1 initialized ssr_4 initialized initialized ? in itialized initialized initialized * 1 initialized rdr_4 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_4 initialized ? ? ? ? initialized * 1 initialized iccra_0 initialized ? ? ? ? initialized * 1 initialized iic2_0 iccrb_0 initialized ? ? ? ? initialized * 1 initialized icmr_0 initialized ? ? ? ? initialized * 1 initialized icier_0 initialized ? ? ? ? initialized * 1 initialized icsr_0 initialized ? ? ? ? initialized * 1 initialized sar_0 initialized ? ? ? ? initialized * 1 initialized icdrt_0 initialized ? ? ? ? initialized * 1 initialized icdrr_0 initialized ? ? ? ? initialized * 1 initialized iccra_1 initialized ? ? ? ? initialized * 1 initialized iic2_1 iccrb_1 initialized ? ? ? ? initialized * 1 initialized icmr_1 initialized ? ? ? ? initialized * 1 initialized icier_1 initialized ? ? ? ? initialized * 1 initialized icsr_1 initialized ? ? ? ? initialized * 1 initialized sar_1 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1041 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module icdrt_1 initialized ? ? ? ? initialized * 1 initialized iic2_1 icdrr_1 initialized ? ? ? ? initialized * 1 initialized tcr_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcr_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcsr_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcsr_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcora_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcora_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcorb_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcorb_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcnt_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tcnt_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tccr_2 initialized ? ? ? ? initialized * 1 initialized tmr_2 tccr_3 initialized ? ? ? ? initialized * 1 initialized tmr_3 tcr_4 initialized ? ? ? ? initialized * 1 initialized tpu_4 tmdr_4 initialized ? ? ? ? initialized * 1 initialized tior_4 initialized ? ? ? ? initialized * 1 initialized tier_4 initialized ? ? ? ? initialized * 1 initialized tsr_4 initialized ? ? ? ? initialized * 1 initialized tcnt_4 initialized ? ? ? ? initialized * 1 initialized tgra_4 initialized ? ? ? ? initialized * 1 initialized tgrb_4 initialized ? ? ? ? initialized * 1 initialized tcr_5 initialized ? ? ? ? initialized * 1 initialized tpu_5 tmdr_5 initialized ? ? ? ? initialized * 1 initialized tior_5 initialized ? ? ? ? initialized * 1 initialized tier_5 initialized ? ? ? ? initialized * 1 initialized tsr_5 initialized ? ? ? ? initialized * 1 initialized tcnt_5 initialized ? ? ? ? initialized * 1 initialized tgra_5 initialized ? ? ? ? initialized * 1 initialized tgrb_5 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1042 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module dtcera initialized ? ? ? ? initialized * 1 initialized intc dtcerb initialized ? ? ? ? initialized * 1 initialized dtcerc initialized ? ? ? ? initialized * 1 initialized dtcerd initialized ? ? ? ? initialized * 1 initialized dtcere initialized ? ? ? ? initialized * 1 initialized dtcerf initialized ? ? ? ? initialized * 1 initialized dtccr initialized ? ? ? ? initialized * 1 initialized intcr initialized ? ? ? ? initialized * 1 initialized cpupcr initialized ? ? ? ? initialized * 1 initialized ier initialized ? ? ? ? initialized * 1 initialized isr initialized ? ? ? ? initialized * 1 initialized port1 ? ? ? ? ? ? ? i/o port port2 ? ? ? ? ? ? ? port3 ? ? ? ? ? ? ? port4 ? ? ? ? ? ? ? port5 ? ? ? ? ? ? ? port6 ? ? ? ? ? ? ? porta ? ? ? ? ? ? ? portb ? ? ? ? ? ? ? portc ? ? ? ? ? ? ? portd ? ? ? ? ? ? ? porte ? ? ? ? ? ? ? portf ? ? ? ? ? ? ? p1dr initialized ? ? ? ? initialized * 1 initialized p2dr initialized ? ? ? ? initialized * 1 initialized p3dr initialized ? ? ? ? initialized * 1 initialized p6dr initialized ? ? ? ? initialized * 1 initialized padr initialized ? ? ? ? initialized * 1 initialized pbdr initialized ? ? ? ? initialized * 1 initialized pcdr initialized ? ? ? ? initialized * 1 initialized pddr initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1043 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module pedr initialized ? ? ? ? initialized * 1 initialized i/o port pfdr initialized ? ? ? ? initialized * 1 initialized smr_2 initialized ? ? ? ? initialized * 1 initialized sci_2 brr_2 initialized ? ? ? ? initialized * 1 initialized scr_2 initialized ? ? ? ? initialized * 1 initialized tdr_2 initialized initialized ? in itialized initialized initialized * 1 initialized ssr_2 initialized initialized ? in itialized initialized initialized * 1 initialized rdr_2 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_2 initialized ? ? ? ? initialized * 1 initialized dadr0 initialized ? ? ? ? initialized * 1 initialized d/a dadr1 initialized ? ? ? ? initialized * 1 initialized dacr01 initialized ? ? ? ? initialized * 1 initialized pcr initialized ? ? ? ? initialized * 1 initialized ppg pmr initialized ? ? ? ? initialized * 1 initialized nderh initialized ? ? ? ? initialized * 1 initialized nderl initialized ? ? ? ? initialized * 1 initialized podrh initialized ? ? ? ? initialized * 1 initialized podrl initialized ? ? ? ? initialized * 1 initialized ndrh initialized ? ? ? ? initialized * 1 initialized ndrl initialized ? ? ? ? initialized * 1 initialized smr_0 initialized ? ? ? ? initialized * 1 initialized sci_0 brr_0 initialized ? ? ? ? initialized * 1 initialized scr_0 initialized ? ? ? ? initialized * 1 initialized tdr_0 initialized initialized ? in itialized initialized initialized * 1 initialized ssr_0 initialized initialized ? in itialized initialized initialized * 1 initialized rdr_0 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_0 initialized ? ? ? ? initialized * 1 initialized smr_1 initialized ? ? ? ? initialized * 1 initialized sci_1 brr_1 initialized ? ? ? ? initialized * 1 initialized scr_1 initialized ? ? ? ? initialized * 1 initialized tdr_1 initialized initialized ? in itialized initialized initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1044 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module ssr_1 initialized initialized ? in itialized initialized initialized * 1 initialized sci_1 rdr_1 initialized initialized ? in itialized initialized initialized * 1 initialized scmr_1 initialized ? ? ? ? initialized * 1 initialized addra_0 initialized ? ? ? ? initialized * 1 initialized a/d_0 addrb_0 initialized ? ? ? ? initialized * 1 initialized addrc_0 initialized ? ? ? ? initialized * 1 initialized addrd_0 initialized ? ? ? ? initialized * 1 initialized addre_0 initialized ? ? ? ? initialized * 1 initialized addrf_0 initialized ? ? ? ? initialized * 1 initialized addrg_0 initialized ? ? ? ? initialized * 1 initialized addrh_0 initialized ? ? ? ? initialized * 1 initialized adcsr_0 initialized ? ? ? ? initialized * 1 initialized adcr_0 initialized ? ? ? ? initialized * 1 initialized tcsr initialized ? ? ? ? initialized * 1 initialized wdt tcnt initialized ? ? ? ? initialized * 1 initialized rstcsr initialized ? ? ? ? initialized * 1 initialized tcr_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcr_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcsr_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcsr_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcora_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcora_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcorb_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcorb_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tcnt_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tcnt_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tccr_0 initialized ? ? ? ? initialized * 1 initialized tmr_0 tccr_1 initialized ? ? ? ? initialized * 1 initialized tmr_1 tstr initialized ? ? ? ? initialized * 1 initialized tpu tsyr initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1045 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module tcr_0 initialized ? ? ? ? initialized * 1 initialized tpu_0 tmdr_0 initialized ? ? ? ? initialized * 1 initialized tiorh_0 initialized ? ? ? ? initialized * 1 initialized tiorl_0 initialized ? ? ? ? initialized * 1 initialized tier_0 initialized ? ? ? ? initialized * 1 initialized tsr_0 initialized ? ? ? ? initialized * 1 initialized tcnt_0 initialized ? ? ? ? initialized * 1 initialized tgra_0 initialized ? ? ? ? initialized * 1 initialized tgrb_0 initialized ? ? ? ? initialized * 1 initialized tgrc_0 initialized ? ? ? ? initialized * 1 initialized tgrd_0 initialized ? ? ? ? initialized * 1 initialized tcr_1 initialized ? ? ? ? initialized * 1 initialized tpu_1 tmdr_1 initialized ? ? ? ? initialized * 1 initialized tior_1 initialized ? ? ? ? initialized * 1 initialized tier_1 initialized ? ? ? ? initialized * 1 initialized tsr_1 initialized ? ? ? ? initialized * 1 initialized tcnt_1 initialized ? ? ? ? initialized * 1 initialized tgra_1 initialized ? ? ? ? initialized * 1 initialized tgrb_1 initialized ? ? ? ? initialized * 1 initialized tcr_2 initialized ? ? ? ? initialized * 1 initialized tpu_2 tmdr_2 initialized ? ? ? ? initialized * 1 initialized tior_2 initialized ? ? ? ? initialized * 1 initialized tier_2 initialized ? ? ? ? initialized * 1 initialized tsr_2 initialized ? ? ? ? initialized * 1 initialized tcnt_2 initialized ? ? ? ? initialized * 1 initialized tgra_2 initialized ? ? ? ? initialized * 1 initialized tgrb_2 initialized ? ? ? ? initialized * 1 initialized tcr_3 initialized ? ? ? ? initialized * 1 initialized tpu_3 tmdr_3 initialized ? ? ? ? initialized * 1 initialized tiorh_3 initialized ? ? ? ? initialized * 1 initialized tiorl_3 initialized ? ? ? ? initialized * 1 initialized section 25 list of registers rev. 1.00 sep. 13, 2007 page 1046 of 1102 rej09b0365-0100 register abbreviation reset module stop state sleep all-module- clock-stop software standby deep software standby hardware standby module tier_3 initialized ? ? ? ? initialized * 1 initialized tsr_3 initialized ? ? ? ? initialized * 1 initialized tcnt_3 initialized ? ? ? ? initialized * 1 initialized tgra_3 initialized ? ? ? ? initialized * 1 initialized tgrb_3 initialized ? ? ? ? initialized * 1 initialized tgrc_3 initialized ? ? ? ? initialized * 1 initialized tgrd_3 initialized ? ? ? ? initialized * 1 initialized note: * not initialized in deep software standby mode but initialized by the internal reset when deep software standby mode is released. section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1047 of 1102 rej09b0365-0100 section 26 electrical characteristics 26.1 absolute maximum ratings table 26.1 absolute maximum ratings item symbol value unit power supply voltage v cc pllv cc ?0.3 to +4.6 v input voltage (except for port 5) v in ?0.3 to v cc +0.3 v input voltage (port 5) v in ?0.3 to av cc +0.3 v reference power supply voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +4.6 v analog input voltage v an ?0.3 to av cc +0.3 v regular specifications: ?20 to +75 * operating temperature t opr wide-range specifications: ?40 to +85 * c storage temperature t stg ?55 to +125 c caution: permanent damage to the lsi may resu lt if absolute maximum ratings are exceeded. note: * the operating temperature range during prog ramming/erasing of the flash memory is 0 c to +75 c for regular specifications and 0 c to +85 c for wide-range specifications. section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1048 of 1102 rej09b0365-0100 26.2 dc characteristics table 26.2 dc characteristics (1) conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v* 1 , t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit test conditions vt ? v cc 0.2 ? ? v vt + ? ? v cc 0.7 v schmitt trigger input voltage irq input pin, tpu input pin, tmr input pin, iic2 input pin, port 2, port 3, port j, port k vt + ? vt ? v cc 0.06 ? ? v irq0 -b to irq7 - b input pins vt ? av cc 0.2 ? ? v vt + ? ? av cc 0.7 v vt + ? vt ? av cc 0.06 ? ? v md, res , stby , emle, nmi v ih v cc 0.9 ? v cc + 0.3 extal other input pins v cc 0.7 ? v cc + 0.3 input high voltage (except schmitt trigger input pin) port 5 av cc 0.7 ? av cc + 0.3 v md, res , stby , emle v il ?0.3 ? v cc 0.1 extal, nmi ?0.3 ? v cc 0.2 input low voltage (except schmitt trigger input pin) other input pins ?0.3 ? v cc 0.2 v all output pins v oh v cc ? 0.5 ? ? v i oh = ?200 a output high voltage v cc ? 1.0 ? ? i oh = ?1 ma all output pins v ol ? ? 0.4 v i ol = 1.6 ma output low voltage port 3 ? ? 1.0 i ol = 10 ma res |i in | ? ? 10.0 a input leakage current md, stby , emle, nmi ? ? 1.0 v in = 0.5 to v cc ? 0.5 v port 5 ? ? 1.0 v in = 0.5 to av cc ? 0.5 v section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1049 of 1102 rej09b0365-0100 table 26.2 dc characteristics (2) conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v* 1 , t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit test conditions three-state leakage current (off state) ports 1, 2, 3, 6, a to k | i tsi | ? ? 1.0 a v in = 0.5 to v cc ? 0.5 v input pull-up mos current ports d to f, h, i ?i p 10 ? 300 a v cc = 3.0 to 3.6 v v in = 0 v input capacitance all input pins c in ? ? 15 pf v in = 0 v f = 1 mhz t a = 25 c normal operation i cc * 4 ? 50 80 ma f = 50 mhz sleep mode ? 45 52 ? 0.15 1.1 ma t a 50 c software standby mode * 3 ? 3.5 50c < t a ? 20 60 a t a 50 c deep software standby mode ram retained * 3 ? ? 200 50c < t a ? 3 8 a t a 50 c current consumption * 2 standby mode ram power supply halted ? ? 26 50c < t a 2 7 ma t a 50 c hardware standby mode ? ? 27 50c < t a all-module-clock- stop mode * 5 ? 23 30 ma during a/d and d/a conversion ai cc ? 1.0 2.5 ma analog power supply current standby for a/d and d/a conversion ? 0.5 1.0 a section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1050 of 1102 rej09b0365-0100 item symbol min. typ. max. unit test conditions during a/d and d/a conversion ai cc ? 0.5 1.0 ma reference power supply current standby for a/d and d/a conversion ? 0.5 1.0 a ram standby voltage v ram 2.5 ? ? v vcc start voltage * 7 v ccstart ? ? 0.8 v vcc rising gradient * 7 sv cc ? ? 20 ms/v notes: 1. when the a/d and d/a c onverters are not used, the av cc , v ref , and av ss pins should not be open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current consumption values are for v ih min = v cc ? 0.5 v and v il max = 0.5 v with all output pins unloaded and all input pull-up moss in the off state. 3. the values are for v ram v cc < 3.0 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on f as follows: i cc max = 25 (ma) + 1.1 (ma/mhz) f (normal operation) i cc max = 27 (ma) + 0.5 (ma/mhz) f (sleep mode) 5. the values are for reference. 6. this can be applied when the res pin is held low at power-on. table 26.3 permissible output currents conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v*, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit permissible output low current (per pin) output pins except port 3 i ol ? ? 2.0 ma permissible output low current (per pin) port 3 i ol ? ? 10 ma permissible output low current (total) total of all output pins i ol ? ? 80 ma permissible output high current (per pin) all output pins ?i oh ? ? 2.0 ma permissible output high current (total) total of all output pins ?i oh ? ? 40 ma caution: to protect the lsi's re liability, do not exceed the output current values in table 26.3. note: * when the a/d and d/a conver ters are not used, the av cc , v ref , and av ss pins should not be open. connect the av cc and v ref pins to v cc , and the av ss pin to v ss . section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1051 of 1102 rej09b0365-0100 26.3 ac characteristics lsi output pin c rh rl 3 v c = 30 pf rl = 2.4 k ? rh = 12 k ? input/output timing measurement level: 1.5 v (v cc = 3.0 v to 3.6 v) figure 26.1 output load circuit 26.3.1 clock timing table 26.4 clock timing conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, i = 8 mhz to 50 mhz, b = 8 mhz to 50 mhz, p = 8 mhz to 35 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit. test conditions clock cycle time t cyc 20 125 ns figure 26.2 clock high pulse width t ch 5 ? ns clock low pulse width t cl 5 ? ns clock rising time t cr ? 5 ns clock falling time t cf ? 5 ns oscillation settling time after reset (crystal) t osc1 10 ? ms figure 26.4 oscillation settling time after leaving software standby mode (crystal) t osc2 10 ? ms figure 26.3 section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1052 of 1102 rej09b0365-0100 item symbol min. max. unit. test conditions external clock output delay settling time t dext 1 ? ms figure 26.4 external clock input low pulse width t exl 27.7 ? ns figure 26.5 external clock input high pulse width t exh 27.7 ? ns external clock rising time t exr ? 5 ns external clock falling time t exf ? 5 ns t cyc b t ch t cf t cl t cr figure 26.2 external bus clock timing oscillator software standby mode (power-down mode) oscillation settling time t osc2 i nmi nmi exception handling nmieg = 1 ssby = 1 nmi exception handling sleep instruction nmieg ssby figure 26.3 oscillation settling ti ming after software standby mode section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1053 of 1102 rej09b0365-0100 extal v cc stby res i t dext t osc1 t dext t osc1 figure 26.4 oscillation settling timing extal vcc 0.5 t exr t exh t exl t exf figure 26.5 external input clock timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1054 of 1102 rej09b0365-0100 26.3.2 control signal timing table 26.5 control signal timing conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, i = 8 mhz to 50 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 26.6 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 26.7 nmi hold time t nmih 10 ? ns nmi pulse width (after leaving software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (after leaving software standby mode) t irqw 200 ? ns i res t ress t ress t resw figure 26.6 reset input timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1055 of 1102 rej09b0365-0100 i nmi irqi * (i = 0 to 15) irq * (edge input) note: * ssier must be set to cancel software standby mode. irq * (level input) t nmis t nmih t irqs t irqs t irqh t nmiw t irqw figure 26.7 interrupt input timing 26.3.3 bus timing table 26.6 bus timing (1) conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, b = 8 mhz to 50 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions address delay time t ad ? 15 ns address setup time 1 t as1 0.5 t cyc ? 8 ? ns figures 26.8 to 26.34 address setup time 2 t as2 1.0 t cyc ? 8 ? ns address setup time 3 t as3 1.5 t cyc ? 8 ? ns address setup time 4 t as4 2.0 t cyc ? 8 ? ns address hold time 1 t ah1 0.5 t cyc ? 8 ? ns address hold time 2 t ah2 1.0 t cyc ? 8 ? ns address hold time 3 t ah3 1.5 t cyc ? 8 ? ns section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1056 of 1102 rej09b0365-0100 item symbol min. max. unit test conditions cs delay time 1 t csd1 ? 15 ns as delay time t asd ? 15 ns rd delay time 1 t rsd1 ? 15 ns rd delay time 2 t rsd2 ? 15 ns read data setup time 1 t rds1 15 ? ns read data setup time 2 t rds2 15 ? ns figures 26.8 to 26.34 read data hold time 1 t rdh1 0.0 ? ns read data hold time 2 t rdh2 0.0 ? ns read data access time 2 t ac2 ? 1.5 t cyc ? 20 ns read data access time 4 t ac4 ? 2.5 t cyc ? 20 ns read data access time 5 t ac5 ? 1.0 t cyc ? 20 ns read data access time 6 t ac6 ? 2.0 t cyc ? 20 ns read data access time (from address) 1 t aa1 ? 1.0 t cyc ? 20 ns read data access time (from address) 2 t aa2 ? 1.5 t cyc ? 20 ns read data access time (from address) 3 t aa3 ? 2.0 t cyc ? 20 ns read data access time (from address) 4 t aa4 ? 2.5 t cyc ? 20 ns read data access time (from address) 5 t aa5 ? 3.0 t cyc ? 20 ns section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1057 of 1102 rej09b0365-0100 table 26.6 bus timing (2) conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, b = 8 mhz to 50 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions wr delay time 1 t wrd1 ? 15 ns wr delay time 2 t wrd2 ? 15 ns figures 26.8 to 26.34 wr pulse width 1 t wsw1 1.0 t cyc ? 13 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 13 ? ns write data delay time t wdd ? 20 ns write data setup time 1 t wds1 0.5 t cyc ? 13 ? ns write data setup time 2 t wds2 1.0 t cyc ? 13 ? ns write data setup time 3 t wds3 1.5 t cyc ? 13 ? ns write data hold time 1 t wdh1 0.5 t cyc ? 8 ? ns write data hold time 3 t wdh3 1.5 t cyc ? 8 ? ns byte control delay time t ubd ? 15 ns figures 26.13, 26.14 byte control pulse width 1 t ubw1 ? 1.0 t cyc ? 15 ns figure 26.13 byte control pulse width 2 t ubw2 ? 2.0 t cyc ? 15 ns figure 26.14 multiplexed address delay time 1 t mad1 ? 15 ns multiplexed address hold time t mah 1.0 t cyc ? 15 ? ns figures 26.17, 26.18 multiplexed address setup time 1 t mas1 0.5 t cyc ? 15 ? ns multiplexed address setup time 2 t mas2 1.5 t cyc ? 15 ? ns address hold delay time t ahd ? 15 ns address hold pulse width 1 t ahw1 1.0 t cyc ? 15 ? ns address hold pulse width 2 t ahw2 2.0 t cyc ? 15 ? ns wait setup time t wts 15 ? ns wait hold time t wth 5.0 ? ns figures 26.10, 26.18 breq setup time t breqs 20 ? ns figure 26.33 back delay time t bacd ? 15 ns bus floating time t bzd ? 30 ns breqo delay time t brqod ? 15 ns figure 26.34 bs delay time t bsd 1.0 15 ns rd/ wr delay time t rwd ? 15 ns figures 26.8, 26.9, 26.11 to 26.14 section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1058 of 1102 rej09b0365-0100 t1 t2 t ad t csd1 t rwd t rwd t as1 t bsd t bsd t as1 t as1 t as1 t rsd1 t rsd1 t ac5 t aa2 t rsd1 t wrd2 t wsw1 t wdh1 t wdd t dacd1 t dacd2 t wrd2 t ah1 t ac2 t rds2 t rdh2 t aa3 t rsd2 t rds1 t rdh1 t ah1 t asd t asd t rwd t rwd t dacd2 t dacd2 t rwd t rwd b a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 26.8 basic bus timing: two-state access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1059 of 1102 rej09b0365-0100 t1 t2 t3 t ad t as1 t ah1 t rsd1 t rds1 t rdh1 t rsd2 t rds2 t rdh2 t asd t asd t rsd1 t rsd1 t ac6 t ac4 t aa5 t as2 t wdd t wsw2 t wdh1 t wds1 t dacd1 t dacd2 t dacd2 t dacd2 t wrd1 t wrd2 t ah1 t aa4 t as1 t as1 t csd1 t rwd t rwd t bsd t bsd t rwd t rwd t rwd t rwd b a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 26.9 basic bus timing: three-state access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1060 of 1102 rej09b0365-0100 t1 b a23 to a0 cs7 to cs0 as bs rd/ wr rd d15 to d0 rd d15 to d0 lhwr , llwr d15 to d0 wait t wts t wth t wts t wth t2 tw t3 read (rdnn = 1) read (rdnn = 0) write rd/ wr rd/ wr figure 26.10 basic bus timing : three-state access, one wait section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1061 of 1102 rej09b0365-0100 th t ad t csd1 t as1 t asd t as3 t rsd1 t ac5 t rds1 t rdh1 t ah2 t ah3 t wdh3 t wsw1 t wds2 t wdd t as3 t wrd2 t wrd2 t rsd2 t rsd1 t ac2 t rds2 t rdh2 t as3 t rsd1 t ah3 t ah1 t asd t1 t2 tt t rwd t rwd t rwd t bsd t bsd t rwd t rwd t rwd t dacd1 t dacd2 t dacd2 t dacd2 b a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 26.11 basic bus timing: two-state access ( cs assertion period extended) section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1062 of 1102 rej09b0365-0100 th t ad t csd1 t as1 t asd t as3 t rsd1 t rsd1 t asd t ah1 t ah3 t ah2 t ah3 t wdh3 t wsw2 t wds3 t as4 t as3 t rsd1 t wdd t wrd2 t wrd1 t ac4 t rds2 t rdh2 t rsd2 t ac6 t rds1 t rdh1 t1 t2 t3 tt t rwd t rwd t rwd t rwd t rwd t bsd t bsd t rwd t dacd2 t dacd1 t dacd2 t dacd2 b a23 to a0 cs7 to cs0 as rd d15 to d0 rd d15 to d0 read (rdnn = 1) read (rdnn = 0) write bs rd/ wr rd/ wr rd/ wr d15 to d0 (write) (dkc = 0) dack0 to dack3 (dkc = 1) dack0 to dack3 lhwr , llwr figure 26.12 basic bus timing: three-state access ( cs assertion period extended) section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1063 of 1102 rej09b0365-0100 t1 as bs rd/ wr t ad t csd1 t as1 t ah1 t ah1 t asd t asd t2 t bsd t ac5 t ac5 t aa2 t rwd t rwd t bsd rd rd/ wr rd t rsd1 t rsd1 t rds1 t rdh1 t ubw1 t ubd t rwd t wdd t wdh1 t rwd t ubd t as1 t as1 b a23 to a0 cs7 to cs0 read d15 to d0 lub , llb d15 to d0 (write) write high figure 26.13 byte control sr am: two-state read/write access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1064 of 1102 rej09b0365-0100 t1 t ad t csd1 t as1 t ah1 t asd t rwd t rwd t asd as bs rd/ wr rd rd/ wr rd t2 t3 t as1 t ah1 t as1 t rsd1 t ubd t rwd t wdd t wdh1 t rwd t ubd t rsd1 t rds1 t ac6 t ac6 t ubw2 t aa4 t rdh1 t bsd t bsd b a23 to a0 cs7 to cs0 lub , llb d15 to d0 d15 to d0 (write) read write high figure 26.14 byte control sram : three-state read/write access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1065 of 1102 rej09b0365-0100 t1 b a23 to a6, a0 a5 to a1 cs7 to cs0 as bs rd/ wr rd d15 to d0 high lhwr , llwr t2 t1 t ad t rsd2 t aa1 t rds2 t rdh2 t1 read figure 26.15 burst rom access timing: one-state burst access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1066 of 1102 rej09b0365-0100 t1 b a23 to a6, a0 a5 to a1 cs7 to cs0 as rd d15 to d0 lhwr , llwr t2 t3 t1 t ad t as1 t asd t aa3 t rsd2 t rds2 t rdh2 t asd t ah1 t2 read bs rd/ wr high figure 26.16 burst rom access timing: two-state burst access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1067 of 1102 rej09b0365-0100 tma1 t ad t ahd t ahw1 t wsw1 t ahd t mad1 t mah t rds2 t rdh2 b a23 to a0 cs7 to cs0 ah ( as ) tma2 t1 t2 rd/ wr bs rd d15 to d0 rd/ wr lhwr , llwr t mad1 t wdd t wdh1 d15 to d0 read write t mas1 t mah t mas1 dkc = 0 dkc = 1 dack3 to dack0 figure 26.17 address/data mult iplexed access timing (no wait) (basic, four-state access) section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1068 of 1102 rej09b0365-0100 tma1 tmaw tma2 t1 t2 tpw ttw t3 rd/ wr wait t ad t ahd t ahd t ahw2 t mas2 t mah rd rd/ wr t mad1 t rds2 t rdh2 t wdd t wds1 t wts t wth t wts t wth t wdh1 t mas2 t mah t mad1 a23 to a0 cs7 to cs0 ah ( as ) d15 to d0 read write d15 to d0 lhwr , llwr b figure 26.18 address/data multiple xed access timing (wait control) (address cycle program wait 1 + data cycle program wait 1 + data cycle pin wait 1) section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1069 of 1102 rej09b0365-0100 b breq t breqs t breqs t bacd t bzd t bacd t bzd back a23 to a0 cs7 to cs0 d15 to d0 as , rd, lhwr , llwr figure 26.19 external bus release timing b back t brqod t brqod breqo figure 26.20 external bus request output timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1070 of 1102 rej09b0365-0100 26.3.4 dmac timing table 26.7 dmac timing conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, b = 8 mhz to 50 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. max. unit test conditions dreq setup time t drqs 20 ? ns figure 26.35 dreq hold time t drqh 5 ? ns tend delay time t ted ? 15 ns figure 26.36 dack delay time 1 t dacd1 ? 15 ns dack delay time 2 t dacd2 ? 15 ns figures 26.37, 26.38 b dreq0 to dreq3 t drqs t drqh figure 26.21 dmac ( dreq ) input timing t1 t ted t ted b tend0 to tend3 t2 or t3 figure 26.22 dmac ( tend ) output timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1071 of 1102 rej09b0365-0100 t1 b a23 to a0 cs7 to cs0 as bs rd/ wr t dacd1 t dacd2 t dacd2 t dacd2 rd (read) d15 to d0 (read) lhwr , llwr (write) d15 to d0 (write) t2 dack0 to dack3 (dkc = 0) dack0 to dack3 (dkc = 1) figure 26.23 dmac single-addre ss transfer timing: two-state access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1072 of 1102 rej09b0365-0100 t1 t dacd1 t dacd2 b a23 to a0 cs7 to cs0 as rd (read) d15 to d0 (read) lhwr , llwr (write) d15 to d0 (write) t2 t3 t dacd2 t dacd2 dack0 to dack3 (dkc = 0) dack0 to dack3 (dkc = 1) bs rd/ wr figure 26.24 dmac single-address transfer timing: three-state access section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1073 of 1102 rej09b0365-0100 26.3.5 timing of on-chip peripheral modules table 26.8 timing of on-chip peripheral modules conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, p = 8 mhz to 35 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item symbol min. max. unit test conditions i/o ports output data delay time t pwd ? 40 ns figure 26.25 input data setup time t prs 25 ? ns input data hold time t prh 25 ? ns tpu timer output delay time t tocd ? 40 ns figure 26.26 timer input setup time t tics 25 ? ns timer clock input setup time t tcks 25 ? ns figure 26.27 single-edge setting t tckwh 1.5 ? t cyc timer clock pulse width both-edge setting t tckwl 2.5 ? t cyc ppg pulse output delay time t pod ? 40 ns figure 26.28 timer output delay time t tmod ? 40 ns figure 26.29 8-bit timer timer reset input setup time t tmrs 25 ? ns figure 26.30 timer clock input setup time t tmcs 25 ? ns figure 26.31 timer clock pulse width single-edge setting t tmcwh 1.5 ? t cyc both-edge setting t tmcwl 2.5 ? t cyc wdt overflow output delay time t wovd ? 40 ns figure 26.32 sci asynchronous t scyc 4 ? t cyc figure 26.33 input clock cycle clocked synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t cyc input clock fall time t sckf ? 1.5 t cyc section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1074 of 1102 rej09b0365-0100 item symbol min. max. unit test conditions sci transmit data delay time t txd ? 40 ns figure 26.34 receive data setup time (clocked synchronous) t rxs 40 ? ns receive data hold time (clocked synchronous) t rxh 40 ? ns a/d converter trigger input setup time t trgs 30 ? ns figure 26.35 iic2 scl input cycle time t scl 12 t cyc + 600 ? ns figure 26.36 scl input high pulse width t sclh 3 t cyc + 300 ? ns scl input low pulse width t scll 5 t cyc + 300 ? ns scl, sda input falling time t sf ? 300 ns scl, sda input spike pulse removal time t sp ? 1 t cyc ns sda input bus free time t buf 5 t cyc ? ns start condition input hold time t stah 3 t cyc ? ns retransmit start condition input setup time t stas 3 t cyc ? ns stop condition input setup time t stos 1 t cyc + 20 ? ns data input setup time t sdas 0 ? ns data input hold time t sdah 0 ? ns scl, sda capacitive load cb ? 400 pf scl, sda falling time t sf ? 300 ns section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1075 of 1102 rej09b0365-0100 item symbol min. max. unit test conditions boundary scan tck clock cycle time t tckcyc 50* ? ns figure 26.37 tck clock high level pulse width t tckh 20 ? ns tck clock low level pulse width t tckl 20 ? ns tck clock rising time t tckr ? 5 ns tck clock falling time t tckf ? 5 ns trst pulse width t trstw 20 ? tcyc figure 26.38 tms setup time t tmss 20 ? ns figure 26.39 tms hold time t tmsh 20 ? ns tdi setup time t tdis 20 ? ns tdi hold time t tdih 20 ? ns tdo data delay time t tdod ? 23 ns note: t tckcyc t tckcyc section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1076 of 1102 rej09b0365-0100 t1 t prs t prh t pwd t2 p ports 1, 2, 3, 5, 6, a, b, d to f, h to k (read) ports 1, 2, 3, 6, a, b, d to f, h to k (write) figure 26.25 i/o port input/output timing p output compare output * 1 input capture input * 2 t tocd t tics notes: 1. tioca0 to tioca11, tiocb0 to tiocb11, tiocc0, tiocc3, tiocc6, tiocc9, tiocd0, tiocd3, tiocd6, tiocd9 2. tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd, tiocd3 figure 26.26 tpu input/output timing p tclka to tclkd t tckwl t tckwh t tcks t tcks figure 26.27 tpu clock input timing p po31 to po0 t pod figure 26.28 ppg output timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1077 of 1102 rej09b0365-0100 p tmo0 to tmo3 t tmod figure 26.29 8-bit timer output timing p tmri0 to tmri3 t tmrs figure 26.30 8-bit timer reset input timing p tmci0 to tmci3 t tmcwl t tmcwh t tmcs t tmcs figure 26.31 8-bit timer clock input timing p wdtovf t wovd t wovd figure 26.32 wdt output timing sck0 to sck6 t sckw t sckr t sckf t scyc figure 26.33 sck clock input timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1078 of 1102 rej09b0365-0100 sck0 to sck6 t txd t rxs t rxh txd0 to txd6 (transmit data) rxd0 to rxd6 (receive data) figure 26.34 sci input/output timing: clocked synchronous mode p adtrg0 , adtrg1 t trgs figure 26.35 a/d converter ex ternal trigger input timing t buf t stah t stas t sp t stos t sclh t scll t sf t sr t scl t sdah t sdas p * p * s * s r * v ih v il sda0 to sda1 scl0 to scl1 note: s, p, and sr represent the following conditions: s: start condition p: stop condition sr: retransmit start condition figure 26.36 i 2 c bus interface 2 input/output timing (option) section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1079 of 1102 rej09b0365-0100 t tckl t tckh tck t tckf t tckcyc t tckr figure 26.37 boundary scan tck timing t trstw tck res trst figure 26.38 boundary scan trst timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1080 of 1102 rej09b0365-0100 t tmss t tmsh tck tms tdi tdo t tdis t tdih t tdod figure 26.39 boundary scan input/output timing section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1081 of 1102 rej09b0365-0100 26.4 a/d conversion characteristics table 26.9 a/d conversion characteristics conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, vref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, p = 8 mhz to 35 mhz, ta = ?20 c to +75 c (regular specifications), ta = ?40 c to +85 c (wide-range specifications) item min. typ. max. unit resolution 10 10 10 bit conversion time 2.7 ? ? s analog input capacitance ? ? 20 pf permissible signal source impedance ? ? 5 k ? nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 8.0 lsb 26.5 d/a conversion characteristics table 26.11 d/a conversion characteristics conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, p = 8 mhz to 35 mhz, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range specifications) item min. typ. max. unit test conditions resolution 8 8 8 bit conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 2.0 3.0 lsb 2-m ? resistive load ? ? 2.0 lsb 4-m ? resistive load section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1082 of 1102 rej09b0365-0100 26.6 flash memory characteristics table 26.12 flash memory characteristics conditions: v cc = pllv cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, operating temperature range during programming/erasing: t a = 0 c to +75 c (regular specifications), t a = 0 c to +85 c (wide-range specifications) item symbol min. typ. max. unit test conditions programming time * 1, * 2, * 4 t p ? 1 10 ms/128 bytes erasure time * 1, * 2, * 4 t e ? 40 130 ms/4 kbyte- block ? 300 800 ms/32 kbyte- block ? 600 1500 ms/64 kbyte- block programming time (total) * 1, * 2, * 4 tp ? 2.3 6 h8sx/1642 s/256 kbytes t a = 25 c, for all 0s ? 4.5 12 h8sx/1644 s/512 kbytes ? 9.0 24 h8sx/1648 s/1 m byte erasure time (total) * 1, * 2, * 4 te ? 2.3 6 h8sx/1642 s/256 kbytes t a = 25 c ? 4.5 12 h8sx/1644 s/512 kbytes ? 9.0 24 h8sx/1648 s/1 m byte programming, erasure time (total) * 1, * 2, * 4 tpe ? 4.6 12 h8sx/1642 s/256 kbytes t a = 25 c ? 9.0 24 h8sx/1644 s/512 kbytes ? 18.0 48 h8sx/1648 s/1 m byte overwrite count n wec 100 * 3 ? ? times data save time * 5 t drp 10 ? ? years section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1083 of 1102 rej09b0365-0100 notes: 1. programming time and erase time depend on data in the flash memory. 2. programming time and erase time do not include time for data transfer. 3. all the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to min. value). 4. characteristics when programming is performed within the min. value section 26 electrical characteristics rev. 1.00 sep. 13, 2007 page 1084 of 1102 rej09b0365-0100 appendix rev. 1.00 sep. 13, 2007 page 1085 of 1102 rej09b0365-0100 appendix a. port states in each pin state table a.1 port states in each pin state deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state port 1 all hi-z hi-z keep keep keep keep keep port 2 all hi-z hi-z keep keep keep keep keep port 3 all hi-z hi-z keep keep keep keep keep port 4 all hi-z hi-z hi-z hi-z hi-z hi-z keep p55 to p50 all hi-z hi-z hi-z hi-z hi-z hi-z keep p56/ an6/ da0/ irq6 -b all hi-z hi-z hi-z hi-z [daoe0 = 1] keep [daoe0 = 0] hi-z [daoe0 = 1] keep [daoe0 = 0] hi-z keep p57/ an7/ da1/ irq7 -b all hi-z hi-z hi-z hi-z [daoe1 = 1] keep [daoe1 = 0] hi-z [daoe1 = 1] keep [daoe1 = 0] hi-z keep p65 to p60 all hi-z hi-z keep keep keep keep keep [breqo output] hi-z [breqo output] hi-z [ breqo output] hi-z [ breqo output] hi-z [ bs output] keep [ bs output] hi-z [ bs output] keep [ bs output] hi-z pa0/ breqo / bs -a all hi-z hi-z [other than above] keep [other than above] keep [other than above] keep [other than above] keep [ breqo output] breqo [ bs output] hi-z [other than above] keep [ back output] hi-z [ back output] hi-z [ back output] hi-z [ back output] hi-z [rd/ wr -a output] keep [rd/ wr -a output] hi-z [rd/ wr -a output] keep [rd/ wr -a output] hi-z pa1/ back / (rd/ wr -a) all hi-z hi-z [other than above] keep [other than above] keep [other than above] keep [other than above] keep [ back output] back [rd/ wr -a output] hi-z [other than above] keep appendix rev. 1.00 sep. 13, 2007 page 1086 of 1102 rej09b0365-0100 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state pa2/ breq / wait all hi-z hi-z [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z [ wait input] hi-z [other than above] keep [ breq input] hi-z ( breq ) [ wait input] hi-z ( wait ) single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep pa3/ llwr / llb external extended mode (expe = 1) h hi-z h hi-z h hi-z hi-z single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep pa4/ lhwr / lub external extended mode (expe = 1) h hi-z [ lhwr , lub output] h [other than above] keep [ lhwr , lub output] hi-z [other than above] keep [ lhwr , lub output] h [other than above] keep [ lhwr , lub output] hi-z [other than above] keep [ lhwr , lub output] hi-z [other than above] keep pa5/ rd single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep external extended mode (expe = 1) h hi-z h hi-z h hi-z hi-z single-chip mode (expe = 0) hi-z hi-z pa6/ as / ah / bs -b external extended mode (expe = 1) h hi-z [ as , bs output] h [ ah output] l [other than above] keep [ as , ah , bs output] hi-z [other than above] keep [ as , bs output] h [ ah output] l [other than above] keep [ as , ah , bs output] hi-z [other than above] keep [ as , ah , bs output] hi-z [other than above] keep appendix rev. 1.00 sep. 13, 2007 page 1087 of 1102 rej09b0365-0100 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state pa7/b single-chip mode (expe = 0) hi-z hi-z external extended mode (expe = 1) clock output hi-z [clock output] h [other than above] keep [clock output] h [other than above] keep [clock output] h [other than above] keep [clock output] h [other than above] keep [clock output] clock output [other than above] keep single-chip mode (expe = 0) hi-z hi-z pb0/ cs0 / cs4 / cs5 -b external extended mode (expe = 1) h hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb1/ cs1 / cs2 -b/ cs5 -a/ cs6 -b/ cs7 -b all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb2/ cs2 -a/ cs6 -a all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb3/ cs3 / cs7 -a all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb4/ cs4 -b all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb5/ cs5 -b all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep appendix rev. 1.00 sep. 13, 2007 page 1088 of 1102 rej09b0365-0100 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state pb6/ cs6 -d/ (rd/ wr )/ adtrgh0 -b all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pb7/ cs7 -d all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep [ wait input] hi-z [ wait input] hi-z [ wait input] hi-z [ wait input] hi-z [ wait input] hi-z pc0/ cs3 -b/ wait -b/ adtrgh1 -b all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pc1/ cs4 -c/ cs5 -c all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep pc2 to pc5 all hi-z hi-z [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] h [other than above] keep [ cs output] hi-z [other than above] keep [ cs output] hi-z [other than above] keep appendix rev. 1.00 sep. 13, 2007 page 1089 of 1102 rej09b0365-0100 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state external extended mode (expe = 1) l hi-z keep hi-z keep hi-z hi-z rom enabled extended mode hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep port d single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep port e external extended mode (expe = 1) l hi-z keep hi-z keep hi-z hi-z rom enabled extended mode hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep external extended mode (expe = 1) l hi-z keep hi-z keep hi-z hi-z rom enabled extended mode hi-z hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep pf3 to pf0 single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep pf7 to pf4 external extended mode (expe = 1) l/ hi-z * hi-z keep [address output] hi-z [other than above] keep keep [address output] hi-z [other than above] keep [address output] hi-z [other than above] keep single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep appendix rev. 1.00 sep. 13, 2007 page 1090 of 1102 rej09b0365-0100 deep software standby mode iokeep = 1/0 software standby mode port name mcu operating mode reset hardware standby mode ope = 1 ope = 0 ope = 1 ope = 0 bus released state port h single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep external extended mode (expe = 1) hi-z hi-z hi-z hi-z hi-z hi-z hi-z port i single-chip mode (expe = 0) hi-z hi-z keep keep keep keep keep 8-bit bus mode hi-z hi-z keep keep keep keep keep external extended mode (expe = 1) 16-bit bus mode hi-z hi-z hi-z hi-z hi-z hi-z hi-z port j hi-z hi-z hi-z keep keep keep keep keep port k hi-z hi-z hi-z keep keep keep keep keep port n hi-z hi-z hi-z keep keep keep keep keep [legend] h: high-level output l: low-level output keep: input pins become high-impedanc e, output pins retain their state. hi-z: high impedance appendix rev. 1.00 sep. 13, 2007 page 1091 of 1102 rej09b0365-0100 b. product lineup product classification product model marking package (package code) h8sx/1642 r5f61642 r5f61642fpv plqp0144ka-a (fp-144lv)* h8sx/1644 r5f61644 r5f61644fpv plqp0144ka-a (fp-144lv)* h8sx/1648 r5f61648 r5f61648fpv plqp0144ka-a (fp-144lv)* note: * pb-free version appendix rev. 1.00 sep. 13, 2007 page 1092 of 1102 rej09b0365-0100 c. package dimensions for the package dimensions, data in the renesas ic package general catalog has priority. terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 20.1 20.0 19.9 d 20.1 20.0 19.9 e 1.4 a 2 22.2 22.0 21.8 22.2 22.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e figure c.1 package dimensions (fp-144lv) appendix rev. 1.00 sep. 13, 2007 page 1093 of 1102 rej09b0365-0100 d. treatment of unused pins the treatments of unused pins are listed in table d.1 table d.1 treatment of unused pins pin name mode 4 mode 5 mode 6 modes 3, 7 res (always used as a reset pin) stby ? connect this pin to vcc via a pull-up resistor emle ? connect this pin to vss via a pull-down resistor md2 to md0 (always used as mode pins) nmi ? connect this pin to vcc via a pull-up resistor extal (always used as a clock pin) xtal ? leave this pin open wdtovf ? leave this pin open port 1 port 2 port 3 port 6 pa2 to pa0 pb7 to pb1 port c pf7 to pf5 port j port k port n ? connect these pins to v cc via a pull-up resistor or to vss via a pull-down resistor, respectively ports 4, 5 ? connect these pins to avcc via a pull-up resistor or to avss via a pull-down resistor, respectively appendix rev. 1.00 sep. 13, 2007 page 1094 of 1102 rej09b0365-0100 pin name mode 4 mode 5 mode 6 modes 3,7 pa7 ? this pin is left open in the initial state for the b output. pa6 ? this pin is left open in the initial state for the as output. pa5 ? this pin is left open in the initial state for the rd output. pa4 ? this pin is left open in the initial state for the lhwr output. pa3 ? this pin is left open in the initial state for the llwr output. pb0 ? this pin is left open in the initial state for the cs0 output. port d port e pf4 to pf0 ? these pins are left open in the initial state for the address output. port h (used as a data bus) port i (used as a data bus) ? connect these pins to vcc via a pull-up resistor or to vss via a pull- down resistor, respectively, in the initial state for the general input. ? connect these pins to vcc via a pull-up resistor or to vss via a pull- down resistor, respectively vref ? connect this pin to avcc notes: 1. do not change the initial value (input-b uffer disabled) of pnicr, where n corresponds to an unused pin. 2. when the pin function is changed from its initial state, use a pull-up or pull-down resistor as needed. rev. 1.00 sep. 13, 2007 page 1095 of 1102 rej09b0365-0100 index numerics 0 output/1 output..................................... 515 0-output/1-output .................................... 515 16-bit access space.................................. 205 16-bit counter mode................................ 618 16-bit timer pulse unit (tpu) ................. 465 8-bit access space.................................... 204 8-bit timers (tmr) ................................. 593 a a/d conversion accuracy........................ 803 absolute accu racy................................... 803 acknowledge .......................................... 756 address error ............................................ 98 address map ............................................. 77 address modes........................................ 291 address/data multiplexed i/o interface.................................... 198, 233 all-module-clock-stop mode .......... 942, 965 area 0 ..................................................... 199 area 1 ..................................................... 200 area 2 ..................................................... 200 area 3 ..................................................... 201 area 4 ..................................................... 201 area 5 ..................................................... 202 area 6 ..................................................... 203 area 7 ..................................................... 203 area division........................................... 192 asynchronous mode ............................... 686 at-cut parallel-re sonance type............... 936 available output signal and settings in each port ............................................. 438 average transfer rate generator............... 640 b b clock output control........................... 987 basic bus interf ace .......................... 197, 207 big endian ............................................... 196 bit rate ..................................................... 668 bit synchronous circuit ........................... 770 block structure ........................................ 823 block transfer mode ........................ 297, 366 boot mode....................................... 820, 849 boundary scan commands ...................... 915 buffer operation ...................................... 520 burst access mode................................... 303 burst rom interface....................... 197, 228 bus access modes.................................... 302 bus arbitration......................................... 260 bus configuration.................................... 184 bus controller (bsc)............................... 159 bus cycle division ................................... 360 bus width ................................................ 195 bus-released state...................................... 68 byte control sram interface ......... 197, 220 c cascaded conn ection............................... 618 cascaded operation ................................. 524 chain transfer.......................................... 367 chip select signals................................... 193 clock pulse generator ............................. 931 clock synchronizati on cycle (tsy).......... 186 clocked synchronous mode .................... 703 communications protocol ....................... 882 compare match a ................................... 616 compare match b ................................... 617 compare match count mode ................... 619 compare match signal............................. 616 counter operation.................................... 512 rev. 1.00 sep. 13, 2007 page 1096 of 1102 rej09b0365-0100 cpu priority control function over dtc and dmac ............................................. 140 crc operation circuit ........................... 732 crystal reso nator..................................... 936 cycle steali ng mode................................ 302 d d/a converter ......................................... 809 data direction register ............................ 389 data register............................................ 390 data transfer controller (dtc) ............... 343 direct convention ................................... 711 dma controller (dmac)....................... 265 double-buffered structure....................... 686 download pass/fail result parameter....... 838 dtc vector address ................................ 355 dtc vector address offset ...................... 355 dual address mode.................................. 291 e endian and data alignment ..................... 204 endian format ......................................... 196 error protection ...................................... 874 error signal ............................................. 711 exception handling ................................... 91 exception-handling state .......................... 68 extended repeat area............................... 289 extended repeat area function ................ 304 extension of chip select ( cs ) assertion period...................................................... 217 external access bus................................. 184 external bus ............................................ 189 external bus clock (b ) .................. 185, 931 external bus interface ............................. 195 external clock......................................... 937 external interrupts .................................. 123 f flash erase block sel ect parameter.......... 847 flash memory ......................................... 817 flash multipurpose address area parameter ................................................ 845 flash multipurpose data destination parameter ................................................ 846 flash pass and fail parameter .................. 839 flash program/erase frequency parameter ........................................ 843, 857 free-running count operation.................. 513 frequency divider ........................... 931, 938 full address mode ................................... 353 full-scale error........................................ 803 g general illegal in structions ..................... 103 h hardware protection ............................... 873 hardware standby mode ................. 942, 982 i i/o ports .................................................. 379 i 2 c bus format......................................... 756 i 2 c bus interface2 (iic2)......................... 739 id code.................................................... 697 idle cycle................................................. 243 illegal instru ction .................................... 103 input buffer control register .................... 391 input capture function ............................. 516 internal interrupts.................................... 124 internal peripheral bus ............................ 184 internal system bus ................................. 184 interrupt .................................................. 100 interrupt control mode 0 ......................... 131 interrupt control mode 2 ......................... 133 rev. 1.00 sep. 13, 2007 page 1097 of 1102 rej09b0365-0100 interrupt controller.................................. 107 interrupt exception handling sequence ... 135 interrupt exception handling vector table ............................................. 125 interrupt response times.......................... 136 interrupt sources ..................................... 123 interrupt sources and vector address offsets ..................................................... 125 interval timer .......................................... 634 interval timer mode................................. 634 inverse convention.................................. 712 irqn interrupts ....................................... 123 j jtag interface ....................................... 773 l little endian............................................ 196 m mark state ....................................... 686, 727 master receive mode............................... 759 master transmit mode ............................. 757 mcu operating modes.............................. 69 memory mat configuration .................. 822 mode 2...................................................... 75 mode 4...................................................... 75 mode 5...................................................... 75 mode 6...................................................... 76 mode 7...................................................... 76 mode pin................................................... 69 multi-clock mode ................................... 963 multiprocessor bit................................... 697 multiprocessor communication function................................................... 697 n nmi interrupt.......................................... 123 noise canceler......................................... 765 nonlinearity error.................................... 803 non-overlapping pulse output................. 583 normal transfer mode ............................. 363 normal transfer mode ............................. 295 number of access cycles ....................... 197 o offset addition ........................................ 307 offset error.............................................. 803 on-board programming .......................... 849 on-board programming mode................. 817 on-chip baud rate generator.................... 689 on-chip rom disabled extended mode .... 69 on-chip rom enabled extended mode..... 69 open-drain control register ..................... 393 oscillator................................................. 936 output buffer control .............................. 393 output trigger.......................................... 582 overflow ......................................... 618, 632 p parity bit.................................................. 686 periodic count operation ......................... 513 peripheral module clock (p ).......... 185, 931 phase counting mode .............................. 531 pin assignments......................................... 10 pin functions ............................................. 17 pll circuit ...................................... 931, 938 port function controller ........................... 447 port register............................................. 390 power-down modes................................. 941 procedure program.................................. 867 processing states ....................................... 68 program execution state ............................ 68 program stop state..................................... 68 rev. 1.00 sep. 13, 2007 page 1098 of 1102 rej09b0365-0100 programmable pulse generator (ppg) .... 557 programmer mode .......................... 820, 880 programming/erasing interface............... 826 programming/erasing interface parameters............................................... 836 programming/erasing interface register .................................................... 829 protection................................................ 873 pull-up mos control register.................. 392 pwm modes ........................................... 526 q quantization error................................... 803 r ram....................................................... 815 read strobe ( rd ) timing......................... 216 register addresses ..................................... 992 register bits ........................................... 1008 register configuration in each port......... 388 registers abwcr ................163, 1000, 1020, 1038 adcr............................1005, 1026, 1044 adcsr..................782, 1005, 1026, 1044 addr............................1005, 1026, 1044 astcr ..................164, 1000, 1020, 1039 bcr1 .....................176, 1000, 1020, 1039 bcr2 .....................178, 1000, 1020, 1039 bromcr ..............181, 1000, 1021, 1039 brr .......................668, 1004, 1025, 1043 ccr ...................................................... 37 cpupcr................111, 1003, 1024, 1042 cra.................................................... 349 crb .................................................... 350 crccr....................733, 992, 1008, 1030 crcdir ..................734, 992, 1008, 1030 crcdor.................734, 992, 1008, 1030 csacr..................171, 1000, 1020, 1039 dacr ..................... 284, 999, 1016, 1037 dacr01 ............... 811, 1004, 1025, 1043 dadr0 ................. 810, 1004, 1025, 1043 dadr1 ................. 810, 1004, 1025, 1043 dar.................................................... 349 dbsr...................... 274, 999, 1016, 1037 ddar ..................... 271, 999, 1016, 1037 ddr.................................. 389, 996, 1013 dmdr .................... 275, 999, 1016, 1037 dmrsr .................. 290, 999, 1019, 1038 dofr...................... 272, 999, 1016, 1037 dpfr .................................................. 838 dpsbycr ........................................ 1001 dpsiegr.......................................... 1001 dpsier............................................. 1001 dpsifr............................................. 1001 dpswcr.......................................... 1001 dr......................... 390, 1003, 1024, 1042 dsar...................... 270, 999, 1016, 1037 dtccr ................. 351, 1003, 1024, 1042 dtcer ................. 350, 1003, 1023, 1042 dtcr...................... 273, 999, 1016, 1037 dtcvbr .............. 353, 1000, 1020, 1038 endiancr.......... 179, 1000, 1021, 1039 exr ...................................................... 38 fccs..................... 829, 1001, 1021, 1039 febs................................................... 847 fecs..................... 832, 1001, 1021, 1039 fkey.................... 833, 1001, 1021, 1039 fmats ............................................... 834 fmpar............................................... 845 fmpdr............................................... 846 fpcs ..................... 832, 1001, 1021, 1039 fpefeq...................................... 843, 857 fpfr ................................................... 839 ftdar ................. 835, 1001, 1021, 1039 general registers ................................... 35 iccra .................. 744, 1001, 1022, 1040 iccrb .................. 745, 1001, 1022, 1040 icdrr .................. 755, 1002, 1022, 1040 rev. 1.00 sep. 13, 2007 page 1099 of 1102 rej09b0365-0100 icdrs ................................................ 755 icdrt ...................755, 1002, 1022, 1040 icier.....................748, 1002, 1022, 1040 icmr.....................747, 1002, 1022, 1040 icr ......................... 391, 997, 1014, 1035 icsr ......................751, 1002, 1022, 1040 idlcr ...................174, 1000, 1020, 1039 ier.........................114, 1003, 1024, 1042 intcr ...................110, 1003, 1024, 1042 ipr.......................... 112, 999, 1019, 1038 ircr ........................ 685, 993, 1010, 1031 iscrh ...................116, 1000, 1020, 1038 iscrl....................116, 1000, 1020, 1038 isr.........................121, 1003, 1024, 1042 mac ..................................................... 39 mdcr .................... 70, 1000, 1021, 1039 mpxcr .................183, 1000, 1021, 1039 mra ................................................... 346 mrb ................................................... 347 mstpcra.............947, 1001, 1021, 1039 mstpcrb.............947, 1001, 1021, 1039 mstpcrc.............950, 1001, 1021, 1039 nderh .................563, 1004, 1025, 1043 nderl..................563, 1004, 1025, 1043 ndrh....................568, 1004, 1025, 1043 ndrl ....................568, 1004, 1025, 1043 odr........................ 393, 998, 1015, 1036 pc ......................................................... 36 pcr..................................................... 573 pcr (i/o port) ........ 392, 997, 1015, 1036 pcr (ppg).................... 1004, 1025, 1043 pfcr0 .................... 448, 998, 1015, 1036 pfcr1 .................... 448, 998, 1015, 1036 pfcr2 .................... 450, 998, 1015, 1036 pfcr4 .................... 451, 998, 1015, 1036 pfcr6 .................... 453, 998, 1015, 1036 pfcr7 .................... 454, 998, 1015, 1036 pfcr9 .................... 456, 998, 1015, 1036 pfcrb.................... 460, 998, 1015, 1036 pfcrc.................... 461, 998, 1015, 1036 pmr ...................... 575, 1004, 1025, 1043 podrh................. 566, 1004, 1025, 1043 podrl ................. 566, 1004, 1025, 1043 port .................... 390, 1003, 1024, 1042 ramer ................ 848, 1000, 1021, 1039 rdncr................. 170, 1000, 1020, 1039 rdr ...................... 647, 1004, 1025, 1043 rsr..................................................... 647 rstcsr................ 631, 1005, 1026, 1044 rstsr .................................................. 1001 sar............... 348, 754, 1002, 1022, 1040 sbr....................................................... 39 sbycr ................. 944, 1000, 1021, 1039 sckcr ................. 933, 1000, 1021, 1039 scmr ................... 667, 1005, 1025, 1043 scr....................... 652, 1004, 1025, 1043 sdbpr................................................ 915 sdbsr................................................ 916 sdid ................................................... 925 semr.................... 676, 1001, 1022, 1040 smr ...................... 648, 1004, 1025, 1043 sramcr.............. 180, 1000, 1021, 1039 ssier...................... 122, 998, 1015, 1036 ssr ....................... 658, 1004, 1025, 1043 syscr.................... 73, 1000, 1021, 1039 tccr .................... 604, 1005, 1027, 1044 tcnt .................................................. 509 tcnt (tmr)........ 601, 1005, 1027, 1044 tcnt (tpu)................. 1006, 1027, 1045 tcnt (wdt) ....... 629, 1005, 1026, 1044 tcora................. 601, 1005, 1026, 1044 tcorb ................. 602, 1005, 1027, 1044 tcr..................................................... 479 tcr (tmr) .......... 602, 1005, 1026, 1044 tcr (tpu) ................... 1006, 1027, 1045 tcsr (tmr) ........ 609, 1005, 1026, 1044 tcsr (wdt)........ 629, 1005, 1026, 1044 tdr ...................... 648, 1004, 1025, 1043 tgr ...................... 509, 1006, 1027, 1045 tier...................... 504, 1006, 1027, 1045 rev. 1.00 sep. 13, 2007 page 1100 of 1102 rej09b0365-0100 tior......................486, 1006, 1027, 1045 tmdr ...................484, 1006, 1027, 1045 tsr............................................. 505, 648 tsr (tpu).....................1006, 1027, 1045 tstr .....................510, 1005, 1027, 1044 tsyr.....................511, 1005, 1027, 1044 vbr...................................................... 39 wtcra.................165, 1000, 1020, 1039 wtcrb.................165, 1000, 1020, 1039 repeat transfer mode ...................... 296, 364 reset ......................................................... 94 reset state................................................. 68 resolution............................................... 803 s sample-and-hold circuit ......................... 798 scan mode .............................................. 795 serial communication interface (sci) .... 639 short address mode................................. 353 single address mode ............................... 292 single mode ............................................ 794 slave receive mode................................. 764 slave transmit mode ............................... 761 sleep instruction exception handling...... 102 sleep mode ..................................... 942, 964 slot illegal inst ructions ........................... 103 smart card interface................................ 710 software prot ection................................. 874 software standby mode .................. 942, 966 space state .............................................. 686 stack status after ex ception handling...... 104 standard serial communication interface specifications for boot mode................... 880 start bit ................................................... 686 state transition of tap controller........... 926 state tran sitions ........................................ 68 stop bit ................................................... 686 strobe assert/neg ate timing..................... 198 synchronous clearing ............................. 518 synchronous op eration............................ 518 synchronous pr esetting........................... 518 system clock (i ) ............................ 185, 931 t tap controller ........................................ 926 toggle output.......................................... 515 trace exception handling.......................... 97 transfer information ............................... 353 transfer information read skip function ........................................... 362 transfer information writeback skip function ................................................... 363 transfer modes ....................................... 295 transmit/receive data.............................. 686 trap instruction ex ception handling ....... 101 u user boot mat....................................... 822 user boot mode............................... 820, 863 user break controller (ubc)................... 147 user mat............................................... 822 user program mode ........................ 820, 853 v vector table address.................................. 92 vector table address offset........................ 92 w wait control ............................................ 214 watchdog timer (wdt).......................... 627 watchdog timer mode............................. 632 waveform output by compare match...... 514 write data buffer function....................... 258 rev. 1.00 sep. 13, 2007 page 1101 of 1102 rej09b0365-0100 write data buffer function for external data bus................................................... 258 write data buffer function for peripheral modules................................................... 259 rev. 1.00 sep. 13, 2007 page 1102 of 1102 rej09b0365-0100 renesas 32-bit cisc microcomputer hardware manual h8sx/1648 group publication date: rev.1.00, sep. 13, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 h8sx/1648 group hardware manual |
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